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git.saurik.com Git - apple/javascriptcore.git/blob - offlineasm/risc_arm64.rb
1 # Copyright (C) 2012 Apple Inc. All rights reserved.
3 # Redistribution and use in source and binary forms, with or without
4 # modification, are permitted provided that the following conditions
6 # 1. Redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer.
8 # 2. Redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution.
12 # THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS''
13 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
14 # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
15 # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS
16 # BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
17 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
18 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
19 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
20 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
21 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
22 # THE POSSIBILITY OF SUCH DAMAGE.
28 # This file contains utilities that should be in risc.rb if it wasn't for the
29 # fact that risc.rb is shared with the ARMv7 backend, and may be part of a
30 # code dump before ARM64 goes public.
32 # FIXME: when ARM64 goes public, we should merge this file into risc.rb
35 # Lowering of the not instruction. The following:
44 def riscLowerNot(list
)
48 if node
.is_a
? Instruction
51 raise "Wrong nubmer of operands at #{node.codeOriginString}" unless node
.operands
.size
== 1
52 suffix
= node
.opcode
[-1..-1]
53 newList
<< Instruction
.new(node
.codeOrigin
, "xor" + suffix
,
54 [Immediate
.new(node
.codeOrigin
, -1), node
.operands
[0]])
66 # Lowing of complex branch ops on 64-bit. For example:
68 # bmulio foo, bar, baz
72 # smulli foo, bar, bar
73 # rshiftp bar, 32, tmp1
74 # rshifti bar, 31, tmp2
76 # bineq tmp1, tmp2, baz
79 def riscLowerHardBranchOps64(list
)
83 if node
.is_a
? Instruction
and node
.opcode
== "bmulio"
84 tmp1
= Tmp
.new(node
.codeOrigin
, :gpr)
85 tmp2
= Tmp
.new(node
.codeOrigin
, :gpr)
86 newList
<< Instruction
.new(node
.codeOrigin
, "smulli", [node
.operands
[0], node
.operands
[1], node
.operands
[1]])
87 newList
<< Instruction
.new(node
.codeOrigin
, "rshiftp", [node
.operands
[1], Immediate
.new(node
.codeOrigin
, 32), tmp1
])
88 newList
<< Instruction
.new(node
.codeOrigin
, "rshifti", [node
.operands
[1], Immediate
.new(node
.codeOrigin
, 31), tmp2
])
89 newList
<< Instruction
.new(node
.codeOrigin
, "zxi2p", [node
.operands
[1], node
.operands
[1]])
90 newList
<< Instruction
.new(node
.codeOrigin
, "bineq", [tmp1
, tmp2
, node
.operands
[2]])
99 # Lowering of test instructions. For example:
108 # and another example:
118 def riscLowerTest(list
)
119 def emit(newList
, andOpcode
, branchOpcode
, node
)
120 if node
.operands
.size
== 2
121 newList
<< Instruction
.new(node
.codeOrigin
, branchOpcode
, [node
.operands
[0], Immediate
.new(node
.codeOrigin
, 0), node
.operands
[1]])
125 raise "Incorrect number of operands at #{codeOriginString}" unless node
.operands
.size
== 3
127 if node
.operands
[0].immediate
? and node
.operands
[0].value
== -1
128 newList
<< Instruction
.new(node
.codeOrigin
, branchOpcode
, [node
.operands
[1], Immediate
.new(node
.codeOrigin
, 0), node
.operands
[2]])
132 if node
.operands
[1].immediate
? and node
.operands
[1].value
== -1
133 newList
<< Instruction
.new(node
.codeOrigin
, branchOpcode
, [node
.operands
[0], Immediate
.new(node
.codeOrigin
, 0), node
.operands
[2]])
137 tmp
= Tmp
.new(node
.codeOrigin
, :gpr)
138 newList
<< Instruction
.new(node
.codeOrigin
, andOpcode
, [node
.operands
[0], node
.operands
[1], tmp
])
139 newList
<< Instruction
.new(node
.codeOrigin
, branchOpcode
, [tmp
, Immediate
.new(node
.codeOrigin
, 0), node
.operands
[2]])
145 if node
.is_a
? Instruction
148 emit(newList
, "andi", "bilt", node
)
150 emit(newList
, "andi", "bieq", node
)
152 emit(newList
, "andi", "bineq", node
)
154 emit(newList
, "andp", "bplt", node
)
156 emit(newList
, "andp", "bpeq", node
)
158 emit(newList
, "andp", "bpneq", node
)
160 emit(newList
, "andq", "bqlt", node
)
162 emit(newList
, "andq", "bqeq", node
)
164 emit(newList
, "andq", "bqneq", node
)
166 emit(newList
, "andi", "bblt", node
)
168 emit(newList
, "andi", "bbeq", node
)
170 emit(newList
, "andi", "bbneq", node
)
172 emit(newList
, "andi", "cilt", node
)
174 emit(newList
, "andi", "cieq", node
)
176 emit(newList
, "andi", "cineq", node
)
178 emit(newList
, "andp", "cplt", node
)
180 emit(newList
, "andp", "cpeq", node
)
182 emit(newList
, "andp", "cpneq", node
)
184 emit(newList
, "andq", "cqlt", node
)
186 emit(newList
, "andq", "cqeq", node
)
188 emit(newList
, "andq", "cqneq", node
)
190 emit(newList
, "andi", "cblt", node
)
192 emit(newList
, "andi", "cbeq", node
)
194 emit(newList
, "andi", "cbneq", node
)