dfg/DFGFPRInfo.h

   1 /*
   2  * Copyright (C) 2011 Apple Inc. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
  14  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  16  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
  17  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  18  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  19  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  20  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  21  * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  23  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 #ifndef DFGFPRInfo_h
  27 #define DFGFPRInfo_h
  28
  29 #if ENABLE(DFG_JIT)
  30
  31 #include <assembler/MacroAssembler.h>
  32 #include <dfg/DFGRegisterBank.h>
  33
  34 namespace JSC { namespace DFG {
  35
  36 typedef MacroAssembler::FPRegisterID FPRReg;
  37 #define InvalidFPRReg ((FPRReg)-1)
  38
  39 #if CPU(X86) || CPU(X86_64)
  40
  41 class FPRInfo {
  42 public:
  43     typedef FPRReg RegisterType;
  44     static const unsigned numberOfRegisters = 6;
  45
  46     // Temporary registers.
  47     static const FPRReg fpRegT0 = X86Registers::xmm0;
  48     static const FPRReg fpRegT1 = X86Registers::xmm1;
  49     static const FPRReg fpRegT2 = X86Registers::xmm2;
  50     static const FPRReg fpRegT3 = X86Registers::xmm3;
  51     static const FPRReg fpRegT4 = X86Registers::xmm4;
  52     static const FPRReg fpRegT5 = X86Registers::xmm5;
  53 #if CPU(X86_64)
  54     // Only X86_64 passes aguments in xmm registers
  55     static const FPRReg argumentFPR0 = X86Registers::xmm0; // fpRegT0
  56     static const FPRReg argumentFPR1 = X86Registers::xmm1; // fpRegT1
  57     static const FPRReg argumentFPR2 = X86Registers::xmm2; // fpRegT2
  58     static const FPRReg argumentFPR3 = X86Registers::xmm3; // fpRegT3
  59 #endif
  60     // On X86 the return will actually be on the x87 stack,
  61     // so we'll copy to xmm0 for sanity!
  62     static const FPRReg returnValueFPR = X86Registers::xmm0; // fpRegT0
  63
  64     // FPRReg mapping is direct, the machine regsiter numbers can
  65     // be used directly as indices into the FPR RegisterBank.
  66     COMPILE_ASSERT(X86Registers::xmm0 == 0, xmm0_is_0);
  67     COMPILE_ASSERT(X86Registers::xmm1 == 1, xmm1_is_1);
  68     COMPILE_ASSERT(X86Registers::xmm2 == 2, xmm2_is_2);
  69     COMPILE_ASSERT(X86Registers::xmm3 == 3, xmm3_is_3);
  70     COMPILE_ASSERT(X86Registers::xmm4 == 4, xmm4_is_4);
  71     COMPILE_ASSERT(X86Registers::xmm5 == 5, xmm5_is_5);
  72     static FPRReg toRegister(unsigned index)
  73     {
  74         return (FPRReg)index;
  75     }
  76     static unsigned toIndex(FPRReg reg)
  77     {
  78         return (unsigned)reg;
  79     }
  80
  81     static const char* debugName(FPRReg reg)
  82     {
  83         ASSERT(reg != InvalidFPRReg);
  84 #if CPU(X86_64)
  85         ASSERT(reg < 16);
  86         static const char* nameForRegister[16] = {
  87             "xmm0", "xmm1", "xmm2", "xmm3",
  88             "xmm4", "xmm5", "xmm6", "xmm7",
  89             "xmm8", "xmm9", "xmm10", "xmm11",
  90             "xmm12", "xmm13", "xmm14", "xmm15"
  91         };
  92 #elif CPU(X86)
  93         ASSERT(reg < 8);
  94         static const char* nameForRegister[8] = {
  95             "xmm0", "xmm1", "xmm2", "xmm3",
  96             "xmm4", "xmm5", "xmm6", "xmm7"
  97         };
  98 #endif
  99         return nameForRegister[reg];
 100     }
 101 };
 102
 103 #endif
 104
 105 #if CPU(ARM_THUMB2)
 106
 107 class FPRInfo {
 108 public:
 109     typedef FPRReg RegisterType;
 110     static const unsigned numberOfRegisters = 6;
 111
 112     // Temporary registers.
 113     // d7 is use by the MacroAssembler as fpTempRegister.
 114     static const FPRReg fpRegT0 = ARMRegisters::d0;
 115     static const FPRReg fpRegT1 = ARMRegisters::d1;
 116     static const FPRReg fpRegT2 = ARMRegisters::d2;
 117     static const FPRReg fpRegT3 = ARMRegisters::d3;
 118     static const FPRReg fpRegT4 = ARMRegisters::d4;
 119     static const FPRReg fpRegT5 = ARMRegisters::d5;
 120     // ARMv7 doesn't pass arguments in fp registers. The return
 121     // value is also actually in integer registers, for now
 122     // we'll return in d0 for simplicity.
 123     static const FPRReg returnValueFPR = ARMRegisters::d0; // fpRegT0
 124
 125     // FPRReg mapping is direct, the machine regsiter numbers can
 126     // be used directly as indices into the FPR RegisterBank.
 127     COMPILE_ASSERT(ARMRegisters::d0 == 0, d0_is_0);
 128     COMPILE_ASSERT(ARMRegisters::d1 == 1, d1_is_1);
 129     COMPILE_ASSERT(ARMRegisters::d2 == 2, d2_is_2);
 130     COMPILE_ASSERT(ARMRegisters::d3 == 3, d3_is_3);
 131     COMPILE_ASSERT(ARMRegisters::d4 == 4, d4_is_4);
 132     COMPILE_ASSERT(ARMRegisters::d5 == 5, d5_is_5);
 133     static FPRReg toRegister(unsigned index)
 134     {
 135         return (FPRReg)index;
 136     }
 137     static unsigned toIndex(FPRReg reg)
 138     {
 139         return (unsigned)reg;
 140     }
 141
 142     static const char* debugName(FPRReg reg)
 143     {
 144         ASSERT(reg != InvalidFPRReg);
 145         ASSERT(reg < 32);
 146         static const char* nameForRegister[32] = {
 147             "d0", "d1", "d2", "d3",
 148             "d4", "d5", "d6", "d7",
 149             "d8", "d9", "d10", "d11",
 150             "d12", "d13", "d14", "d15"
 151             "d16", "d17", "d18", "d19"
 152             "d20", "d21", "d22", "d23"
 153             "d24", "d25", "d26", "d27"
 154             "d28", "d29", "d30", "d31"
 155         };
 156         return nameForRegister[reg];
 157     }
 158 };
 159
 160 #endif
 161
 162 typedef RegisterBank<FPRInfo>::iterator fpr_iterator;
 163
 164 } } // namespace JSC::DFG
 165
 166 #endif
 167 #endif