i386/nasm/insns.h

   1 /*
   2  * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Portions Copyright (c) 1999 Apple Computer, Inc.  All Rights
   7  * Reserved.  This file contains Original Code and/or Modifications of
   8  * Original Code as defined in and that are subject to the Apple Public
   9  * Source License Version 1.1 (the "License").  You may not use this file
  10  * except in compliance with the License.  Please obtain a copy of the
  11  * License at http://www.apple.com/publicsource and read it before using
  12  * this file.
  13  *
  14  * The Original Code and all software distributed under the License are
  15  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  16  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  17  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT.  Please see the
  19  * License for the specific language governing rights and limitations
  20  * under the License.
  21  *
  22  * @APPLE_LICENSE_HEADER_END@
  23  */
  24 /* insns.h   header file for insns.c
  25  *
  26  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
  27  * Julian Hall. All rights reserved. The software is
  28  * redistributable under the licence given in the file "Licence"
  29  * distributed in the NASM archive.
  30  */
  31
  32 #ifndef NASM_INSNS_H
  33 #define NASM_INSNS_H
  34
  35 struct itemplate {
  36     int opcode;                        /* the token, passed from "parser.c" */
  37     int operands;                      /* number of operands */
  38     long opd[3];                       /* bit flags for operand types */
  39     char *code;                        /* the code it assembles to */
  40     int flags;                         /* some flags */
  41 };
  42
  43 /*
  44  * Instruction template flags. These specify which processor
  45  * targets the instruction is eligible for, whether it is
  46  * privileged or undocumented, and also specify extra error
  47  * checking on the matching of the instruction.
  48  *
  49  * IF_SM stands for Size Match: any operand whose size is not
  50  * explicitly specified by the template is `really' intended to be
  51  * the same size as the first size-specified operand.
  52  * Non-specification is tolerated in the input instruction, but
  53  * _wrong_ specification is not.
  54  *
  55  * IF_SM2 invokes Size Match on only the first _two_ operands, for
  56  * three-operand instructions such as SHLD: it implies that the
  57  * first two operands must match in size, but that the third is
  58  * required to be _unspecified_.
  59  *
  60  * IF_SB invokes Size Byte: operands with unspecified size in the
  61  * template are really bytes, and so no non-byte specification in
  62  * the input instruction will be tolerated. IF_SW similarly invokes
  63  * Size Word, and IF_SD invokes Size Doubleword.
  64  *
  65  * (The default state if neither IF_SM nor IF_SM2 is specified is
  66  * that any operand with unspecified size in the template is
  67  * required to have unspecified size in the instruction too...)
  68  */
  69
  70 #define IF_SM     0x0001               /* size match */
  71 #define IF_SM2    0x0002               /* size match first two operands */
  72 #define IF_SB     0x0004               /* unsized operands can't be non-byte */
  73 #define IF_SW     0x0008               /* unsized operands can't be non-word */
  74 #define IF_SD     0x0010               /* unsized operands can't be nondword */
  75 #define IF_8086   0x0000               /* 8086 instruction */
  76 #define IF_186    0x0100               /* 186+ instruction */
  77 #define IF_286    0x0200               /* 286+ instruction */
  78 #define IF_386    0x0300               /* 386+ instruction */
  79 #define IF_486    0x0400               /* 486+ instruction */
  80 #define IF_PENT   0x0500               /* Pentium instruction */
  81 #define IF_P6     0x0600               /* P6 instruction */
  82 #define IF_CYRIX  0x0800               /* Cyrix-specific instruction */
  83 #define IF_PMASK  0x0F00               /* the mask for processor types */
  84 #define IF_PRIV   0x1000               /* it's a privileged instruction */
  85 #define IF_UNDOC  0x2000               /* it's an undocumented instruction */
  86 #define IF_FPU    0x4000               /* it's an FPU instruction */
  87 #define IF_MMX    0x8000               /* it's an MMX instruction */
  88
  89 #endif