/*
- * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
*
- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
- * compliance with the License. Please obtain a copy of the License at
- * http://www.opensource.apple.com/apsl/ and read it before using this
- * file.
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.
+ *
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* Please see the License for the specific language governing rights and
* limitations under the License.
*
- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
/*
* CR4
*/
+#define CR4_VMXE 0x00002000 /* Enable VMX operation */
#define CR4_FXS 0x00000200 /* SSE/SSE2 OS supports FXSave */
#define CR4_XMM 0x00000400 /* SSE/SSE2 instructions supported in OS */
#define CR4_PGE 0x00000080 /* p6: Page Global Enable */
__asm__ volatile("mov %0, %%cr3" : : "r" (value));
}
-/* Implemented in locore: */
-extern uint32_t get_cr4(void);
-extern void set_cr4(uint32_t);
+static inline uint32_t get_cr4(void)
+{
+ uint32_t cr4;
+ __asm__ volatile("mov %%cr4, %0" : "=r" (cr4));
+ return(cr4);
+}
+
+static inline void set_cr4(uint32_t value)
+{
+ __asm__ volatile("mov %0, %%cr4" : : "r" (value));
+}
static inline void clear_ts(void)
{
__asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg)));
}
-static inline unsigned short get_ldt(void)
+static inline unsigned short sldt(void)
{
unsigned short seg;
__asm__ volatile("sldt %0" : "=rm" (seg));
return(seg);
}
-static inline void set_ldt(unsigned int seg)
+static inline void lldt(unsigned int seg)
{
__asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg)));
}
+#ifdef MACH_KERNEL_PRIVATE
+extern void flush_tlb64(void);
+extern uint64_t get64_cr3(void);
+extern void set64_cr3(uint64_t);
static inline void flush_tlb(void)
{
unsigned long cr3_temp;
+ if (cpu_mode_is64bit()) {
+ flush_tlb64();
+ return;
+ }
__asm__ volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (cr3_temp) :: "memory");
}
+#endif /* MACH_KERNEL_PRIVATE */
static inline void wbinvd(void)
{
__asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
#define rdtsc(lo,hi) \
- __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi))
+ __asm__ volatile("rdtsc; lfence" : "=a" (lo), "=d" (hi))
#define write_tsc(lo,hi) wrmsr(0x10, lo, hi)
static inline uint64_t rdtsc64(void)
{
uint64_t ret;
- __asm__ volatile("rdtsc" : "=A" (ret));
+ __asm__ volatile("rdtsc; lfence" : "=A" (ret));
return ret;
}
#define MSR_IA32_APIC_BASE_ENABLE (1<<11)
#define MSR_IA32_APIC_BASE_BASE (0xfffff<<12)
+#define MSR_IA32_FEATURE_CONTROL 0x3a
+#define MSR_IA32_FEATCTL_LOCK (1<<0)
+#define MSR_IA32_FEATCTL_VMXON_SMX (1<<1)
+#define MSR_IA32_FEATCTL_VMXON (1<<2)
+#define MSR_IA32_FEATCTL_CSTATE_SMI (1<<16)
+
#define MSR_IA32_UCODE_WRITE 0x79
#define MSR_IA32_UCODE_REV 0x8b
#define MSR_IA32_PERFCTR0 0xc1
#define MSR_IA32_PERFCTR1 0xc2
+#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+
#define MSR_IA32_BBL_CR_CTL 0x119
+#define MSR_IA32_SYSENTER_CS 0x174
+#define MSR_IA32_SYSENTER_ESP 0x175
+#define MSR_IA32_SYSENTER_EIP 0x176
+
#define MSR_IA32_MCG_CAP 0x179
#define MSR_IA32_MCG_STATUS 0x17a
#define MSR_IA32_MCG_CTL 0x17b
#define MSR_IA32_EVNTSEL0 0x186
#define MSR_IA32_EVNTSEL1 0x187
+#define MSR_IA32_PERF_STS 0x198
+#define MSR_IA32_PERF_CTL 0x199
+
#define MSR_IA32_MISC_ENABLE 0x1a0
#define MSR_IA32_DEBUGCTLMSR 0x1d9
#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
+#define MSR_IA32_VMX_BASE 0x480
+#define MSR_IA32_VMX_BASIC MSR_IA32_VMX_BASE
+#define MSR_IA32_VMXPINBASED_CTLS MSR_IA32_VMX_BASE+1
+#define MSR_IA32_PROCBASED_CTLS MSR_IA32_VMX_BASE+2
+#define MSR_IA32_VMX_EXIT_CTLS MSR_IA32_VMX_BASE+3
+#define MSR_IA32_VMX_ENTRY_CTLS MSR_IA32_VMX_BASE+4
+#define MSR_IA32_VMX_MISC MSR_IA32_VMX_BASE+5
+#define MSR_IA32_VMX_CR0_FIXED0 MSR_IA32_VMX_BASE+6
+#define MSR_IA32_VMX_CR0_FIXED1 MSR_IA32_VMX_BASE+7
+#define MSR_IA32_VMX_CR4_FIXED0 MSR_IA32_VMX_BASE+8
+#define MSR_IA32_VMX_CR4_FIXED1 MSR_IA32_VMX_BASE+9
+
+#define MSR_IA32_EFER 0xC0000080
+#define MSR_IA32_EFER_SCE 0x00000001
+#define MSR_IA32_EFER_LME 0x00000100
+#define MSR_IA32_EFER_LMA 0x00000400
+#define MSR_IA32_EFER_NXE 0x00000800
+
+#define MSR_IA32_STAR 0xC0000081
+#define MSR_IA32_LSTAR 0xC0000082
+#define MSR_IA32_CSTAR 0xC0000083
+#define MSR_IA32_FMASK 0xC0000084
+
+#define MSR_IA32_FS_BASE 0xC0000100
+#define MSR_IA32_GS_BASE 0xC0000101
+#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
+
+#define MSR_IA32_BIOS_SIGN_ID 0x08B
+
#endif /* _I386_PROC_REG_H_ */
projects / apple / xnu.git / blobdiff