xnu-7195.81.3.tar.gz

[apple/xnu.git] / osfmk / arm / proc_reg.h

diff --git a/osfmk/arm/proc_reg.h b/osfmk/arm/proc_reg.h
index c04e0f478782456f97d1556b87ce5ca217bc70bd..0ebbf526bc9c96bb082c3f84d60000ab3f813752 100644 (file)
--- a/osfmk/arm/proc_reg.h
+++ b/osfmk/arm/proc_reg.h
@@ -297,7 +297,26 @@
 #define MMU_I_CLINE     5                      /* cache line size as 1<<MMU_I_CLINE (32) */
 
 /* D-Cache */
+#define MMU_CSIZE       15                     /* cache size as 1<<MMU_CSIZE (32K) */
 #define MMU_CLINE       6                      /* cache line size as 1<<MMU_CLINE (64) */
+#define MMU_NWAY        2                      /* set associativity 1<<MMU_NWAY (4) */
+#define MMU_I7SET       6                      /* cp15 c7 set incrementer 1<<MMU_I7SET */
+#define MMU_I7WAY       30                     /* cp15 c7 way incrementer 1<<MMU_I7WAY */
+
+#define MMU_SWAY        (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
+#define MMU_NSET        (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
+
+#define __ARM_L2CACHE__ 1
+
+#define L2_CSIZE        20                       /* cache size as 1<<MMU_CSIZE */
+#define L2_CLINE        6                        /* cache line size as 1<<MMU_CLINE (64) */
+#define L2_NWAY         3                        /* set associativity 1<<MMU_NWAY (8) */
+#define L2_I7SET        6                        /* cp15 c7 set incrementer 1<<MMU_I7SET */
+#define L2_I7WAY        29                       /* cp15 c7 way incrementer 1<<MMU_I7WAY */
+#define L2_I9WAY        29                       /* cp15 c9 way incrementer 1<<MMU_I9WAY */
+
+#define L2_SWAY         (L2_CSIZE - L2_NWAY)     /* set size 1<<MMU_SWAY */
+#define L2_NSET         (L2_SWAY - L2_CLINE)     /* lines per way 1<<MMU_NSET */
 
 #elif defined (APPLETYPHOON)
 
@@ -347,6 +366,14 @@
 /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */
 #define MMU_CLINE   6                      /* cache line size is 1<<MMU_CLINE (64) */
 
+#elif defined (APPLEFIRESTORM)
+
+/* I-Cache, 256KB for Firestorm, 128KB for Icestorm, 6-way. */
+#define MMU_I_CLINE 6                      /* cache line size as 1<<MMU_I_CLINE (64) */
+
+/* D-Cache, 160KB for Firestorm, 8-way. 64KB for Icestorm, 6-way. */
+#define MMU_CLINE   6                      /* cache line size is 1<<MMU_CLINE (64) */
+
 #elif defined (BCM2837) /* Raspberry Pi 3 */
 
 /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */