+/*!
+ * @typedef ml_topology_cpu_t
+ * @brief Describes one CPU core in the topology.
+ *
+ * @field cpu_id Logical CPU ID (EDT: cpu-id): 0, 1, 2, 3, 4, ...
+ * @field phys_id Physical CPU ID (EDT: reg). Same as MPIDR[15:0], i.e.
+ * (cluster_id << 8) | core_number_within_cluster
+ * @field cluster_id Cluster ID (EDT: cluster-id)
+ * @field die_id Die ID (EDT: die-id)
+ * @field cluster_type The type of CPUs found in this cluster.
+ * @field l2_access_penalty Indicates that the scheduler should try to de-prioritize a core because
+ * L2 accesses are slower than on the boot processor.
+ * @field l2_cache_size Size of the L2 cache, in bytes. 0 if unknown or not present.
+ * @field l2_cache_id l2-cache-id property read from EDT.
+ * @field l3_cache_size Size of the L3 cache, in bytes. 0 if unknown or not present.
+ * @field l3_cache_id l3-cache-id property read from EDT.
+ * @field cpu_IMPL_regs IO-mapped virtual address of cpuX_IMPL (implementation-defined) register block.
+ * @field cpu_IMPL_pa Physical address of cpuX_IMPL register block.
+ * @field cpu_IMPL_len Length of cpuX_IMPL register block.
+ * @field cpu_UTTDBG_regs IO-mapped virtual address of cpuX_UTTDBG register block.
+ * @field cpu_UTTDBG_pa Physical address of cpuX_UTTDBG register block, if set in DT, else zero
+ * @field cpu_UTTDBG_len Length of cpuX_UTTDBG register block, if set in DT, else zero
+ * @field coresight_regs IO-mapped virtual address of CoreSight debug register block.
+ * @field coresight_pa Physical address of CoreSight register block.
+ * @field coresight_len Length of CoreSight register block.
+ * @field self_ipi_irq AIC IRQ vector for self IPI (cpuX->cpuX). 0 if unsupported.
+ * @field other_ipi_irq AIC IRQ vector for other IPI (cpuX->cpuY). 0 if unsupported.
+ * @field pmi_irq AIC IRQ vector for performance management IRQ. 0 if unsupported.
+ * @field die_cluster_id Cluster ID within the local die (EDT: die-cluster-id)
+ * @field cluster_core_id Core ID within the local cluster (EDT: cluster-core-id)
+ */
+typedef struct ml_topology_cpu {
+ unsigned int cpu_id;
+ uint32_t phys_id;
+ unsigned int cluster_id;
+ unsigned int die_id;
+ cluster_type_t cluster_type;
+ uint32_t l2_access_penalty;
+ uint32_t l2_cache_size;
+ uint32_t l2_cache_id;
+ uint32_t l3_cache_size;
+ uint32_t l3_cache_id;
+ vm_offset_t cpu_IMPL_regs;
+ uint64_t cpu_IMPL_pa;
+ uint64_t cpu_IMPL_len;
+ vm_offset_t cpu_UTTDBG_regs;
+ uint64_t cpu_UTTDBG_pa;
+ uint64_t cpu_UTTDBG_len;
+ vm_offset_t coresight_regs;
+ uint64_t coresight_pa;
+ uint64_t coresight_len;
+ int self_ipi_irq;
+ int other_ipi_irq;
+ int pmi_irq;
+ unsigned int die_cluster_id;
+ unsigned int cluster_core_id;
+} ml_topology_cpu_t;
+
+/*!
+ * @typedef ml_topology_cluster_t
+ * @brief Describes one cluster in the topology.
+ *
+ * @field cluster_id Cluster ID (EDT: cluster-id)
+ * @field cluster_type The type of CPUs found in this cluster.
+ * @field num_cpus Total number of usable CPU cores in this cluster.
+ * @field first_cpu_id The cpu_id of the first CPU in the cluster.
+ * @field cpu_mask A bitmask representing the cpu_id's that belong to the cluster. Example:
+ * If the cluster contains CPU4 and CPU5, cpu_mask will be 0x30.
+ * @field acc_IMPL_regs IO-mapped virtual address of acc_IMPL (implementation-defined) register block.
+ * @field acc_IMPL_pa Physical address of acc_IMPL register block.
+ * @field acc_IMPL_len Length of acc_IMPL register block.
+ * @field cpm_IMPL_regs IO-mapped virtual address of cpm_IMPL (implementation-defined) register block.
+ * @field cpm_IMPL_pa Physical address of cpm_IMPL register block.
+ * @field cpm_IMPL_len Length of cpm_IMPL register block.
+ */
+typedef struct ml_topology_cluster {
+ unsigned int cluster_id;
+ cluster_type_t cluster_type;
+ unsigned int num_cpus;
+ unsigned int first_cpu_id;
+ uint64_t cpu_mask;
+ vm_offset_t acc_IMPL_regs;
+ uint64_t acc_IMPL_pa;
+ uint64_t acc_IMPL_len;
+ vm_offset_t cpm_IMPL_regs;
+ uint64_t cpm_IMPL_pa;
+ uint64_t cpm_IMPL_len;
+} ml_topology_cluster_t;
+
+// Bump this version number any time any ml_topology_* struct changes, so
+// that KPI users can check whether their headers are compatible with
+// the running kernel.
+#define CPU_TOPOLOGY_VERSION 1
+
+/*!
+ * @typedef ml_topology_info_t
+ * @brief Describes the CPU topology for all APs in the system. Populated from EDT and read-only at runtime.
+ * @discussion This struct only lists CPU cores that are considered usable by both iBoot and XNU. Some
+ * physically present CPU cores may be considered unusable due to configuration options like
+ * the "cpus=" boot-arg. Cores that are disabled in hardware will not show up in EDT at all, so
+ * they also will not be present in this struct.
+ *
+ * @field version Version of the struct (set to CPU_TOPOLOGY_VERSION).
+ * @field num_cpus Total number of usable CPU cores.
+ * @field max_cpu_id The highest usable logical CPU ID.
+ * @field num_clusters Total number of AP CPU clusters on the system (usable or not).
+ * @field max_cluster_id The highest cluster ID found in EDT.
+ * @field cpus List of |num_cpus| entries.
+ * @field clusters List of |num_clusters| entries.
+ * @field boot_cpu Points to the |cpus| entry for the boot CPU.
+ * @field boot_cluster Points to the |clusters| entry which contains the boot CPU.
+ * @field chip_revision Silicon revision reported by iBoot, which comes from the
+ * SoC-specific fuse bits. See CPU_VERSION_xx macros for definitions.
+ */
+typedef struct ml_topology_info {
+ unsigned int version;
+ unsigned int num_cpus;
+ unsigned int max_cpu_id;
+ unsigned int num_clusters;
+ unsigned int max_cluster_id;
+ unsigned int max_die_id;
+ ml_topology_cpu_t *cpus;
+ ml_topology_cluster_t *clusters;
+ ml_topology_cpu_t *boot_cpu;
+ ml_topology_cluster_t *boot_cluster;
+ unsigned int chip_revision;
+} ml_topology_info_t;
+
+/*!
+ * @function ml_get_topology_info
+ * @result A pointer to the read-only topology struct. Does not need to be freed. Returns NULL
+ * if the struct hasn't been initialized or the feature is unsupported.
+ */
+const ml_topology_info_t *ml_get_topology_info(void);
+
+/*!
+ * @function ml_map_cpu_pio
+ * @brief Maps per-CPU and per-cluster PIO registers found in EDT. This needs to be
+ * called after arm_vm_init() so it can't be part of ml_parse_cpu_topology().
+ */
+void ml_map_cpu_pio(void);
+
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