xnu-7195.50.7.100.1.tar.gz

[apple/xnu.git] / osfmk / arm / caches_asm.s

diff --git a/osfmk/arm/caches_asm.s b/osfmk/arm/caches_asm.s
index 0b305f48f613be90726ad2ce097f88fce74f0288..5556a00ae0c57d9659ab12d68c41b425a0b9770a 100644 (file)
--- a/osfmk/arm/caches_asm.s
+++ b/osfmk/arm/caches_asm.s
@@ -31,6 +31,7 @@
 #include <arm/pmap.h>
 #include <sys/errno.h>
 #include "assym.s"
 #include <arm/pmap.h>
 #include <sys/errno.h>
 #include "assym.s"

+#include "caches_macros.s"

 
 
 /*
 
 
 /*


@@ -143,31 +144,37 @@ fmir_loop:
 LEXT(CleanPoC_Dcache)
 LEXT(clean_mmu_dcache)
 #if    !defined(__ARM_L1_WT_CACHE__)
 LEXT(CleanPoC_Dcache)
 LEXT(clean_mmu_dcache)
 #if    !defined(__ARM_L1_WT_CACHE__)

+       mov             r0, #0
+       GET_CACHE_CONFIG r0, r1, r2, r3

        mov             r0, #0
        dsb
 clean_dcacheway:
 clean_dcacheline:              
        mcr             p15, 0, r0, c7, c10, 2                           // clean dcache line by way/set
        mov             r0, #0
        dsb
 clean_dcacheway:
 clean_dcacheline:              
        mcr             p15, 0, r0, c7, c10, 2                           // clean dcache line by way/set

-       add             r0, r0, #1 << MMU_I7SET                          // increment set index
-       tst             r0, #1 << (MMU_NSET + MMU_I7SET)         // look for overflow
+       add             r0, r0, r1                                                       // increment set index
+       tst             r0, r2                                                           // look for overflow

        beq             clean_dcacheline
        beq             clean_dcacheline

-       bic             r0, r0, #1 << (MMU_NSET + MMU_I7SET) // clear set overflow
-       adds    r0, r0, #1 << MMU_I7WAY                          // increment way
+       bic             r0, r0, r2                                                       // clear set overflow
+       adds    r0, r0, r3                                                       // increment way

        bcc             clean_dcacheway                                          // loop
 #endif
        bcc             clean_dcacheway                                          // loop
 #endif

-#if __ARM_L2CACHE__
+       HAS_L2_CACHE r0
+       cmp             r0, #0
+       beq             clean_skipl2dcache
+       mov             r0, #1
+       GET_CACHE_CONFIG r0, r1, r2, r3

        dsb
        mov             r0, #2
 clean_l2dcacheway:
 clean_l2dcacheline:            
        mcr             p15, 0, r0, c7, c10, 2                           // clean dcache line by way/set
        dsb
        mov             r0, #2
 clean_l2dcacheway:
 clean_l2dcacheline:            
        mcr             p15, 0, r0, c7, c10, 2                           // clean dcache line by way/set

-       add             r0, r0, #1 << L2_I7SET                           // increment set index
-       tst             r0, #1 << (L2_NSET + L2_I7SET)           // look for overflow
+       add             r0, r0, r1                                                       // increment set index
+       tst             r0, r2                                                           // look for overflow

        beq             clean_l2dcacheline
        beq             clean_l2dcacheline

-       bic             r0, r0, #1 << (L2_NSET + L2_I7SET)       // clear set overflow
-       adds    r0, r0, #1 << L2_I7WAY                           // increment way
+       bic             r0, r0, r2                                                       // clear set overflow
+       adds    r0, r0, r3                                                       // increment way

        bcc             clean_l2dcacheway                                        // loop
        bcc             clean_l2dcacheway                                        // loop

-#endif
+clean_skipl2dcache:

        dsb
        bx              lr
                
        dsb
        bx              lr
                


@@ -181,16 +188,18 @@ clean_l2dcacheline:
        .globl EXT(CleanPoU_Dcache)
 LEXT(CleanPoU_Dcache)
 #if    !defined(__ARM_PoU_WT_CACHE__)
        .globl EXT(CleanPoU_Dcache)
 LEXT(CleanPoU_Dcache)
 #if    !defined(__ARM_PoU_WT_CACHE__)

+       mov             r0, #0
+       GET_CACHE_CONFIG r0, r1, r2, r3

        mov             r0, #0
        dsb
 clean_dcacheway_idle:
 clean_dcacheline_idle:         
        mcr             p15, 0, r0, c7, c10, 2                           // clean dcache line by way/set
        mov             r0, #0
        dsb
 clean_dcacheway_idle:
 clean_dcacheline_idle:         
        mcr             p15, 0, r0, c7, c10, 2                           // clean dcache line by way/set

-       add             r0, r0, #1 << MMU_I7SET                          // increment set index
-       tst             r0, #1 << (MMU_NSET + MMU_I7SET)         // look for overflow
+       add             r0, r0, r1                                                       // increment set index
+       tst             r0, r2                                                           // look for overflow

        beq             clean_dcacheline_idle
        beq             clean_dcacheline_idle

-       bic             r0, r0, #1 << (MMU_NSET + MMU_I7SET) // clear set overflow
-       adds    r0, r0, #1 << MMU_I7WAY                          // increment way
+       bic             r0, r0, r2                                                       // clear set overflow
+       adds    r0, r0, r3                                                       // increment way

        bcc             clean_dcacheway_idle                             // loop
 #endif
        dsb
        bcc             clean_dcacheway_idle                             // loop
 #endif
        dsb


@@ -224,7 +233,7 @@ cudr_loop:
        bx              lr
 
 /*
        bx              lr
 
 /*

- *     void CleanPoC_DcacheRegion(vm_offset_t va, unsigned length)
+ *     void CleanPoC_DcacheRegion(vm_offset_t va, size_t length)

  *
  *             Clean d-cache region to Point of Coherency
  */
  *
  *             Clean d-cache region to Point of Coherency
  */


@@ -256,30 +265,36 @@ ccdr_loop:
        .align 2
        .globl EXT(FlushPoC_Dcache)
 LEXT(FlushPoC_Dcache)
        .align 2
        .globl EXT(FlushPoC_Dcache)
 LEXT(FlushPoC_Dcache)

+       mov             r0, #0
+       GET_CACHE_CONFIG r0, r1, r2, r3

        mov             r0, #0
        dsb
 cleanflush_dcacheway:
 cleanflush_dcacheline:         
        mcr             p15, 0, r0, c7, c14, 2                           // cleanflush dcache line by way/set
        mov             r0, #0
        dsb
 cleanflush_dcacheway:
 cleanflush_dcacheline:         
        mcr             p15, 0, r0, c7, c14, 2                           // cleanflush dcache line by way/set

-       add             r0, r0, #1 << MMU_I7SET                          // increment set index
-       tst             r0, #1 << (MMU_NSET + MMU_I7SET)         // look for overflow
+       add             r0, r0, r1                                                       // increment set index
+       tst             r0, r2                                                           // look for overflow

        beq             cleanflush_dcacheline
        beq             cleanflush_dcacheline

-       bic             r0, r0, #1 << (MMU_NSET + MMU_I7SET) // clear set overflow
-       adds    r0, r0, #1 << MMU_I7WAY                          // increment way
+       bic             r0, r0, r2                                                       // clear set overflow
+       adds    r0, r0, r3                                                       // increment way

        bcc             cleanflush_dcacheway                             // loop
        bcc             cleanflush_dcacheway                             // loop

-#if __ARM_L2CACHE__
+       HAS_L2_CACHE r0
+       cmp             r0, #0
+       beq             cleanflush_skipl2dcache
+       mov             r0, #1
+       GET_CACHE_CONFIG r0, r1, r2, r3

        dsb
        mov             r0, #2
 cleanflush_l2dcacheway:
 cleanflush_l2dcacheline:               
        mcr             p15, 0, r0, c7, c14, 2                           // cleanflush dcache line by way/set
        dsb
        mov             r0, #2
 cleanflush_l2dcacheway:
 cleanflush_l2dcacheline:               
        mcr             p15, 0, r0, c7, c14, 2                           // cleanflush dcache line by way/set

-       add             r0, r0, #1 << L2_I7SET                           // increment set index
-       tst             r0, #1 << (L2_NSET + L2_I7SET)          // look for overflow
+       add             r0, r0, r1                                                       // increment set index
+       tst             r0, r2                                                           // look for overflow

        beq             cleanflush_l2dcacheline
        beq             cleanflush_l2dcacheline

-       bic             r0, r0, #1 << (L2_NSET + L2_I7SET)       // clear set overflow
-       adds    r0, r0, #1 << L2_I7WAY                           // increment way
+       bic             r0, r0, r2                                                       // clear set overflow
+       adds    r0, r0, r3                                                       // increment way

        bcc             cleanflush_l2dcacheway                           // loop
        bcc             cleanflush_l2dcacheway                           // loop

-#endif
+cleanflush_skipl2dcache:

        dsb
        bx              lr
 
        dsb
        bx              lr
 


@@ -292,16 +307,18 @@ cleanflush_l2dcacheline:
        .align 2
        .globl EXT(FlushPoU_Dcache)
 LEXT(FlushPoU_Dcache)
        .align 2
        .globl EXT(FlushPoU_Dcache)
 LEXT(FlushPoU_Dcache)

+       mov             r0, #0
+       GET_CACHE_CONFIG r0, r1, r2, r3

        mov             r0, #0
        dsb
 fpud_way:
 fpud_line:             
        mcr             p15, 0, r0, c7, c14, 2                           // cleanflush dcache line by way/set
        mov             r0, #0
        dsb
 fpud_way:
 fpud_line:             
        mcr             p15, 0, r0, c7, c14, 2                           // cleanflush dcache line by way/set

-       add             r0, r0, #1 << MMU_I7SET                          // increment set index
-       tst             r0, #1 << (MMU_NSET + MMU_I7SET)         // look for overflow
+       add             r0, r0, r1                                                       // increment set index
+       tst             r0, r2                                                           // look for overflow

        beq             fpud_line
        beq             fpud_line

-       bic             r0, r0, #1 << (MMU_NSET + MMU_I7SET) // clear set overflow
-       adds    r0, r0, #1 << MMU_I7WAY                          // increment way
+       bic             r0, r0, r2                                                       // clear set overflow
+       adds    r0, r0, r3                                                       // increment way

        bcc             fpud_way                                                         // loop
        dsb
        bx              lr
        bcc             fpud_way                                                         // loop
        dsb
        bx              lr