xnu-4570.71.2.tar.gz

[apple/xnu.git] / osfmk / i386 / mp.c

diff --git a/osfmk/i386/mp.c b/osfmk/i386/mp.c
index 6da284edf97c637d0c1852142a3a2eebf08a4ccf..3b72326873570e426d4e4582ba47b5aeb13129fc 100644 (file)
--- a/osfmk/i386/mp.c
+++ b/osfmk/i386/mp.c
@@ -1,53 +1,89 @@
 /*
 /*

- * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2000-2012 Apple Inc. All rights reserved.

  *
  *

- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@

  * 
  * 

- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License").  You may not use this file except in compliance with the
- * License.  Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.

  * 
  * 

- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
+ * 
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER

  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,

- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.

  * 
  * 

- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@

  */
 /*
  * @OSF_COPYRIGHT@
  */
 
  */
 /*
  * @OSF_COPYRIGHT@
  */
 

-#include <cpus.h>
-#include <mach_rt.h>
-#include <mach_kdb.h>

 #include <mach_kdp.h>
 #include <mach_kdp.h>

+#include <kdp/kdp_internal.h>

 #include <mach_ldebug.h>
 #include <mach_ldebug.h>

+#include <gprof.h>

 
 

-#include <i386/mp.h>
-#include <i386/mp_events.h>
-#include <i386/mp_slave_boot.h>
-#include <i386/apic.h>
-#include <i386/ipl.h>
-#include <i386/fpu.h>
-#include <i386/pio.h>
-#include <i386/cpuid.h>
-#include <i386/proc_reg.h>
-#include <i386/machine_cpu.h>
-#include <i386/misc_protos.h>
-#include <vm/vm_kern.h>

 #include <mach/mach_types.h>
 #include <mach/kern_return.h>
 #include <mach/mach_types.h>
 #include <mach/kern_return.h>

+
+#include <kern/kern_types.h>

 #include <kern/startup.h>
 #include <kern/startup.h>

+#include <kern/timer_queue.h>

 #include <kern/processor.h>
 #include <kern/cpu_number.h>
 #include <kern/cpu_data.h>
 #include <kern/assert.h>
 #include <kern/processor.h>
 #include <kern/cpu_number.h>
 #include <kern/cpu_data.h>
 #include <kern/assert.h>

+#include <kern/machine.h>
+#include <kern/pms.h>
+#include <kern/misc_protos.h>
+#include <kern/timer_call.h>
+#include <kern/kalloc.h>
+#include <kern/queue.h>
+#include <prng/random.h>
+
+#include <vm/vm_map.h>
+#include <vm/vm_kern.h>
+
+#include <profiling/profile-mk.h>
+
+#include <i386/bit_routines.h>
+#include <i386/proc_reg.h>
+#include <i386/cpu_threads.h>
+#include <i386/mp_desc.h>
+#include <i386/misc_protos.h>
+#include <i386/trap.h>
+#include <i386/postcode.h>
+#include <i386/machine_routines.h>
+#include <i386/mp.h>
+#include <i386/mp_events.h>
+#include <i386/lapic.h>
+#include <i386/cpuid.h>
+#include <i386/fpu.h>
+#include <i386/machine_cpu.h>
+#include <i386/pmCPU.h>
+#if CONFIG_MCA
+#include <i386/machine_check.h>
+#endif
+#include <i386/acpi.h>
+
+#include <sys/kdebug.h>
+
+#include <console/serial_protos.h>
+
+#if MONOTONIC
+#include <kern/monotonic.h>
+#endif /* MONOTONIC */

 
 #if    MP_DEBUG
 #define PAUSE          delay(1000000)
 
 #if    MP_DEBUG
 #define PAUSE          delay(1000000)


@@ -57,530 +93,677 @@
 #define PAUSE
 #endif /* MP_DEBUG */
 
 #define PAUSE
 #endif /* MP_DEBUG */
 

-/* Initialize lapic_id so cpu_number() works on non SMP systems */
-unsigned long  lapic_id_initdata = 0;
-unsigned long  lapic_id = (unsigned long)&lapic_id_initdata;
-vm_offset_t    lapic_start;
-
-void           lapic_init(void);
-void           slave_boot_init(void);
+/* Debugging/test trace events: */
+#define        TRACE_MP_TLB_FLUSH              MACHDBG_CODE(DBG_MACH_MP, 0)
+#define        TRACE_MP_CPUS_CALL              MACHDBG_CODE(DBG_MACH_MP, 1)
+#define        TRACE_MP_CPUS_CALL_LOCAL        MACHDBG_CODE(DBG_MACH_MP, 2)
+#define        TRACE_MP_CPUS_CALL_ACTION       MACHDBG_CODE(DBG_MACH_MP, 3)
+#define        TRACE_MP_CPUS_CALL_NOBUF        MACHDBG_CODE(DBG_MACH_MP, 4)
+#define        TRACE_MP_CPU_FAST_START         MACHDBG_CODE(DBG_MACH_MP, 5)
+#define        TRACE_MP_CPU_START              MACHDBG_CODE(DBG_MACH_MP, 6)
+#define        TRACE_MP_CPU_DEACTIVATE         MACHDBG_CODE(DBG_MACH_MP, 7)

 
 

-static void    mp_kdp_wait(void);
-static void    mp_rendezvous_action(void);
+#define ABS(v)         (((v) > 0)?(v):-(v))

 
 

-boolean_t      smp_initialized = FALSE;
+void           slave_boot_init(void);
+void           i386_cpu_IPI(int cpu);

 
 

-decl_simple_lock_data(,mp_kdp_lock);
-decl_simple_lock_data(,mp_putc_lock);
+#if MACH_KDP
+static void    mp_kdp_wait(boolean_t flush, boolean_t isNMI);
+#endif /* MACH_KDP */

 
 

-/* Variables needed for MP rendezvous. */
-static void            (*mp_rv_setup_func)(void *arg);
-static void            (*mp_rv_action_func)(void *arg);
-static void            (*mp_rv_teardown_func)(void *arg);
-static void            *mp_rv_func_arg;
-static int             mp_rv_ncpus;
-static volatile long   mp_rv_waiters[2];
-decl_simple_lock_data(,mp_rv_lock);
+#if MACH_KDP
+static boolean_t       cpu_signal_pending(int cpu, mp_event_t event);
+#endif /* MACH_KDP */
+static int             NMIInterruptHandler(x86_saved_state_t *regs);

 
 

-int            lapic_to_cpu[LAPIC_ID_MAX+1];
-int            cpu_to_lapic[NCPUS];
+boolean_t              smp_initialized = FALSE;
+uint32_t               TSC_sync_margin = 0xFFF;
+volatile boolean_t     force_immediate_debugger_NMI = FALSE;
+volatile boolean_t     pmap_tlb_flush_timeout = FALSE;
+#if DEBUG || DEVELOPMENT
+boolean_t              mp_interrupt_watchdog_enabled = TRUE;
+uint32_t               mp_interrupt_watchdog_events = 0;
+#endif

 
 

-static void
-lapic_cpu_map_init(void)
-{
-       int     i;
+decl_simple_lock_data(,debugger_callback_lock);
+struct debugger_callback *debugger_callback = NULL;

 
 

-       for (i = 0; i < NCPUS; i++)
-               cpu_to_lapic[i] = -1;
-       for (i = 0; i <= LAPIC_ID_MAX; i++)
-               lapic_to_cpu[i] = -1;
-}
+decl_lck_mtx_data(static, mp_cpu_boot_lock);
+lck_mtx_ext_t  mp_cpu_boot_lock_ext;

 
 

-void
-lapic_cpu_map(int apic_id, int cpu_number)
-{
-       cpu_to_lapic[cpu_number] = apic_id;
-       lapic_to_cpu[apic_id] = cpu_number;
+/* Variables needed for MP rendezvous. */
+decl_simple_lock_data(,mp_rv_lock);
+static void    (*mp_rv_setup_func)(void *arg);
+static void    (*mp_rv_action_func)(void *arg);
+static void    (*mp_rv_teardown_func)(void *arg);
+static void    *mp_rv_func_arg;
+static volatile int    mp_rv_ncpus;
+                       /* Cache-aligned barriers: */
+static volatile long   mp_rv_entry    __attribute__((aligned(64)));
+static volatile long   mp_rv_exit     __attribute__((aligned(64)));
+static volatile long   mp_rv_complete __attribute__((aligned(64)));
+
+volatile       uint64_t        debugger_entry_time;
+volatile       uint64_t        debugger_exit_time;
+#if MACH_KDP
+#include <kdp/kdp.h>
+extern int kdp_snapshot;
+static struct _kdp_xcpu_call_func {
+       kdp_x86_xcpu_func_t func;
+       void     *arg0, *arg1;
+       volatile long     ret;
+       volatile uint16_t cpu;
+} kdp_xcpu_call_func = {
+       .cpu  = KDP_XCPU_NONE
+};
+
+#endif
+
+/* Variables needed for MP broadcast. */
+static void        (*mp_bc_action_func)(void *arg);
+static void        *mp_bc_func_arg;
+static int             mp_bc_ncpus;
+static volatile long   mp_bc_count;
+decl_lck_mtx_data(static, mp_bc_lock);
+lck_mtx_ext_t  mp_bc_lock_ext;
+static volatile int    debugger_cpu = -1;
+volatile long   NMIPI_acks = 0;
+volatile long   NMI_count = 0;
+static NMI_reason_t    NMI_panic_reason = NONE;
+static int             vector_timed_out;
+
+extern void    NMI_cpus(void);
+
+static void    mp_cpus_call_init(void); 
+static void    mp_cpus_call_action(void); 
+static void    mp_call_PM(void);
+
+char           mp_slave_stack[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE))); // Temp stack for slave init
+
+/* PAL-related routines */
+boolean_t i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler, 
+               int ipi_vector, i386_intr_func_t ipi_handler);
+void i386_start_cpu(int lapic_id, int cpu_num);
+void i386_send_NMI(int cpu);
+void NMIPI_enable(boolean_t);
+#if GPROF
+/*
+ * Initialize dummy structs for profiling. These aren't used but
+ * allows hertz_tick() to be built with GPROF defined.
+ */
+struct profile_vars _profile_vars;
+struct profile_vars *_profile_vars_cpus[MAX_CPUS] = { &_profile_vars };
+#define GPROF_INIT()                                                   \
+{                                                                      \
+       int     i;                                                      \
+                                                                       \
+       /* Hack to initialize pointers to unused profiling structs */   \
+       for (i = 1; i < MAX_CPUS; i++)                          \
+               _profile_vars_cpus[i] = &_profile_vars;                 \

 }
 }

+#else
+#define GPROF_INIT()
+#endif /* GPROF */

 
 

-#ifdef MP_DEBUG
-static void
-lapic_cpu_map_dump(void)
-{
-       int     i;
+static lck_grp_t       smp_lck_grp;
+static lck_grp_attr_t  smp_lck_grp_attr;

 
 

-       for (i = 0; i < NCPUS; i++) {
-               if (cpu_to_lapic[i] == -1)
-                       continue;
-               kprintf("cpu_to_lapic[%d]: %d\n",
-                       i, cpu_to_lapic[i]);
-       }
-       for (i = 0; i <= LAPIC_ID_MAX; i++) {
-               if (lapic_to_cpu[i] == -1)
-                       continue;
-               kprintf("lapic_to_cpu[%d]: %d\n",
-                       i, lapic_to_cpu[i]);
-       }
-}
-#endif /* MP_DEBUG */
+#define NUM_CPU_WARM_CALLS     20
+struct timer_call      cpu_warm_call_arr[NUM_CPU_WARM_CALLS];
+queue_head_t           cpu_warm_call_list;
+decl_simple_lock_data(static, cpu_warm_lock);

 
 

-#define LAPIC_REG(reg) \
-       (*((volatile int *)(lapic_start + LAPIC_##reg)))
-#define LAPIC_REG_OFFSET(reg,off) \
-       (*((volatile int *)(lapic_start + LAPIC_##reg + (off))))
+typedef struct cpu_warm_data {
+       timer_call_t    cwd_call;
+       uint64_t        cwd_deadline;
+       int             cwd_result;
+} *cpu_warm_data_t;

 
 

+static void            cpu_prewarm_init(void);
+static void            cpu_warm_timer_call_func(call_entry_param_t p0, call_entry_param_t p1);
+static void            _cpu_warm_setup(void *arg);
+static timer_call_t    grab_warm_timer_call(void);
+static void            free_warm_timer_call(timer_call_t call);

 
 void
 smp_init(void)
 
 void
 smp_init(void)

-

 {
 {

-       int             result;
-       vm_map_entry_t  entry;
-       uint32_t        lo;
-       uint32_t        hi;
-       boolean_t       is_boot_processor;
-       boolean_t       is_lapic_enabled;
-
-       /* Local APIC? */
-       if ((cpuid_features() & CPUID_FEATURE_APIC) == 0)
-               return;
-
-       simple_lock_init(&mp_kdp_lock, ETAP_MISC_PRINTF);
-       simple_lock_init(&mp_rv_lock, ETAP_MISC_PRINTF);
-       simple_lock_init(&mp_putc_lock, ETAP_MISC_PRINTF);
-
-       /* Examine the local APIC state */
-       rdmsr(MSR_IA32_APIC_BASE, lo, hi);
-       is_boot_processor = (lo & MSR_IA32_APIC_BASE_BSP) != 0;
-       is_lapic_enabled  = (lo & MSR_IA32_APIC_BASE_ENABLE) != 0;
-       DBG("MSR_IA32_APIC_BASE 0x%x:0x%x %s %s\n", hi, lo,
-               is_lapic_enabled ? "enabled" : "disabled",
-               is_boot_processor ? "BSP" : "AP");
-       assert(is_boot_processor);
-       assert(is_lapic_enabled);
-
-       /* Establish a map to the local apic */
-       lapic_start = vm_map_min(kernel_map);
-       result = vm_map_find_space(kernel_map, &lapic_start,
-                                  round_page(LAPIC_SIZE), 0, &entry);
-       if (result != KERN_SUCCESS) {
-               printf("smp_init: vm_map_find_entry FAILED (err=%d). "
-                       "Only supporting ONE cpu.\n", result);
+       simple_lock_init(&mp_rv_lock, 0);
+       simple_lock_init(&debugger_callback_lock, 0);
+       lck_grp_attr_setdefault(&smp_lck_grp_attr);
+       lck_grp_init(&smp_lck_grp, "i386_smp", &smp_lck_grp_attr);
+       lck_mtx_init_ext(&mp_cpu_boot_lock, &mp_cpu_boot_lock_ext, &smp_lck_grp, LCK_ATTR_NULL);
+       lck_mtx_init_ext(&mp_bc_lock, &mp_bc_lock_ext, &smp_lck_grp, LCK_ATTR_NULL);
+       console_init();
+
+       if(!i386_smp_init(LAPIC_NMI_INTERRUPT, NMIInterruptHandler, 
+                               LAPIC_VECTOR(INTERPROCESSOR), cpu_signal_handler))

                return;
                return;

-       }
-       vm_map_unlock(kernel_map);
-       pmap_enter(pmap_kernel(),
-                       lapic_start,
-                       (ppnum_t) i386_btop(i386_trunc_page(LAPIC_START)),
-                       VM_PROT_READ|VM_PROT_WRITE,
-                       VM_WIMG_USE_DEFAULT,
-                       TRUE);
-       lapic_id = (unsigned long)(lapic_start + LAPIC_ID);

 
 

-       /* Set up the lapic_id <-> cpu_number map and add this boot processor */
-       lapic_cpu_map_init();
-       lapic_cpu_map((LAPIC_REG(ID)>>LAPIC_ID_SHIFT)&LAPIC_ID_MASK, 0);
+       cpu_thread_init();

 
 

-       lapic_init();
+       GPROF_INIT();
+       DBGLOG_CPU_INIT(master_cpu);

 
 

-       slave_boot_init();
-       master_up();
+       mp_cpus_call_init();
+       mp_cpus_call_cpu_init(master_cpu);

 
 

+#if DEBUG || DEVELOPMENT
+       if (PE_parse_boot_argn("interrupt_watchdog",
+                              &mp_interrupt_watchdog_enabled,
+                              sizeof(mp_interrupt_watchdog_enabled))) {
+               kprintf("Interrupt watchdog %sabled\n",
+                       mp_interrupt_watchdog_enabled ? "en" : "dis");
+       }
+#endif
+
+       if (PE_parse_boot_argn("TSC_sync_margin",
+                                       &TSC_sync_margin, sizeof(TSC_sync_margin))) {
+               kprintf("TSC sync Margin 0x%x\n", TSC_sync_margin);
+       } else if (cpuid_vmm_present()) {
+               kprintf("TSC sync margin disabled\n");
+               TSC_sync_margin = 0;
+       }

        smp_initialized = TRUE;
 
        smp_initialized = TRUE;
 

+       cpu_prewarm_init();
+

        return;
 }
 
        return;
 }
 

+typedef struct {
+       int                     target_cpu;
+       int                     target_lapic;
+       int                     starter_cpu;
+} processor_start_info_t;
+static processor_start_info_t  start_info        __attribute__((aligned(64)));

 
 

-int
-lapic_esr_read(void)
-{
-       /* write-read register */
-       LAPIC_REG(ERROR_STATUS) = 0;
-       return LAPIC_REG(ERROR_STATUS);
-}
+/* 
+ * Cache-alignment is to avoid cross-cpu false-sharing interference.
+ */
+static volatile long           tsc_entry_barrier __attribute__((aligned(64)));
+static volatile long           tsc_exit_barrier  __attribute__((aligned(64)));
+static volatile uint64_t       tsc_target        __attribute__((aligned(64)));

 
 

-void 
-lapic_esr_clear(void)
+/*
+ * Poll a CPU to see when it has marked itself as running.
+ */
+static void
+mp_wait_for_cpu_up(int slot_num, unsigned int iters, unsigned int usecdelay)

 {
 {

-       LAPIC_REG(ERROR_STATUS) = 0;
-       LAPIC_REG(ERROR_STATUS) = 0;
-}
-
-static char *DM[8] = {
-       "Fixed",
-       "Lowest Priority",
-       "Invalid",
-       "Invalid",
-       "NMI",
-       "Reset",
-       "Invalid",
-       "ExtINT"};
-
-void
-lapic_dump(void)
-{
-       int     i;
-       char    buf[128];
-
-#define BOOL(a) ((a)?' ':'!')
-
-       kprintf("LAPIC %d at 0x%x version 0x%x\n", 
-               (LAPIC_REG(ID)>>LAPIC_ID_SHIFT)&LAPIC_ID_MASK,
-               lapic_start,
-               LAPIC_REG(VERSION)&LAPIC_VERSION_MASK);
-       kprintf("Priorities: Task 0x%x  Arbitration 0x%x  Processor 0x%x\n",
-               LAPIC_REG(TPR)&LAPIC_TPR_MASK,
-               LAPIC_REG(APR)&LAPIC_APR_MASK,
-               LAPIC_REG(PPR)&LAPIC_PPR_MASK);
-       kprintf("Destination Format 0x%x Logical Destination 0x%x\n",
-               LAPIC_REG(DFR)>>LAPIC_DFR_SHIFT,
-               LAPIC_REG(LDR)>>LAPIC_LDR_SHIFT);
-       kprintf("%cEnabled %cFocusChecking SV 0x%x\n",
-               BOOL(LAPIC_REG(SVR)&LAPIC_SVR_ENABLE),
-               BOOL(!(LAPIC_REG(SVR)&LAPIC_SVR_FOCUS_OFF)),
-               LAPIC_REG(SVR) & LAPIC_SVR_MASK);
-       kprintf("LVT_TIMER:   Vector 0x%02x %s %cmasked %s\n",
-               LAPIC_REG(LVT_TIMER)&LAPIC_LVT_VECTOR_MASK,
-               (LAPIC_REG(LVT_TIMER)&LAPIC_LVT_DS_PENDING)?"SendPending":"Idle",
-               BOOL(LAPIC_REG(LVT_TIMER)&LAPIC_LVT_MASKED),
-               (LAPIC_REG(LVT_TIMER)&LAPIC_LVT_PERIODIC)?"Periodic":"OneShot");
-       kprintf("LVT_PERFCNT: Vector 0x%02x [%s][%s][%s] %s %cmasked\n",
-               LAPIC_REG(LVT_PERFCNT)&LAPIC_LVT_VECTOR_MASK,
-               DM[(LAPIC_REG(LVT_PERFCNT)>>LAPIC_LVT_DM_SHIFT)&LAPIC_LVT_DM_MASK],
-               (LAPIC_REG(LVT_PERFCNT)&LAPIC_LVT_TM_LEVEL)?"Level":"Edge ",
-               (LAPIC_REG(LVT_PERFCNT)&LAPIC_LVT_IP_PLRITY_LOW)?"Low ":"High",
-               (LAPIC_REG(LVT_PERFCNT)&LAPIC_LVT_DS_PENDING)?"SendPending":"Idle",
-               BOOL(LAPIC_REG(LVT_PERFCNT)&LAPIC_LVT_MASKED));
-       kprintf("LVT_LINT0:   Vector 0x%02x [%s][%s][%s] %s %cmasked\n",
-               LAPIC_REG(LVT_LINT0)&LAPIC_LVT_VECTOR_MASK,
-               DM[(LAPIC_REG(LVT_LINT0)>>LAPIC_LVT_DM_SHIFT)&LAPIC_LVT_DM_MASK],
-               (LAPIC_REG(LVT_LINT0)&LAPIC_LVT_TM_LEVEL)?"Level":"Edge ",
-               (LAPIC_REG(LVT_LINT0)&LAPIC_LVT_IP_PLRITY_LOW)?"Low ":"High",
-               (LAPIC_REG(LVT_LINT0)&LAPIC_LVT_DS_PENDING)?"SendPending":"Idle",
-               BOOL(LAPIC_REG(LVT_LINT0)&LAPIC_LVT_MASKED));
-       kprintf("LVT_LINT1:   Vector 0x%02x [%s][%s][%s] %s %cmasked\n",
-               LAPIC_REG(LVT_LINT1)&LAPIC_LVT_VECTOR_MASK,
-               DM[(LAPIC_REG(LVT_LINT1)>>LAPIC_LVT_DM_SHIFT)&LAPIC_LVT_DM_MASK],
-               (LAPIC_REG(LVT_LINT1)&LAPIC_LVT_TM_LEVEL)?"Level":"Edge ",
-               (LAPIC_REG(LVT_LINT1)&LAPIC_LVT_IP_PLRITY_LOW)?"Low ":"High",
-               (LAPIC_REG(LVT_LINT1)&LAPIC_LVT_DS_PENDING)?"SendPending":"Idle",
-               BOOL(LAPIC_REG(LVT_LINT1)&LAPIC_LVT_MASKED));
-       kprintf("LVT_ERROR:   Vector 0x%02x %s %cmasked\n",
-               LAPIC_REG(LVT_ERROR)&LAPIC_LVT_VECTOR_MASK,
-               (LAPIC_REG(LVT_ERROR)&LAPIC_LVT_DS_PENDING)?"SendPending":"Idle",
-               BOOL(LAPIC_REG(LVT_ERROR)&LAPIC_LVT_MASKED));
-       kprintf("ESR: %08x \n", lapic_esr_read());
-       kprintf("       ");
-       for(i=0xf; i>=0; i--)
-               kprintf("%x%x%x%x",i,i,i,i);
-       kprintf("\n");
-       kprintf("TMR: 0x");
-       for(i=7; i>=0; i--)
-               kprintf("%08x",LAPIC_REG_OFFSET(TMR_BASE, i*0x10));
-       kprintf("\n");
-       kprintf("IRR: 0x");
-       for(i=7; i>=0; i--)
-               kprintf("%08x",LAPIC_REG_OFFSET(IRR_BASE, i*0x10));
-       kprintf("\n");
-       kprintf("ISR: 0x");
-       for(i=7; i >= 0; i--)
-               kprintf("%08x",LAPIC_REG_OFFSET(ISR_BASE, i*0x10));
-       kprintf("\n");
+       while (iters-- > 0) {
+               if (cpu_datap(slot_num)->cpu_running)
+                       break;
+               delay(usecdelay);
+       }

 }
 
 }
 

-void
-lapic_init(void)
+/*
+ * Quickly bring a CPU back online which has been halted.
+ */
+kern_return_t
+intel_startCPU_fast(int slot_num)

 {
 {

-       int     value;
-
-       mp_disable_preemption();
+       kern_return_t   rc;

 
 

-       /* Set flat delivery model, logical processor id */
-       LAPIC_REG(DFR) = LAPIC_DFR_FLAT;
-       LAPIC_REG(LDR) = (get_cpu_number()) << LAPIC_LDR_SHIFT;
-
-       /* Accept all */
-       LAPIC_REG(TPR) =  0;
+       /*
+        * Try to perform a fast restart
+        */
+       rc = pmCPUExitHalt(slot_num);
+       if (rc != KERN_SUCCESS)
+               /*
+                * The CPU was not eligible for a fast restart.
+                */
+               return(rc);

 
 

-       LAPIC_REG(SVR) = SPURIOUS_INTERRUPT | LAPIC_SVR_ENABLE;
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPU_FAST_START | DBG_FUNC_START,
+               slot_num, 0, 0, 0, 0);

 
 

-       /* ExtINT */
-       if (get_cpu_number() == master_cpu) {
-               value = LAPIC_REG(LVT_LINT0);
-               value |= LAPIC_LVT_DM_EXTINT;
-               LAPIC_REG(LVT_LINT0) = value;
-       }
+       /*
+        * Wait until the CPU is back online.
+        */
+       mp_disable_preemption();
+    
+       /*
+        * We use short pauses (1us) for low latency.  30,000 iterations is
+        * longer than a full restart would require so it should be more
+        * than long enough.
+        */

 
 

-       lapic_esr_clear();
+       mp_wait_for_cpu_up(slot_num, 30000, 1);
+       mp_enable_preemption();

 
 

-       LAPIC_REG(LVT_ERROR) = APIC_ERROR_INTERRUPT;
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPU_FAST_START | DBG_FUNC_END,
+               slot_num, cpu_datap(slot_num)->cpu_running, 0, 0, 0);

 
 

-       mp_enable_preemption();
+       /*
+        * Check to make sure that the CPU is really running.  If not,
+        * go through the slow path.
+        */
+       if (cpu_datap(slot_num)->cpu_running)
+               return(KERN_SUCCESS);
+       else
+               return(KERN_FAILURE);

 }
 
 }
 

-
-void
-lapic_end_of_interrupt(void)
+static void
+started_cpu(void)

 {
 {

-       LAPIC_REG(EOI) = 0;
+       /* Here on the started cpu with cpu_running set TRUE */
+
+       if (TSC_sync_margin &&
+           start_info.target_cpu == cpu_number()) {
+               /*
+                * I've just started-up, synchronize again with the starter cpu
+                * and then snap my TSC.
+                */
+               tsc_target   = 0;
+               atomic_decl(&tsc_entry_barrier, 1);
+               while (tsc_entry_barrier != 0)
+                       ;       /* spin for starter and target at barrier */
+               tsc_target = rdtsc64();
+               atomic_decl(&tsc_exit_barrier, 1);
+       }

 }
 
 }
 

-void
-lapic_interrupt(int interrupt, void *state)
+static void
+start_cpu(void *arg)

 {
 {

+       int                     i = 1000;
+       processor_start_info_t  *psip = (processor_start_info_t *) arg;
+
+       /* Ignore this if the current processor is not the starter */
+       if (cpu_number() != psip->starter_cpu)
+               return;

 
 

-       switch(interrupt) {
-       case APIC_ERROR_INTERRUPT:
-               panic("Local APIC error\n");
-               break;
-       case SPURIOUS_INTERRUPT:
-               kprintf("SPIV\n");
-               break;
-       case INTERPROCESS_INTERRUPT:
-               cpu_signal_handler((struct i386_interrupt_state *) state);
-               break;
+       DBG("start_cpu(%p) about to start cpu %d, lapic %d\n",
+               arg, psip->target_cpu, psip->target_lapic);
+
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPU_START | DBG_FUNC_START,
+               psip->target_cpu,
+               psip->target_lapic, 0, 0, 0);
+
+       i386_start_cpu(psip->target_lapic, psip->target_cpu);
+
+#ifdef POSTCODE_DELAY
+       /* Wait much longer if postcodes are displayed for a delay period. */
+       i *= 10000;
+#endif
+       DBG("start_cpu(%p) about to wait for cpu %d\n",
+               arg, psip->target_cpu);
+
+       mp_wait_for_cpu_up(psip->target_cpu, i*100, 100);
+
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPU_START | DBG_FUNC_END,
+               psip->target_cpu,
+               cpu_datap(psip->target_cpu)->cpu_running, 0, 0, 0);
+
+       if (TSC_sync_margin &&
+           cpu_datap(psip->target_cpu)->cpu_running) {
+               /*
+                * Compare the TSC from the started processor with ours.
+                * Report and log/panic if it diverges by more than
+                * TSC_sync_margin (TSC_SYNC_MARGIN) ticks. This margin
+                * can be overriden by boot-arg (with 0 meaning no checking).
+                */
+               uint64_t        tsc_starter;
+               int64_t         tsc_delta;
+               atomic_decl(&tsc_entry_barrier, 1);
+               while (tsc_entry_barrier != 0)
+                       ;       /* spin for both processors at barrier */
+               tsc_starter = rdtsc64();
+               atomic_decl(&tsc_exit_barrier, 1);
+               while (tsc_exit_barrier != 0)
+                       ;       /* spin for target to store its TSC */
+               tsc_delta = tsc_target - tsc_starter;
+               kprintf("TSC sync for cpu %d: 0x%016llx delta 0x%llx (%lld)\n",
+                       psip->target_cpu, tsc_target, tsc_delta, tsc_delta);
+               if (ABS(tsc_delta) > (int64_t) TSC_sync_margin) { 
+#if DEBUG
+                       panic(
+#else
+                       printf(
+#endif
+                               "Unsynchronized  TSC for cpu %d: "
+                                       "0x%016llx, delta 0x%llx\n",
+                               psip->target_cpu, tsc_target, tsc_delta);
+               }

        }
        }

-       lapic_end_of_interrupt();

 }
 
 kern_return_t
 intel_startCPU(
        int     slot_num)
 {
 }
 
 kern_return_t
 intel_startCPU(
        int     slot_num)
 {

+       int             lapic = cpu_to_lapic[slot_num];
+       boolean_t       istate;

 
 

-       int     i = 1000;
-       int     lapic_id = cpu_to_lapic[slot_num];
-
-       if (slot_num == get_cpu_number())
-               return KERN_SUCCESS;
-
-       assert(lapic_id != -1);
-
-       DBG("intel_startCPU(%d) lapic_id=%d\n", slot_num, lapic_id);
-
-       mp_disable_preemption();
+       assert(lapic != -1);

 
 

-       LAPIC_REG(ICRD) = lapic_id << LAPIC_ICRD_DEST_SHIFT;
-       LAPIC_REG(ICR) = LAPIC_ICR_DM_INIT;
-       delay(10000);
+       DBGLOG_CPU_INIT(slot_num);

 
 

-       LAPIC_REG(ICRD) = lapic_id << LAPIC_ICRD_DEST_SHIFT;
-       LAPIC_REG(ICR) = LAPIC_ICR_DM_STARTUP|(MP_BOOT>>12);
-       delay(200);
+       DBG("intel_startCPU(%d) lapic_id=%d\n", slot_num, lapic);
+       DBG("IdlePTD(%p): 0x%x\n", &IdlePTD, (int) (uintptr_t)IdlePTD);

 
 

-       while(i-- > 0) {
-               delay(10000);
-               if (machine_slot[slot_num].running)
-                       break;
-       }
+       /*
+        * Initialize (or re-initialize) the descriptor tables for this cpu.
+        * Propagate processor mode to slave.
+        */
+       cpu_desc_init(cpu_datap(slot_num));

 
 

-       mp_enable_preemption();
+       /* Serialize use of the slave boot stack, etc. */
+       lck_mtx_lock(&mp_cpu_boot_lock);

 
 

-       if (!machine_slot[slot_num].running) {
-               DBG("Failed to start CPU %02d\n", slot_num);
-               printf("Failed to start CPU %02d\n", slot_num);
-               return KERN_SUCCESS;
-       } else {
-               DBG("Started CPU %02d\n", slot_num);
-               printf("Started CPU %02d\n", slot_num);
+       istate = ml_set_interrupts_enabled(FALSE);
+       if (slot_num == get_cpu_number()) {
+               ml_set_interrupts_enabled(istate);
+               lck_mtx_unlock(&mp_cpu_boot_lock);

                return KERN_SUCCESS;
        }
                return KERN_SUCCESS;
        }

-}
-
-void
-slave_boot_init(void)
-{
-       extern char     slave_boot_base[];
-       extern char     slave_boot_end[];
-       extern void     pstart(void);

 
 

-       DBG("slave_base=%p slave_end=%p MP_BOOT P=%p V=%p\n",
-               slave_boot_base, slave_boot_end, MP_BOOT, phystokv(MP_BOOT));
+       start_info.starter_cpu  = cpu_number();
+       start_info.target_cpu   = slot_num;
+       start_info.target_lapic = lapic;
+       tsc_entry_barrier = 2;
+       tsc_exit_barrier = 2;

 
        /*
 
        /*

-        * Copy the boot entry code to the real-mode vector area MP_BOOT.
-        * This is in page 1 which has been reserved for this purpose by
-        * machine_startup() from the boot processor.
-        * The slave boot code is responsible for switching to protected
-        * mode and then jumping to the common startup, pstart().
+        * Perform the processor startup sequence with all running
+        * processors rendezvous'ed. This is required during periods when
+        * the cache-disable bit is set for MTRR/PAT initialization.

         */
         */

-       bcopy(slave_boot_base,
-             (char *)phystokv(MP_BOOT),
-             slave_boot_end-slave_boot_base);
+       mp_rendezvous_no_intrs(start_cpu, (void *) &start_info);

 
 

-       /*
-        * Zero a stack area above the boot code.
-        */
-       bzero((char *)(phystokv(MP_BOOTSTACK+MP_BOOT)-0x400), 0x400);
+       start_info.target_cpu = 0;

 
 

-       /*
-        * Set the location at the base of the stack to point to the
-        * common startup entry.
-        */
-       *((vm_offset_t *) phystokv(MP_MACH_START+MP_BOOT)) =
-                                               kvtophys((vm_offset_t)&pstart);
-       
-       /* Flush caches */
-       __asm__("wbinvd");
+       ml_set_interrupts_enabled(istate);
+       lck_mtx_unlock(&mp_cpu_boot_lock);
+
+       if (!cpu_datap(slot_num)->cpu_running) {
+               kprintf("Failed to start CPU %02d\n", slot_num);
+               printf("Failed to start CPU %02d, rebooting...\n", slot_num);
+               delay(1000000);
+               halt_cpu();
+               return KERN_SUCCESS;
+       } else {
+               kprintf("Started cpu %d (lapic id %08x)\n", slot_num, lapic);
+               return KERN_SUCCESS;
+       }

 }
 
 #if    MP_DEBUG
 }
 
 #if    MP_DEBUG

-cpu_signal_event_log_t cpu_signal[NCPUS] = { 0, 0, 0 };
-cpu_signal_event_log_t cpu_handle[NCPUS] = { 0, 0, 0 };
+cpu_signal_event_log_t *cpu_signal[MAX_CPUS];
+cpu_signal_event_log_t *cpu_handle[MAX_CPUS];

 
 MP_EVENT_NAME_DECL();
 
 
 MP_EVENT_NAME_DECL();
 

-void
-cpu_signal_dump_last(int cpu)
-{
-       cpu_signal_event_log_t  *logp = &cpu_signal[cpu];
-       int                     last;
-       cpu_signal_event_t      *eventp;
-
-       last = (logp->next_entry == 0) ? 
-                       LOG_NENTRIES - 1 : logp->next_entry - 1;
-       
-       eventp = &logp->entry[last];
-
-       kprintf("cpu%d: tsc=%lld cpu_signal(%d,%s)\n",
-               cpu, eventp->time, eventp->cpu, mp_event_name[eventp->event]);
-}
-
-void
-cpu_handle_dump_last(int cpu)
-{
-       cpu_signal_event_log_t  *logp = &cpu_handle[cpu];
-       int                     last;
-       cpu_signal_event_t      *eventp;
-
-       last = (logp->next_entry == 0) ? 
-                       LOG_NENTRIES - 1 : logp->next_entry - 1;
-       
-       eventp = &logp->entry[last];
-
-       kprintf("cpu%d: tsc=%lld cpu_signal_handle%s\n",
-               cpu, eventp->time, mp_event_name[eventp->event]);
-}

 #endif /* MP_DEBUG */
 
 #endif /* MP_DEBUG */
 

-void
-cpu_signal_handler(struct i386_interrupt_state *regs)
+/*
+ * Note: called with NULL state when polling for TLB flush and cross-calls.
+ */
+int
+cpu_signal_handler(x86_saved_state_t *regs)

 {
 {

-       register        my_cpu;
+#if    !MACH_KDP
+#pragma unused (regs)
+#endif /* !MACH_KDP */
+       int             my_cpu;

        volatile int    *my_word;
        volatile int    *my_word;

-#if    MACH_KDB && MACH_ASSERT
-       int             i=100;
-#endif /* MACH_KDB && MACH_ASSERT */

 
 

-       mp_disable_preemption();
+       SCHED_STATS_IPI(current_processor());

 
        my_cpu = cpu_number();
 
        my_cpu = cpu_number();

-       my_word = &cpu_data[my_cpu].cpu_signals;
+       my_word = &cpu_data_ptr[my_cpu]->cpu_signals;
+       /* Store the initial set of signals for diagnostics. New
+        * signals could arrive while these are being processed
+        * so it's no more than a hint.
+        */
+
+       cpu_data_ptr[my_cpu]->cpu_prior_signals = *my_word;

 
        do {
 
        do {

-#if    MACH_KDB && MACH_ASSERT
-               if (i-- <= 0)
-                   Debugger("cpu_signal_handler");
-#endif /* MACH_KDB && MACH_ASSERT */

 #if    MACH_KDP
                if (i_bit(MP_KDP, my_word)) {
                        DBGLOG(cpu_handle,my_cpu,MP_KDP);
                        i_bit_clear(MP_KDP, my_word);
 #if    MACH_KDP
                if (i_bit(MP_KDP, my_word)) {
                        DBGLOG(cpu_handle,my_cpu,MP_KDP);
                        i_bit_clear(MP_KDP, my_word);

-                       mp_kdp_wait();
+/* Ensure that the i386_kernel_state at the base of the
+ * current thread's stack (if any) is synchronized with the
+ * context at the moment of the interrupt, to facilitate
+ * access through the debugger.
+ */
+                       sync_iss_to_iks(regs);
+                       if (pmsafe_debug && !kdp_snapshot)
+                               pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
+                       mp_kdp_wait(TRUE, FALSE);
+                       if (pmsafe_debug && !kdp_snapshot)
+                               pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);

                } else
 #endif /* MACH_KDP */
                } else
 #endif /* MACH_KDP */

-               if (i_bit(MP_CLOCK, my_word)) {
-                       DBGLOG(cpu_handle,my_cpu,MP_CLOCK);
-                       i_bit_clear(MP_CLOCK, my_word);
-                       hardclock(regs);
-               } else if (i_bit(MP_TLB_FLUSH, my_word)) {
+               if (i_bit(MP_TLB_FLUSH, my_word)) {

                        DBGLOG(cpu_handle,my_cpu,MP_TLB_FLUSH);
                        i_bit_clear(MP_TLB_FLUSH, my_word);
                        pmap_update_interrupt();
                        DBGLOG(cpu_handle,my_cpu,MP_TLB_FLUSH);
                        i_bit_clear(MP_TLB_FLUSH, my_word);
                        pmap_update_interrupt();

+               } else if (i_bit(MP_CALL, my_word)) {
+                       DBGLOG(cpu_handle,my_cpu,MP_CALL);
+                       i_bit_clear(MP_CALL, my_word);
+                       mp_cpus_call_action();
+               } else if (i_bit(MP_CALL_PM, my_word)) {
+                       DBGLOG(cpu_handle,my_cpu,MP_CALL_PM);
+                       i_bit_clear(MP_CALL_PM, my_word);
+                       mp_call_PM();
+               }
+               if (regs == NULL) {
+                       /* Called to poll only for cross-calls and TLB flush */
+                       break;

                } else if (i_bit(MP_AST, my_word)) {
                        DBGLOG(cpu_handle,my_cpu,MP_AST);
                        i_bit_clear(MP_AST, my_word);
                        ast_check(cpu_to_processor(my_cpu));
                } else if (i_bit(MP_AST, my_word)) {
                        DBGLOG(cpu_handle,my_cpu,MP_AST);
                        i_bit_clear(MP_AST, my_word);
                        ast_check(cpu_to_processor(my_cpu));

-#if    MACH_KDB
-               } else if (i_bit(MP_KDB, my_word)) {
-                       extern kdb_is_slave[];
-
-                       i_bit_clear(MP_KDB, my_word);
-                       kdb_is_slave[my_cpu]++;
-                       kdb_kintr();
-#endif /* MACH_KDB */
-               } else if (i_bit(MP_RENDEZVOUS, my_word)) {
-                       DBGLOG(cpu_handle,my_cpu,MP_RENDEZVOUS);
-                       i_bit_clear(MP_RENDEZVOUS, my_word);
-                       mp_rendezvous_action();

                }
        } while (*my_word);
 
                }
        } while (*my_word);
 

-       mp_enable_preemption();
+       return 0;
+}
+
+extern void kprintf_break_lock(void);
+static int
+NMIInterruptHandler(x86_saved_state_t *regs)
+{
+       void            *stackptr;
+       char            pstr[192];
+       uint64_t        now = mach_absolute_time();
+
+       if (panic_active() && !panicDebugging) {
+               if (pmsafe_debug)
+                       pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
+               for(;;)
+                       cpu_pause();
+       }

 
 

+       atomic_incl(&NMIPI_acks, 1);
+       atomic_incl(&NMI_count, 1);
+       sync_iss_to_iks_unconditionally(regs);
+       __asm__ volatile("movq %%rbp, %0" : "=m" (stackptr));
+
+       if (cpu_number() == debugger_cpu)
+               goto NMExit;
+
+       if (NMI_panic_reason == SPINLOCK_TIMEOUT) {
+               snprintf(&pstr[0], sizeof(pstr),
+                       "Panic(CPU %d, time %llu): NMIPI for spinlock acquisition timeout, spinlock: %p, spinlock owner: %p, current_thread: %p, spinlock_owner_cpu: 0x%x\n",
+                       cpu_number(), now, spinlock_timed_out, (void *) spinlock_timed_out->interlock.lock_data, current_thread(), spinlock_owner_cpu);
+               panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
+       } else if (NMI_panic_reason == TLB_FLUSH_TIMEOUT) {
+               snprintf(&pstr[0], sizeof(pstr),
+                       "Panic(CPU %d, time %llu): NMIPI for unresponsive processor: TLB flush timeout, TLB state:0x%x\n",
+                       cpu_number(), now, current_cpu_datap()->cpu_tlb_invalid);
+               panic_i386_backtrace(stackptr, 48, &pstr[0], TRUE, regs);
+       } else if (NMI_panic_reason == CROSSCALL_TIMEOUT) {
+               snprintf(&pstr[0], sizeof(pstr),
+                       "Panic(CPU %d, time %llu): NMIPI for unresponsive processor: cross-call timeout\n",
+                       cpu_number(), now);
+               panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
+       } else if (NMI_panic_reason == INTERRUPT_WATCHDOG) {
+               snprintf(&pstr[0], sizeof(pstr),
+                       "Panic(CPU %d, time %llu): NMIPI for unresponsive processor: interrupt watchdog for vector 0x%x\n",
+                       cpu_number(), now, vector_timed_out);
+               panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
+       }
+       
+#if MACH_KDP
+       if (pmsafe_debug && !kdp_snapshot)
+               pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
+       current_cpu_datap()->cpu_NMI_acknowledged = TRUE;
+       i_bit_clear(MP_KDP, &current_cpu_datap()->cpu_signals);
+       if (panic_active() || NMI_panic_reason != NONE) {
+               mp_kdp_wait(FALSE, TRUE);
+       } else if (!mp_kdp_trap &&
+                  !mp_kdp_is_NMI &&
+                  virtualized && (debug_boot_arg & DB_NMI)) {
+               /*
+                * Under a VMM with the debug boot-arg set, drop into kdp.
+                * Since an NMI is involved, there's a risk of contending with
+                * a panic. And side-effects of NMIs may result in entry into, 
+                * and continuing from, the debugger being unreliable.
+                */
+               if (__sync_bool_compare_and_swap(&mp_kdp_is_NMI, FALSE, TRUE)) {
+                       kprintf_break_lock();
+                       kprintf("Debugger entry requested by NMI\n");
+                       kdp_i386_trap(T_DEBUG, saved_state64(regs), 0, 0);
+                       printf("Debugger entry requested by NMI\n");
+                       mp_kdp_is_NMI = FALSE;
+               } else {
+                       mp_kdp_wait(FALSE, FALSE);
+               }
+       } else {
+               mp_kdp_wait(FALSE, FALSE);
+       }
+       if (pmsafe_debug && !kdp_snapshot)
+               pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
+#endif
+NMExit:        
+       return 1;

 }
 
 }
 

+
+/*
+ * cpu_interrupt is really just to be used by the scheduler to
+ * get a CPU's attention it may not always issue an IPI.  If an
+ * IPI is always needed then use i386_cpu_IPI.
+ */

 void
 cpu_interrupt(int cpu)
 {
 void
 cpu_interrupt(int cpu)
 {

-       boolean_t       state;
+       boolean_t did_IPI = FALSE;
+
+       if (smp_initialized
+           && pmCPUExitIdle(cpu_datap(cpu))) {
+               i386_cpu_IPI(cpu);
+               did_IPI = TRUE;
+       }
+
+       KERNEL_DEBUG_CONSTANT(MACHDBG_CODE(DBG_MACH_SCHED, MACH_REMOTE_AST), cpu, did_IPI, 0, 0, 0);
+}

 
 

+/*
+ * Send a true NMI via the local APIC to the specified CPU.
+ */
+void
+cpu_NMI_interrupt(int cpu)
+{

        if (smp_initialized) {
        if (smp_initialized) {

+               i386_send_NMI(cpu);
+       }
+}

 
 

-               /* Wait for previous interrupt to be delivered... */
-               while (LAPIC_REG(ICR) & LAPIC_ICR_DS_PENDING)
-                       cpu_pause();
+void
+NMI_cpus(void)
+{
+       unsigned int    cpu;
+       boolean_t       intrs_enabled;
+       uint64_t        tsc_timeout;

 
 

-               state = ml_set_interrupts_enabled(FALSE);
-               LAPIC_REG(ICRD) =
-                       cpu_to_lapic[cpu] << LAPIC_ICRD_DEST_SHIFT;
-               LAPIC_REG(ICR)  =
-                       INTERPROCESS_INTERRUPT | LAPIC_ICR_DM_FIXED;
-               (void) ml_set_interrupts_enabled(state);
+       intrs_enabled = ml_set_interrupts_enabled(FALSE);
+
+       for (cpu = 0; cpu < real_ncpus; cpu++) {
+               if (!cpu_is_running(cpu))
+                       continue;
+               cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
+               cpu_NMI_interrupt(cpu);
+               tsc_timeout = !machine_timeout_suspended() ?
+                               rdtsc64() + (1000 * 1000 * 1000 * 10ULL) :
+                               ~0ULL;
+               while (!cpu_datap(cpu)->cpu_NMI_acknowledged) {
+                       handle_pending_TLB_flushes();
+                       cpu_pause();
+                       if (rdtsc64() > tsc_timeout)
+                               panic("NMI_cpus() timeout cpu %d", cpu);
+               }
+               cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;

        }
 
        }
 

+       ml_set_interrupts_enabled(intrs_enabled);
+}
+
+static void    (* volatile mp_PM_func)(void) = NULL;
+
+static void
+mp_call_PM(void)
+{
+       assert(!ml_get_interrupts_enabled());
+
+       if (mp_PM_func != NULL)
+               mp_PM_func();

 }
 
 void
 }
 
 void

-slave_clock(void)
+cpu_PM_interrupt(int cpu)

 {
 {

-       int     cpu;
+       assert(!ml_get_interrupts_enabled());

 
 

-       /*
-        * Clock interrupts are chained from the boot processor
-        * to the next logical processor that is running and from
-        * there on to any further running processor etc.
-        */
-       mp_disable_preemption();
-       for (cpu=cpu_number()+1; cpu<NCPUS; cpu++)
-               if (machine_slot[cpu].running) {
-                       i386_signal_cpu(cpu, MP_CLOCK, ASYNC);
-                       mp_enable_preemption();
-                       return;
-               }
-       mp_enable_preemption();
+       if (mp_PM_func != NULL) {
+               if (cpu == cpu_number())
+                       mp_PM_func();
+               else
+                       i386_signal_cpu(cpu, MP_CALL_PM, ASYNC);
+       }
+}

 
 

+void
+PM_interrupt_register(void (*fn)(void))
+{
+       mp_PM_func = fn;

 }
 
 void
 i386_signal_cpu(int cpu, mp_event_t event, mp_sync_t mode)
 {
 }
 
 void
 i386_signal_cpu(int cpu, mp_event_t event, mp_sync_t mode)
 {

-       volatile int    *signals = &cpu_data[cpu].cpu_signals;
-       uint64_t        timeout;
-       
+       volatile int    *signals = &cpu_datap(cpu)->cpu_signals;
+       uint64_t        tsc_timeout;

 
 

-       if (!cpu_data[cpu].cpu_status)
+       
+       if (!cpu_datap(cpu)->cpu_running)

                return;
 
                return;
 

-       DBGLOG(cpu_signal, cpu, event);
+       if (event == MP_TLB_FLUSH)
+               KERNEL_DEBUG(TRACE_MP_TLB_FLUSH | DBG_FUNC_START, cpu, 0, 0, 0, 0);

 
 

+       DBGLOG(cpu_signal, cpu, event);
+       

        i_bit_set(event, signals);
        i_bit_set(event, signals);

-       cpu_interrupt(cpu);
+       i386_cpu_IPI(cpu);

        if (mode == SYNC) {
           again:
        if (mode == SYNC) {
           again:

-               timeout = rdtsc64() + (1000*1000*1000);
-               while (i_bit(event, signals) && rdtsc64() < timeout) {
+               tsc_timeout = !machine_timeout_suspended() ?
+                                       rdtsc64() + (1000*1000*1000) :
+                                       ~0ULL;
+               while (i_bit(event, signals) && rdtsc64() < tsc_timeout) {

                        cpu_pause();
                }
                if (i_bit(event, signals)) {
                        cpu_pause();
                }
                if (i_bit(event, signals)) {


@@ -589,32 +772,61 @@ i386_signal_cpu(int cpu, mp_event_t event, mp_sync_t mode)
                        goto again;
                }
        }
                        goto again;
                }
        }

+       if (event == MP_TLB_FLUSH)
+               KERNEL_DEBUG(TRACE_MP_TLB_FLUSH | DBG_FUNC_END, cpu, 0, 0, 0, 0);

 }
 
 }
 

-void
-i386_signal_cpus(mp_event_t event, mp_sync_t mode)
+/*
+ * Helper function called when busy-waiting: panic if too long
+ * a TSC-based time has elapsed since the start of the spin.
+ */
+static boolean_t
+mp_spin_timeout(uint64_t tsc_start)

 {
 {

-       int     cpu;
-       int     my_cpu = cpu_number();
+       uint64_t        tsc_timeout;

 
 

-       for (cpu = 0; cpu < NCPUS; cpu++) {
-               if (cpu == my_cpu || !machine_slot[cpu].running)
-                       continue;
-               i386_signal_cpu(cpu, event, mode);
-       }
+       cpu_pause();
+       if (machine_timeout_suspended())
+               return FALSE;
+
+       /*
+        * The timeout is 4 * the spinlock timeout period
+        * unless we have serial console printing (kprintf) enabled
+        * in which case we allow an even greater margin.
+        */
+       tsc_timeout = disable_serial_output ? LockTimeOutTSC << 2
+                                           : LockTimeOutTSC << 4;
+       return  (rdtsc64() > tsc_start + tsc_timeout);

 }
 
 }
 

-int
-i386_active_cpus(void)
+/*
+ * Helper function to take a spinlock while ensuring that incoming IPIs
+ * are still serviced if interrupts are masked while we spin.
+ * Returns current interrupt state.
+ */
+boolean_t
+mp_safe_spin_lock(usimple_lock_t lock)

 {
 {

-       int     cpu;
-       int     ncpus = 0;
-
-       for (cpu = 0; cpu < NCPUS; cpu++) {
-               if (machine_slot[cpu].running)
-                       ncpus++;
-       }
-       return(ncpus);
+       if (ml_get_interrupts_enabled()) {
+               simple_lock(lock);
+               return TRUE;
+       } else {
+               uint64_t tsc_spin_start = rdtsc64();
+               while (!simple_lock_try(lock)) {
+                       cpu_signal_handler(NULL);
+                       if (mp_spin_timeout(tsc_spin_start)) {
+                               uint32_t lock_cpu;
+                               uintptr_t lowner = (uintptr_t)
+                                                  lock->interlock.lock_data;
+                               spinlock_timed_out = lock;
+                               lock_cpu = spinlock_timeout_NMI(lowner);
+                               NMIPI_panic(cpu_to_cpumask(lock_cpu), SPINLOCK_TIMEOUT);
+                               panic("mp_safe_spin_lock() timed out, lock: %p, owner thread: 0x%lx, current_thread: %p, owner on CPU 0x%x, time: %llu",
+                                     lock, lowner, current_thread(), lock_cpu, mach_absolute_time());
+                       }
+               }
+               return FALSE;
+       } 

 }
 
 /*
 }
 
 /*


@@ -632,26 +844,50 @@ i386_active_cpus(void)
  */
 
 static void
  */
 
 static void

-mp_rendezvous_action(void)
+mp_rendezvous_action(__unused void *null)

 {
 {

+       boolean_t       intrs_enabled;
+       uint64_t        tsc_spin_start;

 
        /* setup function */
        if (mp_rv_setup_func != NULL)
                mp_rv_setup_func(mp_rv_func_arg);
 
        /* setup function */
        if (mp_rv_setup_func != NULL)
                mp_rv_setup_func(mp_rv_func_arg);

+
+       intrs_enabled = ml_get_interrupts_enabled();
+

        /* spin on entry rendezvous */
        /* spin on entry rendezvous */

-       atomic_incl(&mp_rv_waiters[0], 1);
-       while (mp_rv_waiters[0] < mp_rv_ncpus)
-               cpu_pause();
+       atomic_incl(&mp_rv_entry, 1);
+       tsc_spin_start = rdtsc64();
+
+       while (mp_rv_entry < mp_rv_ncpus) {
+               /* poll for pesky tlb flushes if interrupts disabled */
+               if (!intrs_enabled)
+                       handle_pending_TLB_flushes();
+               if (mp_spin_timeout(tsc_spin_start)) {
+                       panic("mp_rv_action() entry: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_entry, mp_rv_ncpus, tsc_spin_start, rdtsc64());
+               }
+       }
+

        /* action function */
        if (mp_rv_action_func != NULL)
                mp_rv_action_func(mp_rv_func_arg);
        /* action function */
        if (mp_rv_action_func != NULL)
                mp_rv_action_func(mp_rv_func_arg);

+

        /* spin on exit rendezvous */
        /* spin on exit rendezvous */

-       atomic_incl(&mp_rv_waiters[1], 1);
-       while (mp_rv_waiters[1] < mp_rv_ncpus)
-               cpu_pause();
+       atomic_incl(&mp_rv_exit, 1);
+       tsc_spin_start = rdtsc64();
+       while (mp_rv_exit < mp_rv_ncpus) {
+               if (!intrs_enabled)
+                       handle_pending_TLB_flushes();
+               if (mp_spin_timeout(tsc_spin_start))
+                       panic("mp_rv_action() exit: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_exit, mp_rv_ncpus, tsc_spin_start, rdtsc64());
+       }
+

        /* teardown function */
        if (mp_rv_teardown_func != NULL)
                mp_rv_teardown_func(mp_rv_func_arg);
        /* teardown function */
        if (mp_rv_teardown_func != NULL)
                mp_rv_teardown_func(mp_rv_func_arg);

+
+       /* Bump completion count */
+       atomic_incl(&mp_rv_complete, 1);

 }
 
 void
 }
 
 void


@@ -660,6 +896,7 @@ mp_rendezvous(void (*setup_func)(void *),
              void (*teardown_func)(void *),
              void *arg)
 {
              void (*teardown_func)(void *),
              void *arg)
 {

+       uint64_t        tsc_spin_start;

 
        if (!smp_initialized) {
                if (setup_func != NULL)
 
        if (!smp_initialized) {
                if (setup_func != NULL)


@@ -672,7 +909,7 @@ mp_rendezvous(void (*setup_func)(void *),
        }
                
        /* obtain rendezvous lock */
        }
                
        /* obtain rendezvous lock */

-       simple_lock(&mp_rv_lock);
+       (void) mp_safe_spin_lock(&mp_rv_lock);

 
        /* set static function pointers */
        mp_rv_setup_func = setup_func;
 
        /* set static function pointers */
        mp_rv_setup_func = setup_func;


@@ -680,282 +917,1145 @@ mp_rendezvous(void (*setup_func)(void *),
        mp_rv_teardown_func = teardown_func;
        mp_rv_func_arg = arg;
 
        mp_rv_teardown_func = teardown_func;
        mp_rv_func_arg = arg;
 

-       mp_rv_waiters[0] = 0;           /* entry rendezvous count */
-       mp_rv_waiters[1] = 0;           /* exit  rendezvous count */
-       mp_rv_ncpus = i386_active_cpus();
+       mp_rv_entry    = 0;
+       mp_rv_exit     = 0;
+       mp_rv_complete = 0;

 
        /*
         * signal other processors, which will call mp_rendezvous_action()
         * with interrupts disabled
         */
 
        /*
         * signal other processors, which will call mp_rendezvous_action()
         * with interrupts disabled
         */

-       i386_signal_cpus(MP_RENDEZVOUS, ASYNC);
+       mp_rv_ncpus = mp_cpus_call(CPUMASK_OTHERS, NOSYNC, &mp_rendezvous_action, NULL) + 1;

 
        /* call executor function on this cpu */
 
        /* call executor function on this cpu */

-       mp_rendezvous_action();
+       mp_rendezvous_action(NULL);
+
+       /*
+        * Spin for everyone to complete.
+        * This is necessary to ensure that all processors have proceeded
+        * from the exit barrier before we release the rendezvous structure.
+        */
+       tsc_spin_start = rdtsc64();
+       while (mp_rv_complete < mp_rv_ncpus) {
+               if (mp_spin_timeout(tsc_spin_start))
+                       panic("mp_rendezvous() timeout: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_complete, mp_rv_ncpus, tsc_spin_start, rdtsc64());
+       }
+       
+       /* Tidy up */
+       mp_rv_setup_func = NULL;
+       mp_rv_action_func = NULL;
+       mp_rv_teardown_func = NULL;
+       mp_rv_func_arg = NULL;

 
        /* release lock */
        simple_unlock(&mp_rv_lock);
 }
 
 
        /* release lock */
        simple_unlock(&mp_rv_lock);
 }
 

-#if    MACH_KDP
-volatile boolean_t     mp_kdp_trap = FALSE;
-long                   mp_kdp_ncpus;
-

 void
 void

-mp_kdp_enter(void)
+mp_rendezvous_break_lock(void)

 {
 {

-       int             cpu;
-       int             ncpus;
-       int             my_cpu = cpu_number();
-       boolean_t       state;
-       uint64_t        timeout;
-
-       DBG("mp_kdp_enter()\n");
-
-       /*
-        * Here to enter the debugger.
-        * In case of races, only one cpu is allowed to enter kdp after
-        * stopping others.
-        */
-       state = ml_set_interrupts_enabled(FALSE);
-       simple_lock(&mp_kdp_lock);
-       while (mp_kdp_trap) {
-               simple_unlock(&mp_kdp_lock);
-               DBG("mp_kdp_enter() race lost\n");
-               mp_kdp_wait();
-               simple_lock(&mp_kdp_lock);
-       }
-       mp_kdp_ncpus = 1;       /* self */
-       mp_kdp_trap = TRUE;
-       simple_unlock(&mp_kdp_lock);
-       (void) ml_set_interrupts_enabled(state);
+       simple_lock_init(&mp_rv_lock, 0);
+}

 
 

-       /* Deliver a nudge to other cpus, counting how many */
-       DBG("mp_kdp_enter() signaling other processors\n");
-       for (ncpus = 1, cpu = 0; cpu < NCPUS; cpu++) {
-               if (cpu == my_cpu || !machine_slot[cpu].running)
-                       continue;
-               ncpus++;
-               i386_signal_cpu(cpu, MP_KDP, ASYNC); 
-       }
+static void
+setup_disable_intrs(__unused void * param_not_used)
+{
+       /* disable interrupts before the first barrier */
+       boolean_t intr = ml_set_interrupts_enabled(FALSE);

 
 

-       /* Wait other processors to spin. */
-       DBG("mp_kdp_enter() waiting for (%d) processors to suspend\n", ncpus);
-       timeout = rdtsc64() + (1000*1000*1000);
-       while (*((volatile long *) &mp_kdp_ncpus) != ncpus
-               && rdtsc64() < timeout) {
-               cpu_pause();
-       }
-       DBG("mp_kdp_enter() %d processors done %s\n",
-               mp_kdp_ncpus, (mp_kdp_ncpus == ncpus) ? "OK" : "timed out");
+       current_cpu_datap()->cpu_iflag = intr;
+       DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);

 }
 
 static void
 }
 
 static void

-mp_kdp_wait(void)
+teardown_restore_intrs(__unused void * param_not_used)

 {
 {

-       DBG("mp_kdp_wait()\n");
-       atomic_incl(&mp_kdp_ncpus, 1);
-       while (mp_kdp_trap) {
-               cpu_pause();
-       }
-       atomic_decl(&mp_kdp_ncpus, 1);
-       DBG("mp_kdp_wait() done\n");
+       /* restore interrupt flag following MTRR changes */
+       ml_set_interrupts_enabled(current_cpu_datap()->cpu_iflag);
+       DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);

 }
 
 }
 

+/*
+ * A wrapper to mp_rendezvous() to call action_func() with interrupts disabled.
+ * This is exported for use by kexts.
+ */

 void
 void

-mp_kdp_exit(void)
+mp_rendezvous_no_intrs(
+             void (*action_func)(void *),
+             void *arg)

 {
 {

-       DBG("mp_kdp_exit()\n");
-       atomic_decl(&mp_kdp_ncpus, 1);
-       mp_kdp_trap = FALSE;
+       mp_rendezvous(setup_disable_intrs,
+                     action_func,
+                     teardown_restore_intrs,
+                     arg);     
+}

 
 

-       /* Wait other processors to stop spinning. XXX needs timeout */
-       DBG("mp_kdp_exit() waiting for processors to resume\n");
-       while (*((volatile long *) &mp_kdp_ncpus) > 0) {
-               cpu_pause();
-       }
-       DBG("mp_kdp_exit() done\n");
+
+typedef struct {
+       queue_chain_t   link;                   /* queue linkage */
+       void            (*func)(void *,void *); /* routine to call */
+       void            *arg0;                  /* routine's 1st arg */
+       void            *arg1;                  /* routine's 2nd arg */
+       cpumask_t       *maskp;                 /* completion response mask */
+} mp_call_t;
+
+
+typedef struct {
+       queue_head_t            queue;
+       decl_simple_lock_data(, lock);
+} mp_call_queue_t;
+#define MP_CPUS_CALL_BUFS_PER_CPU      MAX_CPUS
+static mp_call_queue_t mp_cpus_call_freelist;
+static mp_call_queue_t mp_cpus_call_head[MAX_CPUS];
+
+static inline boolean_t
+mp_call_head_lock(mp_call_queue_t *cqp)
+{
+       boolean_t       intrs_enabled;
+
+       intrs_enabled = ml_set_interrupts_enabled(FALSE);
+       simple_lock(&cqp->lock);
+
+       return intrs_enabled;

 }
 }

-#endif /* MACH_KDP */

 
 

+/*
+ * Deliver an NMIPI to a set of processors to cause them to panic .
+ */

 void
 void

-lapic_test(void)
+NMIPI_panic(cpumask_t cpu_mask, NMI_reason_t why) {
+       unsigned int cpu, cpu_bit;
+       uint64_t deadline;
+
+       NMIPI_enable(TRUE);
+       NMI_panic_reason = why;
+
+       for (cpu = 0, cpu_bit = 1; cpu < real_ncpus; cpu++, cpu_bit <<= 1) {
+               if ((cpu_mask & cpu_bit) == 0)
+                       continue;
+               cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
+               cpu_NMI_interrupt(cpu);
+       }
+
+       /* Wait (only so long) for NMi'ed cpus to respond */
+       deadline = mach_absolute_time() + LockTimeOut;
+       for (cpu = 0, cpu_bit = 1; cpu < real_ncpus; cpu++, cpu_bit <<= 1) {
+               if ((cpu_mask & cpu_bit) == 0)
+                       continue;
+               while (!cpu_datap(cpu)->cpu_NMI_acknowledged &&
+                       mach_absolute_time() < deadline) {
+                       cpu_pause();
+               }
+       }
+}
+
+#if MACH_ASSERT
+static inline boolean_t
+mp_call_head_is_locked(mp_call_queue_t *cqp)

 {
 {

-       int     cpu = 1;
+       return !ml_get_interrupts_enabled() &&
+               hw_lock_held((hw_lock_t)&cqp->lock);
+}
+#endif

 
 

-       lapic_dump();
-       i_bit_set(0, &cpu_data[cpu].cpu_signals);
-       cpu_interrupt(1);
+static inline void
+mp_call_head_unlock(mp_call_queue_t *cqp, boolean_t intrs_enabled)
+{
+       simple_unlock(&cqp->lock);
+       ml_set_interrupts_enabled(intrs_enabled);

 }
 
 }
 

-/*ARGSUSED*/
-void
-init_ast_check(
-       processor_t     processor)
+static inline mp_call_t *
+mp_call_alloc(void)
+{
+       mp_call_t       *callp = NULL;
+       boolean_t       intrs_enabled;
+       mp_call_queue_t *cqp = &mp_cpus_call_freelist;
+
+       intrs_enabled = mp_call_head_lock(cqp);
+       if (!queue_empty(&cqp->queue))
+               queue_remove_first(&cqp->queue, callp, typeof(callp), link);
+       mp_call_head_unlock(cqp, intrs_enabled);
+
+       return callp;
+}
+
+static inline void
+mp_call_free(mp_call_t *callp)
+{
+       boolean_t       intrs_enabled;
+       mp_call_queue_t *cqp = &mp_cpus_call_freelist;
+
+       intrs_enabled = mp_call_head_lock(cqp);
+       queue_enter_first(&cqp->queue, callp, typeof(callp), link);
+       mp_call_head_unlock(cqp, intrs_enabled);
+}
+
+static inline mp_call_t *
+mp_call_dequeue_locked(mp_call_queue_t *cqp)
+{
+       mp_call_t       *callp = NULL;
+
+       assert(mp_call_head_is_locked(cqp));
+       if (!queue_empty(&cqp->queue))
+               queue_remove_first(&cqp->queue, callp, typeof(callp), link);
+       return callp;
+}
+
+static inline void
+mp_call_enqueue_locked(
+       mp_call_queue_t *cqp,
+       mp_call_t       *callp)
+{
+       queue_enter(&cqp->queue, callp, typeof(callp), link);
+}
+
+/* Called on the boot processor to initialize global structures */
+static void
+mp_cpus_call_init(void)

 {
 {

+       mp_call_queue_t *cqp = &mp_cpus_call_freelist;
+
+       DBG("mp_cpus_call_init()\n");
+       simple_lock_init(&cqp->lock, 0);
+       queue_init(&cqp->queue);

 }
 
 }
 

+/*
+ * Called at processor registration to add call buffers to the free list
+ * and to initialize the per-cpu call queue.
+ */

 void
 void

-cause_ast_check(
-       processor_t     processor)
+mp_cpus_call_cpu_init(int cpu)

 {
 {

-       int     cpu = processor->slot_num;
+       int             i;
+       mp_call_queue_t *cqp = &mp_cpus_call_head[cpu];
+       mp_call_t       *callp;
+
+       simple_lock_init(&cqp->lock, 0);
+       queue_init(&cqp->queue);
+       for (i = 0; i < MP_CPUS_CALL_BUFS_PER_CPU; i++) {
+               callp = (mp_call_t *) kalloc(sizeof(mp_call_t));
+               mp_call_free(callp);
+       }

 
 

-       if (cpu != cpu_number()) {
-               i386_signal_cpu(cpu, MP_AST, ASYNC);
+       DBG("mp_cpus_call_init(%d) done\n", cpu);
+}
+
+/*
+ * This is called from cpu_signal_handler() to process an MP_CALL signal.
+ * And also from i386_deactivate_cpu() when a cpu is being taken offline.
+ */
+static void
+mp_cpus_call_action(void)
+{
+       mp_call_queue_t *cqp;
+       boolean_t       intrs_enabled;
+       mp_call_t       *callp;
+       mp_call_t       call;
+
+       assert(!ml_get_interrupts_enabled());
+       cqp = &mp_cpus_call_head[cpu_number()];
+       intrs_enabled = mp_call_head_lock(cqp);
+       while ((callp = mp_call_dequeue_locked(cqp)) != NULL) {
+               /* Copy call request to the stack to free buffer */
+               call = *callp;
+               mp_call_free(callp);
+               if (call.func != NULL) {
+                       mp_call_head_unlock(cqp, intrs_enabled);
+                       KERNEL_DEBUG_CONSTANT(
+                               TRACE_MP_CPUS_CALL_ACTION,
+                               VM_KERNEL_UNSLIDE(call.func), VM_KERNEL_UNSLIDE_OR_PERM(call.arg0),
+                               VM_KERNEL_UNSLIDE_OR_PERM(call.arg1), VM_KERNEL_ADDRPERM(call.maskp), 0);
+                       call.func(call.arg0, call.arg1);
+                       (void) mp_call_head_lock(cqp);
+               }
+               if (call.maskp != NULL)
+                       i_bit_set(cpu_number(), call.maskp);

        }
        }

+       mp_call_head_unlock(cqp, intrs_enabled);

 }
 
 /*
 }
 
 /*

- * invoke kdb on slave processors 
+ * mp_cpus_call() runs a given function on cpus specified in a given cpu mask.
+ * Possible modes are:
+ *  SYNC:   function is called serially on target cpus in logical cpu order
+ *         waiting for each call to be acknowledged before proceeding
+ *  ASYNC:  function call is queued to the specified cpus
+ *         waiting for all calls to complete in parallel before returning
+ *  NOSYNC: function calls are queued
+ *         but we return before confirmation of calls completing. 
+ * The action function may be NULL.
+ * The cpu mask may include the local cpu. Offline cpus are ignored.
+ * The return value is the number of cpus on which the call was made or queued.

  */
  */

+cpu_t
+mp_cpus_call(
+       cpumask_t       cpus,
+       mp_sync_t       mode,
+        void           (*action_func)(void *),
+        void           *arg)
+{
+       return mp_cpus_call1(
+                       cpus,
+                       mode,
+                       (void (*)(void *,void *))action_func,
+                       arg,
+                       NULL,
+                       NULL);
+}

 
 

-void
-remote_kdb(void)
+static void
+mp_cpus_call_wait(boolean_t    intrs_enabled,
+                 cpumask_t     cpus_called,
+                 cpumask_t     *cpus_responded)

 {
 {

-       int     my_cpu = cpu_number();
-       int     cpu;
-       
+       mp_call_queue_t         *cqp;
+       uint64_t                tsc_spin_start;
+
+       assert(ml_get_interrupts_enabled() == 0 || get_preemption_level() != 0);
+       cqp = &mp_cpus_call_head[cpu_number()];
+
+       tsc_spin_start = rdtsc64();
+       while (*cpus_responded != cpus_called) {
+               if (!intrs_enabled) {
+                       /* Sniffing w/o locking */
+                       if (!queue_empty(&cqp->queue))
+                               mp_cpus_call_action();
+                       cpu_signal_handler(NULL);
+               }
+               if (mp_spin_timeout(tsc_spin_start)) {
+                       cpumask_t       cpus_unresponsive;
+
+                       cpus_unresponsive = cpus_called & ~(*cpus_responded);
+                       NMIPI_panic(cpus_unresponsive, CROSSCALL_TIMEOUT);
+                       panic("mp_cpus_call_wait() timeout, cpus: 0x%llx",
+                               cpus_unresponsive);
+               }
+       }
+}
+
+cpu_t
+mp_cpus_call1(
+       cpumask_t       cpus,
+       mp_sync_t       mode,
+        void           (*action_func)(void *, void *),
+        void           *arg0,
+        void           *arg1,
+       cpumask_t       *cpus_calledp)
+{
+       cpu_t           cpu = 0;
+       boolean_t       intrs_enabled = FALSE;
+       boolean_t       call_self = FALSE;
+       cpumask_t       cpus_called = 0;
+       cpumask_t       cpus_responded = 0;
+       long            cpus_call_count = 0;
+       uint64_t        tsc_spin_start;
+       boolean_t       topo_lock;
+
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPUS_CALL | DBG_FUNC_START,
+               cpus, mode, VM_KERNEL_UNSLIDE(action_func), VM_KERNEL_UNSLIDE_OR_PERM(arg0), VM_KERNEL_UNSLIDE_OR_PERM(arg1));
+
+       if (!smp_initialized) {
+               if ((cpus & CPUMASK_SELF) == 0)
+                       goto out;
+               if (action_func != NULL) {
+                       intrs_enabled = ml_set_interrupts_enabled(FALSE);
+                       action_func(arg0, arg1);
+                       ml_set_interrupts_enabled(intrs_enabled);
+               }
+               call_self = TRUE;
+               goto out;
+       }
+
+       /*
+        * Queue the call for each non-local requested cpu.
+        * This is performed under the topo lock to prevent changes to
+        * cpus online state and to prevent concurrent rendezvouses --
+        * although an exception is made if we're calling only the master
+        * processor since that always remains active. Note: this exception
+        * is expected for longterm timer nosync cross-calls to the master cpu.
+        */ 

        mp_disable_preemption();
        mp_disable_preemption();

-       for (cpu = 0; cpu < NCPUS; cpu++) {
-               if (cpu == my_cpu || !machine_slot[cpu].running)
+       intrs_enabled = ml_get_interrupts_enabled();
+       topo_lock = (cpus != cpu_to_cpumask(master_cpu));
+       if (topo_lock) {
+               ml_set_interrupts_enabled(FALSE);
+               (void) mp_safe_spin_lock(&x86_topo_lock);
+       }
+       for (cpu = 0; cpu < (cpu_t) real_ncpus; cpu++) {
+               if (((cpu_to_cpumask(cpu) & cpus) == 0) ||
+                   !cpu_is_running(cpu))

                        continue;
                        continue;

-               i386_signal_cpu(cpu, MP_KDB, SYNC);
+               tsc_spin_start = rdtsc64();
+               if (cpu == (cpu_t) cpu_number()) {
+                       /*
+                        * We don't IPI ourself and if calling asynchronously,
+                        * we defer our call until we have signalled all others.
+                        */
+                       call_self = TRUE;
+                       if (mode == SYNC && action_func != NULL) {
+                               KERNEL_DEBUG_CONSTANT(
+                                       TRACE_MP_CPUS_CALL_LOCAL,
+                                       VM_KERNEL_UNSLIDE(action_func),
+                                       VM_KERNEL_UNSLIDE_OR_PERM(arg0), VM_KERNEL_UNSLIDE_OR_PERM(arg1), 0, 0);
+                               action_func(arg0, arg1);
+                       }
+               } else {
+                       /*
+                        * Here to queue a call to cpu and IPI.
+                        */
+                       mp_call_t       *callp = NULL;
+                       mp_call_queue_t *cqp = &mp_cpus_call_head[cpu];
+                       boolean_t       intrs_inner;
+
+               queue_call:
+                       if (callp == NULL)
+                               callp = mp_call_alloc();
+                       intrs_inner = mp_call_head_lock(cqp);
+                       if (callp == NULL) {
+                               mp_call_head_unlock(cqp, intrs_inner);
+                               KERNEL_DEBUG_CONSTANT(
+                                       TRACE_MP_CPUS_CALL_NOBUF,
+                                       cpu, 0, 0, 0, 0);
+                               if (!intrs_inner) {
+                                       /* Sniffing w/o locking */
+                                       if (!queue_empty(&cqp->queue))
+                                               mp_cpus_call_action();
+                                       handle_pending_TLB_flushes();
+                               }
+                               if (mp_spin_timeout(tsc_spin_start))
+                                       panic("mp_cpus_call1() timeout start: 0x%llx, cur: 0x%llx",
+                                             tsc_spin_start, rdtsc64());
+                               goto queue_call;
+                       }
+                       callp->maskp = (mode == NOSYNC) ? NULL : &cpus_responded;
+                       callp->func = action_func;
+                       callp->arg0 = arg0;
+                       callp->arg1 = arg1;
+                       mp_call_enqueue_locked(cqp, callp);
+                       cpus_call_count++;
+                       cpus_called |= cpu_to_cpumask(cpu);
+                       i386_signal_cpu(cpu, MP_CALL, ASYNC);
+                       mp_call_head_unlock(cqp, intrs_inner);
+                       if (mode == SYNC) {
+                               mp_cpus_call_wait(intrs_inner, cpus_called, &cpus_responded);
+                       }
+               }
+       }
+       if (topo_lock) {
+               simple_unlock(&x86_topo_lock);
+               ml_set_interrupts_enabled(intrs_enabled);
+       }
+
+       /* Call locally if mode not SYNC */
+       if (mode != SYNC && call_self ) {
+               KERNEL_DEBUG_CONSTANT(
+                       TRACE_MP_CPUS_CALL_LOCAL,
+                       VM_KERNEL_UNSLIDE(action_func), VM_KERNEL_UNSLIDE_OR_PERM(arg0), VM_KERNEL_UNSLIDE_OR_PERM(arg1), 0, 0);
+               if (action_func != NULL) {
+                       ml_set_interrupts_enabled(FALSE);
+                       action_func(arg0, arg1);
+                       ml_set_interrupts_enabled(intrs_enabled);
+               }

        }
        }

+
+       /* For ASYNC, now wait for all signaled cpus to complete their calls */
+       if (mode == ASYNC)
+               mp_cpus_call_wait(intrs_enabled, cpus_called, &cpus_responded);
+
+       /* Safe to allow pre-emption now */

        mp_enable_preemption();
        mp_enable_preemption();

+
+out:
+       if (call_self){
+               cpus_called |= cpu_to_cpumask(cpu);
+               cpus_call_count++;
+       }
+
+       if (cpus_calledp)
+               *cpus_calledp = cpus_called;
+
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPUS_CALL | DBG_FUNC_END,
+               cpus_call_count, cpus_called, 0, 0, 0);
+
+       return (cpu_t) cpus_call_count;
+}
+
+
+static void
+mp_broadcast_action(__unused void *null)
+{
+   /* call action function */
+   if (mp_bc_action_func != NULL)
+       mp_bc_action_func(mp_bc_func_arg);
+
+   /* if we're the last one through, wake up the instigator */
+   if (atomic_decl_and_test(&mp_bc_count, 1))
+       thread_wakeup(((event_t)(uintptr_t) &mp_bc_count));

 }
 
 /*
 }
 
 /*

- * Clear kdb interrupt
+ * mp_broadcast() runs a given function on all active cpus.
+ * The caller blocks until the functions has run on all cpus.
+ * The caller will also block if there is another pending braodcast.

  */
  */

+void
+mp_broadcast(
+         void (*action_func)(void *),
+         void *arg)
+{
+   if (!smp_initialized) {
+       if (action_func != NULL)
+                  action_func(arg);
+       return;
+   }
+       
+   /* obtain broadcast lock */
+   lck_mtx_lock(&mp_bc_lock);
+
+   /* set static function pointers */
+   mp_bc_action_func = action_func;
+   mp_bc_func_arg = arg;
+
+   assert_wait((event_t)(uintptr_t)&mp_bc_count, THREAD_UNINT);
+
+   /*
+    * signal other processors, which will call mp_broadcast_action()
+    */
+   mp_bc_count = real_ncpus;                           /* assume max possible active */
+   mp_bc_ncpus = mp_cpus_call(CPUMASK_OTHERS, NOSYNC, *mp_broadcast_action, NULL) + 1;
+   atomic_decl(&mp_bc_count, real_ncpus - mp_bc_ncpus);        /* subtract inactive */
+
+   /* call executor function on this cpu */
+   mp_broadcast_action(NULL);
+
+   /* block for other cpus to have run action_func */
+   if (mp_bc_ncpus > 1)
+       thread_block(THREAD_CONTINUE_NULL);
+   else
+       clear_wait(current_thread(), THREAD_AWAKENED);
+       
+   /* release lock */
+   lck_mtx_unlock(&mp_bc_lock);
+}

 
 void
 
 void

-clear_kdb_intr(void)
+mp_cpus_kick(cpumask_t cpus)

 {
 {

+       cpu_t           cpu;
+       boolean_t       intrs_enabled = FALSE;
+
+       intrs_enabled = ml_set_interrupts_enabled(FALSE);
+       mp_safe_spin_lock(&x86_topo_lock);
+
+       for (cpu = 0; cpu < (cpu_t) real_ncpus; cpu++) {
+               if ((cpu == (cpu_t) cpu_number())
+                       || ((cpu_to_cpumask(cpu) & cpus) == 0)
+                       || !cpu_is_running(cpu))
+               {
+                               continue;
+               }
+
+               lapic_send_ipi(cpu, LAPIC_VECTOR(KICK));
+       }
+
+       simple_unlock(&x86_topo_lock);
+       ml_set_interrupts_enabled(intrs_enabled);
+}
+
+void
+i386_activate_cpu(void)
+{
+       cpu_data_t      *cdp = current_cpu_datap();
+
+       assert(!ml_get_interrupts_enabled());
+
+       if (!smp_initialized) {
+               cdp->cpu_running = TRUE;
+               return;
+       }
+
+       mp_safe_spin_lock(&x86_topo_lock);
+       cdp->cpu_running = TRUE;
+       started_cpu();
+       simple_unlock(&x86_topo_lock);
+       flush_tlb_raw();
+}
+
+void
+i386_deactivate_cpu(void)
+{
+       cpu_data_t      *cdp = current_cpu_datap();
+
+       assert(!ml_get_interrupts_enabled());
+ 
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPU_DEACTIVATE | DBG_FUNC_START,
+               0, 0, 0, 0, 0);
+
+       mp_safe_spin_lock(&x86_topo_lock);
+       cdp->cpu_running = FALSE;
+       simple_unlock(&x86_topo_lock);
+
+       /*
+        * Move all of this cpu's timers to the master/boot cpu,
+        * and poke it in case there's a sooner deadline for it to schedule.
+        */
+       timer_queue_shutdown(&cdp->rtclock_timer.queue);
+       mp_cpus_call(cpu_to_cpumask(master_cpu), ASYNC, timer_queue_expire_local, NULL);
+
+#if MONOTONIC
+       mt_cpu_down(cdp);
+#endif /* MONOTONIC */
+
+       /*
+        * Open an interrupt window
+        * and ensure any pending IPI or timer is serviced
+        */

        mp_disable_preemption();
        mp_disable_preemption();

-       i_bit_clear(MP_KDB, &cpu_data[cpu_number()].cpu_signals);
+       ml_set_interrupts_enabled(TRUE);
+
+       while (cdp->cpu_signals && x86_lcpu()->rtcDeadline != EndOfAllTime)
+               cpu_pause();
+       /*
+        * Ensure there's no remaining timer deadline set
+        * - AICPM may have left one active.
+        */
+       setPop(0);
+
+       ml_set_interrupts_enabled(FALSE);

        mp_enable_preemption();
        mp_enable_preemption();

+
+       KERNEL_DEBUG_CONSTANT(
+               TRACE_MP_CPU_DEACTIVATE | DBG_FUNC_END,
+               0, 0, 0, 0, 0);

 }
 
 }
 

+int    pmsafe_debug    = 1;
+
+#if    MACH_KDP
+volatile boolean_t     mp_kdp_trap = FALSE;
+volatile boolean_t     mp_kdp_is_NMI = FALSE;
+volatile unsigned long mp_kdp_ncpus;
+boolean_t              mp_kdp_state;
+
+

 void
 void

-slave_machine_init(void)
+mp_kdp_enter(boolean_t proceed_on_failure)

 {
 {

-       int     my_cpu;
+       unsigned int    cpu;
+       unsigned int    ncpus = 0;
+       unsigned int    my_cpu;
+       uint64_t        tsc_timeout;

 
 

-       /* Ensure that caching and write-through are enabled */
-       set_cr0(get_cr0() & ~(CR0_NW|CR0_CD));
+       DBG("mp_kdp_enter()\n");

 
 

-       mp_disable_preemption();
-       my_cpu = get_cpu_number();
+       /*
+        * Here to enter the debugger.
+        * In case of races, only one cpu is allowed to enter kdp after
+        * stopping others.
+        */
+       mp_kdp_state = ml_set_interrupts_enabled(FALSE);
+       my_cpu = cpu_number();

 
 

-       DBG("slave_machine_init() CPU%d: phys (%d) active.\n",
-               my_cpu, get_cpu_phys_number());
+       if (my_cpu == (unsigned) debugger_cpu) {
+               kprintf("\n\nRECURSIVE DEBUGGER ENTRY DETECTED\n\n");
+               kdp_reset();
+               return;
+       }

 
 

-       lapic_init();
+       uint64_t start_time = cpu_datap(my_cpu)->debugger_entry_time = mach_absolute_time();
+       int locked = 0;
+       while (!locked || mp_kdp_trap) {
+               if (locked) {
+                       simple_unlock(&x86_topo_lock);
+               }
+               if (proceed_on_failure) {
+                       if (mach_absolute_time() - start_time > 500000000ll) {
+                               kprintf("mp_kdp_enter() can't get x86_topo_lock! Debugging anyway! #YOLO\n");
+                               break;
+                       }
+                       locked = simple_lock_try(&x86_topo_lock);
+                       if (!locked) {
+                               cpu_pause();
+                       }
+               } else {
+                       mp_safe_spin_lock(&x86_topo_lock);
+                       locked = TRUE;
+               }

 
 

-       init_fpu();
+               if (locked && mp_kdp_trap) {
+                       simple_unlock(&x86_topo_lock);
+                       DBG("mp_kdp_enter() race lost\n");
+#if MACH_KDP
+                       mp_kdp_wait(TRUE, FALSE);
+#endif
+                       locked = FALSE;
+               }
+       }

 
 

-       cpu_machine_init();
+       if (pmsafe_debug && !kdp_snapshot)
+               pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);

 
 

-       mp_enable_preemption();
+       debugger_cpu = my_cpu;
+       ncpus = 1;
+       atomic_incl((volatile long *)&mp_kdp_ncpus, 1);
+       mp_kdp_trap = TRUE;
+       debugger_entry_time = cpu_datap(my_cpu)->debugger_entry_time;

 
 

-#ifdef MP_DEBUG
-       lapic_dump();
-       lapic_cpu_map_dump();
-#endif /* MP_DEBUG */
+       /*
+        * Deliver a nudge to other cpus, counting how many
+        */
+       DBG("mp_kdp_enter() signaling other processors\n");
+       if (force_immediate_debugger_NMI == FALSE) {
+               for (cpu = 0; cpu < real_ncpus; cpu++) {
+                       if (cpu == my_cpu || !cpu_is_running(cpu))
+                               continue;
+                       ncpus++;
+                       i386_signal_cpu(cpu, MP_KDP, ASYNC);
+               }
+               /*
+                * Wait other processors to synchronize
+                */
+               DBG("mp_kdp_enter() waiting for (%d) processors to suspend\n", ncpus);
+
+               /*
+                * This timeout is rather arbitrary; we don't want to NMI
+                * processors that are executing at potentially
+                * "unsafe-to-interrupt" points such as the trampolines,
+                * but neither do we want to lose state by waiting too long.
+                */
+               tsc_timeout = rdtsc64() + (LockTimeOutTSC);
+
+               while (mp_kdp_ncpus != ncpus && rdtsc64() < tsc_timeout) {
+                       /*
+                        * A TLB shootdown request may be pending--this would
+                        * result in the requesting processor waiting in
+                        * PMAP_UPDATE_TLBS() until this processor deals with it.
+                        * Process it, so it can now enter mp_kdp_wait()
+                        */
+                       handle_pending_TLB_flushes();
+                       cpu_pause();
+               }
+               /* If we've timed out, and some processor(s) are still unresponsive,
+                * interrupt them with an NMI via the local APIC, iff a panic is
+                * in progress.
+                */
+               if (panic_active()) {
+                       NMIPI_enable(TRUE);
+               }
+               if (mp_kdp_ncpus != ncpus) {
+                       cpumask_t cpus_NMI_pending = 0;
+                       DBG("mp_kdp_enter() timed-out on cpu %d, NMI-ing\n", my_cpu);
+                       for (cpu = 0; cpu < real_ncpus; cpu++) {
+                               if (cpu == my_cpu || !cpu_is_running(cpu))
+                                       continue;
+                               if (cpu_signal_pending(cpu, MP_KDP)) {
+                                       cpus_NMI_pending |= cpu_to_cpumask(cpu);
+                                       cpu_NMI_interrupt(cpu);
+                               }
+                       }
+                       /* Wait again for the same timeout */
+                       tsc_timeout = rdtsc64() + (LockTimeOutTSC);
+                       while (mp_kdp_ncpus != ncpus && rdtsc64() < tsc_timeout) {
+                               handle_pending_TLB_flushes();
+                               cpu_pause();
+                       }
+                       if (mp_kdp_ncpus != ncpus) {
+                               kdb_printf("mp_kdp_enter(): %llu, %lu, %u TIMED-OUT WAITING FOR NMI-ACK, PROCEEDING\n", cpus_NMI_pending, mp_kdp_ncpus, ncpus);
+                       }
+               }
+       }
+       else
+               for (cpu = 0; cpu < real_ncpus; cpu++) {
+                       if (cpu == my_cpu || !cpu_is_running(cpu))
+                               continue;
+                       cpu_NMI_interrupt(cpu);
+               }

 
 

+       if (locked) {
+               simple_unlock(&x86_topo_lock);
+       }
+
+       DBG("mp_kdp_enter() %d processors done %s\n",
+           (int)mp_kdp_ncpus, (mp_kdp_ncpus == ncpus) ? "OK" : "timed out");
+       
+       postcode(MP_KDP_ENTER);

 }
 
 }
 

-#undef cpu_number()
-int cpu_number(void)
+static boolean_t
+cpu_signal_pending(int cpu, mp_event_t event)

 {
 {

-       return get_cpu_number();
+       volatile int    *signals = &cpu_datap(cpu)->cpu_signals;
+       boolean_t retval = FALSE;
+
+       if (i_bit(event, signals))
+               retval = TRUE;
+       return retval;

 }
 
 }
 

-#if    MACH_KDB
-#include <ddb/db_output.h>
+long kdp_x86_xcpu_invoke(const uint16_t lcpu, kdp_x86_xcpu_func_t func,
+                        void *arg0, void *arg1)
+{
+       if (lcpu > (real_ncpus - 1))
+               return -1;
+
+        if (func == NULL)
+               return -1;
+
+       kdp_xcpu_call_func.func = func;
+        kdp_xcpu_call_func.ret  = -1;
+       kdp_xcpu_call_func.arg0 = arg0;
+       kdp_xcpu_call_func.arg1 = arg1;
+       kdp_xcpu_call_func.cpu  = lcpu;
+       DBG("Invoking function %p on CPU %d\n", func, (int32_t)lcpu);
+       while (kdp_xcpu_call_func.cpu != KDP_XCPU_NONE)
+               cpu_pause();
+        return kdp_xcpu_call_func.ret;
+}

 
 

-#define TRAP_DEBUG 0 /* Must match interrupt.s and spl.s */
+static void
+kdp_x86_xcpu_poll(void)
+{
+       if ((uint16_t)cpu_number() == kdp_xcpu_call_func.cpu) {
+            kdp_xcpu_call_func.ret = 
+                   kdp_xcpu_call_func.func(kdp_xcpu_call_func.arg0,
+                                           kdp_xcpu_call_func.arg1,
+                                           cpu_number());
+               kdp_xcpu_call_func.cpu = KDP_XCPU_NONE;
+       }
+}

 
 

+static void
+mp_kdp_wait(boolean_t flush, boolean_t isNMI)
+{
+       DBG("mp_kdp_wait()\n");

 
 

-#if    TRAP_DEBUG
-#define MTRAPS 100
-struct mp_trap_hist_struct {
-       unsigned char type;
-       unsigned char data[5];
-} trap_hist[MTRAPS], *cur_trap_hist = trap_hist,
-    *max_trap_hist = &trap_hist[MTRAPS];
+       current_cpu_datap()->debugger_ipi_time = mach_absolute_time();
+#if CONFIG_MCA
+       /* If we've trapped due to a machine-check, save MCA registers */
+       mca_check_save();
+#endif
+
+       atomic_incl((volatile long *)&mp_kdp_ncpus, 1);
+       while (mp_kdp_trap || (isNMI == TRUE)) {
+               /*
+                * A TLB shootdown request may be pending--this would result
+                * in the requesting processor waiting in PMAP_UPDATE_TLBS()
+                * until this processor handles it.
+                * Process it, so it can now enter mp_kdp_wait()
+                */
+               if (flush)
+                       handle_pending_TLB_flushes();
+
+               kdp_x86_xcpu_poll();
+               cpu_pause();
+       }

 
 

-void db_trap_hist(void);
+       atomic_decl((volatile long *)&mp_kdp_ncpus, 1);
+       DBG("mp_kdp_wait() done\n");
+}

 
 

-/*
- * SPL:
- *     1: new spl
- *     2: old spl
- *     3: new tpr
- *     4: old tpr
- * INT:
- *     1: int vec
- *     2: old spl
- *     3: new spl
- *     4: post eoi tpr
- *     5: exit tpr
- */
+void
+mp_kdp_exit(void)
+{
+       DBG("mp_kdp_exit()\n");
+       debugger_cpu = -1;
+       atomic_decl((volatile long *)&mp_kdp_ncpus, 1);
+
+       debugger_exit_time = mach_absolute_time();
+
+       mp_kdp_trap = FALSE;
+       mfence();
+
+       /* Wait other processors to stop spinning. XXX needs timeout */
+       DBG("mp_kdp_exit() waiting for processors to resume\n");
+       while (mp_kdp_ncpus > 0) {
+               /*
+                * a TLB shootdown request may be pending... this would result in the requesting
+                * processor waiting in PMAP_UPDATE_TLBS() until this processor deals with it.
+                * Process it, so it can now enter mp_kdp_wait()
+                */
+               handle_pending_TLB_flushes();
+
+               cpu_pause();
+       }
+
+       if (pmsafe_debug && !kdp_snapshot)
+           pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
+
+       debugger_exit_time = mach_absolute_time();

 
 

+       DBG("mp_kdp_exit() done\n");
+       (void) ml_set_interrupts_enabled(mp_kdp_state);
+       postcode(MP_KDP_EXIT);
+}
+
+#endif /* MACH_KDP */
+
+boolean_t
+mp_recent_debugger_activity(void) {
+       uint64_t abstime = mach_absolute_time();
+       return (((abstime - debugger_entry_time) < LastDebuggerEntryAllowance) ||
+           ((abstime - debugger_exit_time) < LastDebuggerEntryAllowance));
+}
+
+/*ARGSUSED*/

 void
 void

-db_trap_hist(void)
-{
-       int i,j;
-       for(i=0;i<MTRAPS;i++)
-           if (trap_hist[i].type == 1 || trap_hist[i].type == 2) {
-                   db_printf("%s%s",
-                             (&trap_hist[i]>=cur_trap_hist)?"*":" ",
-                             (trap_hist[i].type == 1)?"SPL":"INT");
-                   for(j=0;j<5;j++)
-                       db_printf(" %02x", trap_hist[i].data[j]);
-                   db_printf("\n");
-           }
-               
+init_ast_check(
+       __unused processor_t    processor)
+{

 }
 }

-#endif /* TRAP_DEBUG */

 
 

-void db_lapic(int cpu);
-unsigned int db_remote_read(int cpu, int reg);
-void db_ioapic(unsigned int);
-void kdb_console(void);
+void
+cause_ast_check(
+       processor_t     processor)
+{
+       int     cpu = processor->cpu_id;
+
+       if (cpu != cpu_number()) {
+               i386_signal_cpu(cpu, MP_AST, ASYNC);
+               KERNEL_DEBUG_CONSTANT(MACHDBG_CODE(DBG_MACH_SCHED, MACH_REMOTE_AST), cpu, 1, 0, 0, 0);
+       }
+}

 
 void
 
 void

-kdb_console(void)
+slave_machine_init(void *param)
+{
+       /*
+        * Here in process context, but with interrupts disabled.
+        */
+       DBG("slave_machine_init() CPU%d\n", get_cpu_number());
+
+       if (param == FULL_SLAVE_INIT) {
+               /*
+                * Cold start
+                */
+               clock_init();
+       }
+       cpu_machine_init();     /* Interrupts enabled hereafter */
+}
+
+#undef cpu_number
+int cpu_number(void)

 {
 {

+       return get_cpu_number();

 }
 
 }
 

-#define BOOLP(a) ((a)?' ':'!')
+static void
+cpu_prewarm_init()
+{
+       int i;

 
 

-static char *DM[8] = {
-       "Fixed",
-       "Lowest Priority",
-       "Invalid",
-       "Invalid",
-       "NMI",
-       "Reset",
-       "Invalid",
-       "ExtINT"};
+       simple_lock_init(&cpu_warm_lock, 0);
+       queue_init(&cpu_warm_call_list);
+       for (i = 0; i < NUM_CPU_WARM_CALLS; i++) {
+               enqueue_head(&cpu_warm_call_list, (queue_entry_t)&cpu_warm_call_arr[i]);
+       }
+}

 
 

-unsigned int
-db_remote_read(int cpu, int reg)
+static timer_call_t
+grab_warm_timer_call()

 {
 {

-       return -1;
+       spl_t x;
+       timer_call_t call = NULL;
+
+       x = splsched();
+       simple_lock(&cpu_warm_lock);
+       if (!queue_empty(&cpu_warm_call_list)) {
+               call = (timer_call_t) dequeue_head(&cpu_warm_call_list);
+       }
+       simple_unlock(&cpu_warm_lock);
+       splx(x);
+
+       return call;

 }
 
 }
 

-void
-db_lapic(int cpu)
+static void
+free_warm_timer_call(timer_call_t call)

 {
 {

+       spl_t x;
+
+       x = splsched();
+       simple_lock(&cpu_warm_lock);
+       enqueue_head(&cpu_warm_call_list, (queue_entry_t)call);
+       simple_unlock(&cpu_warm_lock);
+       splx(x);

 }
 
 }
 

+/*
+ * Runs in timer call context (interrupts disabled).
+ */
+static void
+cpu_warm_timer_call_func(
+               call_entry_param_t p0,
+               __unused call_entry_param_t p1)
+{
+       free_warm_timer_call((timer_call_t)p0);
+       return;
+}
+
+/*
+ * Runs with interrupts disabled on the CPU we wish to warm (i.e. CPU 0).
+ */
+static void
+_cpu_warm_setup(
+               void *arg)
+{
+       cpu_warm_data_t cwdp = (cpu_warm_data_t)arg;
+
+       timer_call_enter(cwdp->cwd_call, cwdp->cwd_deadline, TIMER_CALL_SYS_CRITICAL | TIMER_CALL_LOCAL);
+       cwdp->cwd_result = 0;
+
+       return;
+}
+
+/*
+ * Not safe to call with interrupts disabled.
+ */
+kern_return_t
+ml_interrupt_prewarm(
+       uint64_t        deadline)
+{
+       struct cpu_warm_data cwd;
+       timer_call_t call;
+       cpu_t ct;
+
+       if (ml_get_interrupts_enabled() == FALSE) {
+               panic("%s: Interrupts disabled?\n", __FUNCTION__);
+       }
+
+       /* 
+        * If the platform doesn't need our help, say that we succeeded. 
+        */
+       if (!ml_get_interrupt_prewake_applicable()) {
+               return KERN_SUCCESS;
+       }
+
+       /*
+        * Grab a timer call to use.
+        */
+       call = grab_warm_timer_call();
+       if (call == NULL) {
+               return KERN_RESOURCE_SHORTAGE;
+       }
+
+       timer_call_setup(call, cpu_warm_timer_call_func, call);
+       cwd.cwd_call = call;
+       cwd.cwd_deadline = deadline;
+       cwd.cwd_result = 0;
+
+       /*
+        * For now, non-local interrupts happen on the master processor.
+        */
+       ct = mp_cpus_call(cpu_to_cpumask(master_cpu), SYNC, _cpu_warm_setup, &cwd);
+       if (ct == 0) {
+               free_warm_timer_call(call);
+               return KERN_FAILURE;
+       } else {
+               return cwd.cwd_result;
+       }
+}
+
+#if DEBUG || DEVELOPMENT

 void
 void

-db_ioapic(unsigned int ind)
+kernel_spin(uint64_t spin_ns)

 {
 {

+       boolean_t       istate;
+       uint64_t        spin_abs;
+       uint64_t        deadline;
+       cpu_data_t      *cdp;
+
+       kprintf("kernel_spin(%llu) spinning uninterruptibly\n", spin_ns);
+       istate = ml_set_interrupts_enabled(FALSE);
+       cdp = current_cpu_datap();
+       nanoseconds_to_absolutetime(spin_ns, &spin_abs);
+
+       /* Fake interrupt handler entry for testing mp_interrupt_watchdog() */
+       cdp->cpu_int_event_time = mach_absolute_time();
+       cdp->cpu_int_state = (void *) USER_STATE(current_thread());
+
+       deadline = mach_absolute_time() + spin_ns;
+       while (mach_absolute_time() < deadline)
+               cpu_pause();
+
+       cdp->cpu_int_event_time = 0;
+       cdp->cpu_int_state = NULL;
+
+       ml_set_interrupts_enabled(istate);
+       kprintf("kernel_spin() continuing\n");

 }
 
 }
 

-#endif /* MACH_KDB */
+/*
+ * Called from the scheduler's maintenance thread,
+ * scan running processors for long-running ISRs and:
+ *  - panic if longer than LockTimeOut, or
+ *  - log if more than a quantum.
+ */
+void
+mp_interrupt_watchdog(void)
+{
+       cpu_t                   cpu;
+       boolean_t               intrs_enabled = FALSE;
+       uint16_t                cpu_int_num;
+       uint64_t                cpu_int_event_time;
+       uint64_t                cpu_rip;
+       uint64_t                cpu_int_duration;
+       uint64_t                now;
+       x86_saved_state_t       *cpu_int_state;
+
+       if (__improbable(!mp_interrupt_watchdog_enabled))
+               return;

 
 

+       intrs_enabled = ml_set_interrupts_enabled(FALSE);
+       now = mach_absolute_time();
+       /*
+        * While timeouts are not suspended,
+        * check all other processors for long outstanding interrupt handling.
+        */
+       for (cpu = 0;
+            cpu < (cpu_t) real_ncpus && !machine_timeout_suspended();
+            cpu++) {
+               if ((cpu == (cpu_t) cpu_number()) ||
+                   (!cpu_is_running(cpu)))
+                       continue;
+               cpu_int_event_time = cpu_datap(cpu)->cpu_int_event_time;
+               if (cpu_int_event_time == 0)
+                       continue;
+               if (__improbable(now < cpu_int_event_time))
+                       continue;       /* skip due to inter-processor skew */
+               cpu_int_state = cpu_datap(cpu)->cpu_int_state;
+               if (__improbable(cpu_int_state == NULL))
+                       /* The interrupt may have been dismissed */
+                       continue;
+
+               /* Here with a cpu handling an interrupt */
+
+               cpu_int_duration = now - cpu_int_event_time;
+               if (__improbable(cpu_int_duration > LockTimeOut)) {
+                       cpu_int_num = saved_state64(cpu_int_state)->isf.trapno;
+                       cpu_rip = saved_state64(cpu_int_state)->isf.rip;
+                       vector_timed_out = cpu_int_num;
+                       NMIPI_panic(cpu_to_cpumask(cpu), INTERRUPT_WATCHDOG);
+                       panic("Interrupt watchdog, "
+                               "cpu: %d interrupt: 0x%x time: %llu..%llu state: %p RIP: 0x%llx",
+                               cpu, cpu_int_num, cpu_int_event_time, now, cpu_int_state, cpu_rip);
+                       /* NOT REACHED */
+               } else if (__improbable(cpu_int_duration > (uint64_t) std_quantum)) {
+                       mp_interrupt_watchdog_events++;
+                       cpu_int_num = saved_state64(cpu_int_state)->isf.trapno;
+                       cpu_rip = saved_state64(cpu_int_state)->isf.rip;
+                       ml_set_interrupts_enabled(intrs_enabled);
+                       printf("Interrupt watchdog, "
+                               "cpu: %d interrupt: 0x%x time: %llu..%llu RIP: 0x%llx\n",
+                               cpu, cpu_int_num, cpu_int_event_time, now, cpu_rip);
+                       return;
+               }
+       }
+
+       ml_set_interrupts_enabled(intrs_enabled);
+}
+#endif