xnu-1228.3.13.tar.gz

[apple/xnu.git] / osfmk / ppc / commpage / cacheflush.s

diff --git a/osfmk/ppc/commpage/cacheflush.s b/osfmk/ppc/commpage/cacheflush.s
index 8b53f91e93b829e39dd509cb7c42dfc683295658..43d7452eaeaa84a97af4d84ea4539f30bebe2b31 100644 (file)
--- a/osfmk/ppc/commpage/cacheflush.s
+++ b/osfmk/ppc/commpage/cacheflush.s
@@ -1,26 +1,31 @@
 /*
  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
  *
 /*
  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
  *

- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@

  * 
  * 

- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License").  You may not use this file except in compliance with the
- * License.  Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.

  * 
  * 

- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
+ * 
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER

  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,

- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.

  * 
  * 

- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@

  */
 
  */
 

-#define        ASSEMBLER

 #include <sys/appleapiopts.h>
 #include <ppc/asm.h>                                   // EXT, LEXT
 #include <machine/cpu_capabilities.h>
 #include <sys/appleapiopts.h>
 #include <ppc/asm.h>                                   // EXT, LEXT
 #include <machine/cpu_capabilities.h>


@@ -28,19 +33,19 @@
 
         .text
         .align 2
 
         .text
         .align 2

-        .globl EXT(commpage_flush_dcache)
-        .globl EXT(commpage_flush_icache)

 
 
 // *********************************************
 // * C O M M P A G E _ F L U S H _ D C A C H E *
 // *********************************************
 //
 
 
 // *********************************************
 // * C O M M P A G E _ F L U S H _ D C A C H E *
 // *********************************************
 //

+// Note that this routine is called both in 32 and 64-bit mode.
+//

 //     r3 = ptr to 1st byte to flush
 //     r4 = length to flush (may be 0)
 
 commpage_flush_dcache:
 //     r3 = ptr to 1st byte to flush
 //     r4 = length to flush (may be 0)
 
 commpage_flush_dcache:

-        cmpwi  r4,0                    // length 0?
+        mr.     r4,r4           // test length for 0 in mode-independent way

         lhz            r5,_COMM_PAGE_CACHE_LINESIZE(0)
         subi   r9,r5,1                 // get (linesize-1)
         and            r0,r3,r9                // get offset within line of 1st byte
         lhz            r5,_COMM_PAGE_CACHE_LINESIZE(0)
         subi   r9,r5,1                 // get (linesize-1)
         and            r0,r3,r9                // get offset within line of 1st byte


@@ -56,18 +61,20 @@ commpage_flush_dcache:
         sync                                   // make sure lines are flushed before we return
         blr
         
         sync                                   // make sure lines are flushed before we return
         blr
         

-        COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,0)       // matches all CPUs
+       COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth)

         
         
 // *********************************************
 // * C O M M P A G E _ F L U S H _ I C A C H E *
 // *********************************************
 //
         
         
 // *********************************************
 // * C O M M P A G E _ F L U S H _ I C A C H E *
 // *********************************************
 //

+// Note that this routine is called both in 32 and 64-bit mode.
+//

 //     r3 = ptr to 1st byte to flush
 //     r4 = length to flush (may be 0)
 
 commpage_flush_icache:
 //     r3 = ptr to 1st byte to flush
 //     r4 = length to flush (may be 0)
 
 commpage_flush_icache:

-        cmpwi  r4,0                    // length 0?
+        mr.     r4,r4           // test length for 0 in mode-independent way

         lhz            r5,_COMM_PAGE_CACHE_LINESIZE(0)
         subi   r9,r5,1                 // get (linesize-1)
         and            r0,r3,r9                // get offset within line of 1st byte
         lhz            r5,_COMM_PAGE_CACHE_LINESIZE(0)
         subi   r9,r5,1                 // get (linesize-1)
         and            r0,r3,r9                // get offset within line of 1st byte


@@ -88,10 +95,16 @@ commpage_flush_icache:
         icbi   0,r7
         add            r7,r7,r5
         bne            2b
         icbi   0,r7
         add            r7,r7,r5
         bne            2b

+        
+        // The following sync is only needed on MP machines, probably only on
+        // 7400-family MP machines.  But because we're not certain of this, and
+        // this isn't a speed critical routine, we are conservative and always sync.
+        
+        sync                                   // wait until other processors see the icbi's

         isync                                  // make sure we haven't prefetched old instructions
         
         blr
 
         isync                                  // make sure we haven't prefetched old instructions
         
         blr
 

-        COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,0)       // matches all CPUs
+       COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth)