+ CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_LOCKED,
+ 0, 0, make_brand_string, "A", "CPU brand string");
+
+
+static
+SYSCTL_INT(_machdep, OID_AUTO, lck_mtx_adaptive_spin_mode,
+ CTLFLAG_RW, &lck_mtx_adaptive_spin_mode, 0,
+ "Enable adaptive spin behavior for kernel mutexes");
+
+static int
+virtual_address_size SYSCTL_HANDLER_ARGS
+{
+#pragma unused(arg1, arg2, oidp)
+ int return_value = 64 - T0SZ_BOOT;
+ return SYSCTL_OUT(req, &return_value, sizeof(return_value));
+}
+
+static
+SYSCTL_PROC(_machdep, OID_AUTO, virtual_address_size,
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_LOCKED,
+ 0, 0, virtual_address_size, "I",
+ "Number of addressable bits in userspace virtual addresses");
+
+
+#if DEVELOPMENT || DEBUG
+extern uint64_t TLockTimeOut;
+SYSCTL_QUAD(_machdep, OID_AUTO, tlto,
+ CTLFLAG_RW | CTLFLAG_LOCKED, &TLockTimeOut,
+ "Ticket spinlock timeout (MATUs): use with care");
+
+/*
+ * macro to generate a sysctl machdep.cpu.sysreg_* for a given system register
+ * using __builtin_arm_rsr64.
+ */
+#define SYSCTL_PROC_MACHDEP_CPU_SYSREG(name) \
+static int \
+sysctl_sysreg_##name SYSCTL_HANDLER_ARGS \
+{ \
+_Pragma("unused(arg1, arg2, oidp)") \
+ uint64_t return_value = __builtin_arm_rsr64(#name); \
+ return SYSCTL_OUT(req, &return_value, sizeof(return_value)); \
+} \
+SYSCTL_PROC(_machdep_cpu, OID_AUTO, sysreg_##name, \
+ CTLFLAG_RD | CTLTYPE_QUAD | CTLFLAG_LOCKED, \
+ 0, 0, sysctl_sysreg_##name, "Q", \
+ #name " register on the current CPU");
+
+
+// CPU system registers
+// ARM64: AArch64 Vector Base Address Register
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(VBAR_EL1);
+// ARM64: AArch64 Memory Attribute Indirection Register
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(MAIR_EL1);
+// ARM64: AArch64 Translation table base register 1
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(TTBR1_EL1);
+// ARM64: AArch64 System Control Register
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(SCTLR_EL1);
+// ARM64: AArch64 Translation Control Register
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(TCR_EL1);
+// ARM64: AArch64 Memory Model Feature Register 0
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(ID_AA64MMFR0_EL1);
+// ARM64: AArch64 Instruction Set Attribute Register 1
+SYSCTL_PROC_MACHDEP_CPU_SYSREG(ID_AA64ISAR1_EL1);
+
+#endif /* DEVELOPMENT || DEBUG */
+