/* H4 (ARMv7 architecture) */
#define CPU_PART_CORTEXA9 0xC09
-/* H5 (SWIFT architecture) */
-#define CPU_PART_SWIFT 0x0
-
-/* H6 (ARMv8 architecture) */
-#define CPU_PART_CYCLONE 0x1
-
/* H7 (ARMv8 architecture) */
#define CPU_PART_TYPHOON 0x2
/* H11G e-Core (ARMv8 architecture) */
#define CPU_PART_TEMPEST_ARUBA 0x11
+/* H12 p-Core (ARMv8 architecture) */
+#define CPU_PART_LIGHTNING 0x12
+
+/* H12 e-Core (ARMv8 architecture) */
+#define CPU_PART_THUNDER 0x13
+
+#ifndef RC_HIDE_XNU_FIRESTORM
+/*
+ * Whilst this is a Thunder-based SoC, it
+ * hasn't been released and should remain
+ * hidden in 2020 seeds.
+ */
+/* M10 e-Core (ARMv8 architecture) */
+#define CPU_PART_THUNDER_M10 0x26
+#endif
+
+#ifndef RC_HIDE_XNU_FIRESTORM
+
+/* H13 e-Core */
+#define CPU_PART_ICESTORM 0x20
+
+/* H13 p-Core */
+#define CPU_PART_FIRESTORM 0x21
+
+/* H13G e-Core */
+#define CPU_PART_ICESTORM_TONGA 0x22
+
+/* H13G p-Core */
+#define CPU_PART_FIRESTORM_TONGA 0x23
+
+#endif /* !RC_HIDE_XNU_FIRESTORM */
+
+
/* Cache type identification */
extern void do_cpuid(void);
extern arm_cpu_info_t *cpuid_info(void);
extern int cpuid_get_cpufamily(void);
+extern int cpuid_get_cpusubfamily(void);
extern void do_debugid(void);
extern arm_debug_info_t *arm_debug_info(void);