xnu-1228.9.59.tar.gz

[apple/xnu.git] / osfmk / i386 / proc_reg.h

diff --git a/osfmk/i386/proc_reg.h b/osfmk/i386/proc_reg.h
index 27ca1e7ed77aa3f92e1e671a11a1e02717f082f5..a74ca7548c8ac314fbac6f0aca297f2fbf03763d 100644 (file)
--- a/osfmk/i386/proc_reg.h
+++ b/osfmk/i386/proc_reg.h
@@ -1,23 +1,29 @@
 /*
- * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
  *
- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
  * 
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License").  You may not use this file except in compliance with the
- * License.  Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.
  * 
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
+ * 
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.
  * 
- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  */
 /*
  * @OSF_COPYRIGHT@
@@ -139,6 +145,7 @@
 /*
  * CR4
  */
+#define CR4_VMXE 0x00002000    /* Enable VMX operation */
 #define CR4_FXS 0x00000200     /* SSE/SSE2 OS supports FXSave */
 #define CR4_XMM 0x00000400     /* SSE/SSE2 instructions supported in OS */
 #define CR4_PGE 0x00000080     /* p6:   Page Global Enable */
@@ -232,6 +239,8 @@ static inline void lldt(unsigned int seg)
 
 #ifdef MACH_KERNEL_PRIVATE
 extern void flush_tlb64(void);
+extern uint64_t get64_cr3(void);
+extern void set64_cr3(uint64_t);
 static inline void flush_tlb(void)
 {
        unsigned long   cr3_temp;
@@ -266,7 +275,7 @@ static inline void invlpg(unsigned long addr)
        __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
 
 #define rdtsc(lo,hi) \
-       __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi))
+       __asm__ volatile("rdtsc; lfence" : "=a" (lo), "=d" (hi))
 
 #define write_tsc(lo,hi) wrmsr(0x10, lo, hi)
 
@@ -288,7 +297,7 @@ static inline void wrmsr64(uint32_t msr, uint64_t val)
 static inline uint64_t rdtsc64(void)
 {
        uint64_t ret;
-       __asm__ volatile("rdtsc" : "=A" (ret));
+       __asm__ volatile("rdtsc; lfence" : "=A" (ret));
        return ret;
 }
 
@@ -313,6 +322,12 @@ __END_DECLS
 #define MSR_IA32_APIC_BASE_ENABLE      (1<<11)
 #define MSR_IA32_APIC_BASE_BASE                (0xfffff<<12)
 
+#define MSR_IA32_FEATURE_CONTROL       0x3a
+#define MSR_IA32_FEATCTL_LOCK          (1<<0)
+#define MSR_IA32_FEATCTL_VMXON_SMX     (1<<1)
+#define MSR_IA32_FEATCTL_VMXON         (1<<2)
+#define MSR_IA32_FEATCTL_CSTATE_SMI    (1<<16)
+
 #define MSR_IA32_UCODE_WRITE           0x79
 #define MSR_IA32_UCODE_REV             0x8b
 
@@ -368,12 +383,23 @@ __END_DECLS
 #define MSR_IA32_MTRR_FIX4K_F0000      0x26e
 #define MSR_IA32_MTRR_FIX4K_F8000      0x26f
 
+#define MSR_IA32_VMX_BASE              0x480
+#define MSR_IA32_VMX_BASIC             MSR_IA32_VMX_BASE
+#define MSR_IA32_VMXPINBASED_CTLS              MSR_IA32_VMX_BASE+1
+#define MSR_IA32_PROCBASED_CTLS                MSR_IA32_VMX_BASE+2
+#define MSR_IA32_VMX_EXIT_CTLS         MSR_IA32_VMX_BASE+3
+#define MSR_IA32_VMX_ENTRY_CTLS                MSR_IA32_VMX_BASE+4
+#define MSR_IA32_VMX_MISC              MSR_IA32_VMX_BASE+5
+#define MSR_IA32_VMX_CR0_FIXED0                MSR_IA32_VMX_BASE+6
+#define MSR_IA32_VMX_CR0_FIXED1                MSR_IA32_VMX_BASE+7
+#define MSR_IA32_VMX_CR4_FIXED0                MSR_IA32_VMX_BASE+8
+#define MSR_IA32_VMX_CR4_FIXED1                MSR_IA32_VMX_BASE+9
 
 #define        MSR_IA32_EFER           0xC0000080
-#define        MSR_IA32_EFER_SCE               0x00000001
-#define        MSR_IA32_EFER_LME               0x00000100
-#define        MSR_IA32_EFER_LMA               0x00000400
-#define        MSR_IA32_EFER_NXE               0x00000800
+#define        MSR_IA32_EFER_SCE       0x00000001
+#define        MSR_IA32_EFER_LME       0x00000100
+#define        MSR_IA32_EFER_LMA       0x00000400
+#define        MSR_IA32_EFER_NXE       0x00000800
 
 #define        MSR_IA32_STAR           0xC0000081
 #define        MSR_IA32_LSTAR          0xC0000082
@@ -384,4 +410,6 @@ __END_DECLS
 #define MSR_IA32_GS_BASE       0xC0000101
 #define MSR_IA32_KERNEL_GS_BASE        0xC0000102
 
+#define MSR_IA32_BIOS_SIGN_ID  0x08B
+
 #endif /* _I386_PROC_REG_H_ */