xnu-3247.1.106.tar.gz

[apple/xnu.git] / osfmk / i386 / cpuid.h

diff --git a/osfmk/i386/cpuid.h b/osfmk/i386/cpuid.h
index 32b07e12ab4a6440a42720de7ee774ec3fb83ce8..adb8c4a62742a6af30affcc54d3a4d06a8de70d3 100644 (file)
--- a/osfmk/i386/cpuid.h
+++ b/osfmk/i386/cpuid.h
@@ -44,6 +44,9 @@
 #define        CPUID_VID_INTEL         "GenuineIntel"
 #define        CPUID_VID_AMD           "AuthenticAMD"
 
 #define        CPUID_VID_INTEL         "GenuineIntel"
 #define        CPUID_VID_AMD           "AuthenticAMD"
 

+#define CPUID_VMM_ID_VMWARE            "VMwareVMware"
+#define CPUID_VMM_ID_PARALLELS "Parallels\0\0\0"
+

 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
 
 #define _Bit(n)                        (1ULL << n)
 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
 
 #define _Bit(n)                        (1ULL << n)


@@ -53,56 +56,86 @@
  * The CPUID_FEATURE_XXX values define 64-bit values
  * returned in %ecx:%edx to a CPUID request with %eax of 1: 
  */
  * The CPUID_FEATURE_XXX values define 64-bit values
  * returned in %ecx:%edx to a CPUID request with %eax of 1: 
  */

-#define        CPUID_FEATURE_FPU     _Bit(0)   /* Floating point unit on-chip */
-#define        CPUID_FEATURE_VME     _Bit(1)   /* Virtual Mode Extension */
-#define        CPUID_FEATURE_DE      _Bit(2)   /* Debugging Extension */
-#define        CPUID_FEATURE_PSE     _Bit(3)   /* Page Size Extension */
-#define        CPUID_FEATURE_TSC     _Bit(4)   /* Time Stamp Counter */
-#define        CPUID_FEATURE_MSR     _Bit(5)   /* Model Specific Registers */
-#define CPUID_FEATURE_PAE     _Bit(6)  /* Physical Address Extension */
-#define        CPUID_FEATURE_MCE     _Bit(7)   /* Machine Check Exception */
-#define        CPUID_FEATURE_CX8     _Bit(8)   /* CMPXCHG8B */
-#define        CPUID_FEATURE_APIC    _Bit(9)   /* On-chip APIC */
-#define CPUID_FEATURE_SEP     _Bit(11) /* Fast System Call */
-#define        CPUID_FEATURE_MTRR    _Bit(12)  /* Memory Type Range Register */
-#define        CPUID_FEATURE_PGE     _Bit(13)  /* Page Global Enable */
-#define        CPUID_FEATURE_MCA     _Bit(14)  /* Machine Check Architecture */
-#define        CPUID_FEATURE_CMOV    _Bit(15)  /* Conditional Move Instruction */
-#define CPUID_FEATURE_PAT     _Bit(16) /* Page Attribute Table */
-#define CPUID_FEATURE_PSE36   _Bit(17) /* 36-bit Page Size Extension */
-#define CPUID_FEATURE_PSN     _Bit(18) /* Processor Serial Number */
-#define CPUID_FEATURE_CLFSH   _Bit(19) /* CLFLUSH Instruction supported */
-#define CPUID_FEATURE_DS      _Bit(21) /* Debug Store */
-#define CPUID_FEATURE_ACPI    _Bit(22) /* Thermal monitor and Clock Ctrl */
-#define CPUID_FEATURE_MMX     _Bit(23) /* MMX supported */
-#define CPUID_FEATURE_FXSR    _Bit(24) /* Fast floating pt save/restore */
-#define CPUID_FEATURE_SSE     _Bit(25) /* Streaming SIMD extensions */
-#define CPUID_FEATURE_SSE2    _Bit(26) /* Streaming SIMD extensions 2 */
-#define CPUID_FEATURE_SS      _Bit(27) /* Self-Snoop */
-#define CPUID_FEATURE_HTT     _Bit(28) /* Hyper-Threading Technology */
-#define CPUID_FEATURE_TM      _Bit(29) /* Thermal Monitor (TM1) */
-#define CPUID_FEATURE_PBE     _Bit(31) /* Pend Break Enable */
-
-#define CPUID_FEATURE_SSE3    _HBit(0) /* Streaming SIMD extensions 3 */
-
-#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
-#define CPUID_FEATURE_DSCPL   _HBit(4) /* Debug Store CPL */
-#define CPUID_FEATURE_VMX     _HBit(5) /* VMX */
-#define CPUID_FEATURE_SMX     _HBit(6) /* SMX */
-#define CPUID_FEATURE_EST     _HBit(7) /* Enhanced SpeedsTep (GV3) */
-#define CPUID_FEATURE_TM2     _HBit(8) /* Thermal Monitor 2 */
-#define CPUID_FEATURE_SSSE3   _HBit(9) /* Supplemental SSE3 instructions */
-#define CPUID_FEATURE_CID     _HBit(10)        /* L1 Context ID */
-#define CPUID_FEATURE_CX16    _HBit(13)        /* CmpXchg16b instruction */
-#define CPUID_FEATURE_xTPR    _HBit(14)        /* Send Task PRiority msgs */
-#define CPUID_FEATURE_PDCM    _HBit(15)        /* Perf/Debug Capability MSR */
-
-#define CPUID_FEATURE_DCA     _HBit(18)        /* Direct Cache Access */
-#define CPUID_FEATURE_SSE4_1  _HBit(19)        /* Streaming SIMD extensions 4.1 */
-#define CPUID_FEATURE_SSE4_2  _HBit(20)        /* Streaming SIMD extensions 4.2 */
-#define CPUID_FEATURE_xAPIC   _HBit(21)        /* Extended APIC Mode */
-#define CPUID_FEATURE_POPCNT  _HBit(23)        /* POPCNT instruction */
-#define CPUID_FEATURE_VMM     _HBit(31)        /* VMM (Hypervisor) present */
+#define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
+#define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
+#define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
+#define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
+#define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
+#define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
+#define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
+#define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
+#define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
+#define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
+#define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
+#define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
+#define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
+#define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
+#define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
+#define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
+#define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
+#define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
+#define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
+#define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
+#define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
+#define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
+#define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
+#define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
+#define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
+#define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
+#define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
+#define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
+#define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
+ 
+#define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
+#define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
+#define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
+#define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
+#define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
+#define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
+#define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
+#define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
+#define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
+#define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
+#define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
+#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_FMA       _HBit(12) /* Fused-Multiply-Add support */
+#define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
+#define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
+#define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */
+
+#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
+#define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
+#define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
+#define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
+#define CPUID_FEATURE_x2APIC    _HBit(21) /* Extended APIC Mode */
+#define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
+#define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
+#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
+#define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
+#define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
+#define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
+#define CPUID_FEATURE_AVX1_0   _HBit(28) /* AVX 1.0 instructions */
+#define CPUID_FEATURE_F16C     _HBit(29) /* Float16 convert instructions */
+#define CPUID_FEATURE_RDRAND   _HBit(30) /* RDRAND instruction */
+#define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
+
+/*
+ * Leaf 7, subleaf 0 additional features.
+ * Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
+ */
+#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)   /* FS/GS base read/write */
+#define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)   /* TSC thread offset */
+#define CPUID_LEAF7_FEATURE_BMI1     _Bit(3)   /* Bit Manipulation Instrs, set 1 */
+#define CPUID_LEAF7_FEATURE_HLE      _Bit(4)   /* Hardware Lock Elision*/
+#define CPUID_LEAF7_FEATURE_AVX2     _Bit(5)   /* AVX2 Instructions */
+#define CPUID_LEAF7_FEATURE_SMEP     _Bit(7)   /* Supervisor Mode Execute Protect */
+#define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)   /* Bit Manipulation Instrs, set 2 */
+#define CPUID_LEAF7_FEATURE_ERMS     _Bit(9)   /* Enhanced Rep Movsb/Stosb */
+#define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)  /* INVPCID intruction, TDB */
+#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)  /* RTM */
+#define CPUID_LEAF7_FEATURE_RDSEED   _Bit(18)  /* RDSEED Instruction */
+#define CPUID_LEAF7_FEATURE_ADX      _Bit(19)  /* ADX Instructions */
+#define CPUID_LEAF7_FEATURE_SMAP     _Bit(20)  /* Supervisor Mode Access Protect */

 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values


@@ -111,10 +144,13 @@
 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)    /* SYSCALL/sysret */
 #define CPUID_EXTFEATURE_XD       _Bit(20)     /* eXecute Disable */
 
 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)    /* SYSCALL/sysret */
 #define CPUID_EXTFEATURE_XD       _Bit(20)     /* eXecute Disable */
 

+#define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)    /* 1GB pages */

 #define CPUID_EXTFEATURE_RDTSCP           _Bit(27)     /* RDTSCP */
 #define CPUID_EXTFEATURE_EM64T    _Bit(29)     /* Extended Mem 64 Technology */
 
 #define CPUID_EXTFEATURE_RDTSCP           _Bit(27)     /* RDTSCP */
 #define CPUID_EXTFEATURE_EM64T    _Bit(29)     /* Extended Mem 64 Technology */
 

-#define CPUID_EXTFEATURE_LAHF     _HBit(0)     /* LAHF/SAHF instructions */
+#define CPUID_EXTFEATURE_LAHF     _HBit(0)     /* LAFH/SAHF instructions */
+#define CPUID_EXTFEATURE_LZCNT     _HBit(5)    /* LZCNT instruction */
+#define CPUID_EXTFEATURE_PREFETCHW _HBit(8)    /* PREFETCHW instruction */

 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values


@@ -122,18 +158,57 @@
  */
 #define CPUID_EXTFEATURE_TSCI      _Bit(8)     /* TSC Invariant */
 
  */
 #define CPUID_EXTFEATURE_TSCI      _Bit(8)     /* TSC Invariant */
 

+/*
+ * CPUID_X86_64_H_FEATURE_SUBSET and CPUID_X86_64_H_LEAF7_FEATURE_SUBSET
+ * indicate the bitmask of features that must be present before the system
+ * is eligible to run the "x86_64h" "Haswell feature subset" slice.
+ */
+#define CPUID_X86_64_H_FEATURE_SUBSET ( CPUID_FEATURE_FMA    | \
+                                        CPUID_FEATURE_SSE4_2 | \
+                                        CPUID_FEATURE_MOVBE  | \
+                                        CPUID_FEATURE_POPCNT | \
+                                        CPUID_FEATURE_AVX1_0   \
+                                      )
+
+#define CPUID_X86_64_H_EXTFEATURE_SUBSET ( CPUID_EXTFEATURE_LZCNT \
+                                         )
+
+#define CPUID_X86_64_H_LEAF7_FEATURE_SUBSET ( CPUID_LEAF7_FEATURE_BMI1 | \
+                                              CPUID_LEAF7_FEATURE_AVX2 | \
+                                              CPUID_LEAF7_FEATURE_BMI2   \
+                                            )
+

 #define        CPUID_CACHE_SIZE        16      /* Number of descriptor values */
 
 #define CPUID_MWAIT_EXTENSION  _Bit(0) /* enumeration of WMAIT extensions */
 #define CPUID_MWAIT_BREAK      _Bit(1) /* interrupts are break events     */
 
 #define        CPUID_CACHE_SIZE        16      /* Number of descriptor values */
 
 #define CPUID_MWAIT_EXTENSION  _Bit(0) /* enumeration of WMAIT extensions */
 #define CPUID_MWAIT_BREAK      _Bit(1) /* interrupts are break events     */
 

-#define CPUID_MODEL_YONAH      14
-#define CPUID_MODEL_MEROM      15
-#define CPUID_MODEL_PENRYN     23
-#define CPUID_MODEL_NEHALEM    26
-#define CPUID_MODEL_FIELDS     30      /* Lynnfield, Clarksfield, Jasper */
-#define CPUID_MODEL_DALES      31      /* Havendale, Auburndale */
-#define CPUID_MODEL_NEHALEM_EX 46
+#define CPUID_MODEL_YONAH              0x0E
+#define CPUID_MODEL_MEROM              0x0F
+#define CPUID_MODEL_PENRYN             0x17
+#define CPUID_MODEL_NEHALEM            0x1A
+#define CPUID_MODEL_FIELDS             0x1E    /* Lynnfield, Clarksfield */
+#define CPUID_MODEL_DALES              0x1F    /* Havendale, Auburndale */
+#define CPUID_MODEL_NEHALEM_EX         0x2E
+#define CPUID_MODEL_DALES_32NM         0x25    /* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE           0x2C    /* Gulftown, Westmere-EP/-WS */
+#define CPUID_MODEL_WESTMERE_EX                0x2F
+#define CPUID_MODEL_SANDYBRIDGE                0x2A
+#define CPUID_MODEL_JAKETOWN           0x2D
+#define CPUID_MODEL_IVYBRIDGE          0x3A
+#define CPUID_MODEL_IVYBRIDGE_EP       0x3E
+#define CPUID_MODEL_CRYSTALWELL                0x46
+#define CPUID_MODEL_HASWELL            0x3C
+#define CPUID_MODEL_HASWELL_EP         0x3F
+#define CPUID_MODEL_HASWELL_ULT                0x45
+#define CPUID_MODEL_BROADWELL          0x3D
+#define CPUID_MODEL_BROADWELL_ULX      0x3D
+#define CPUID_MODEL_BROADWELL_ULT      0x3D
+#define CPUID_MODEL_BRYSTALWELL                0x47
+
+#define CPUID_VMM_FAMILY_UNKNOWN       0x0
+#define CPUID_VMM_FAMILY_VMWARE                0x1
+#define CPUID_VMM_FAMILY_PARALLELS     0x2

 
 #ifndef ASSEMBLER
 #include <stdint.h>
 
 #ifndef ASSEMBLER
 #include <stdint.h>


@@ -146,7 +221,7 @@ typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
 static inline void
 cpuid(uint32_t *data)
 {
 static inline void
 cpuid(uint32_t *data)
 {

-       asm("cpuid"
+       __asm__ volatile ("cpuid"

                : "=a" (data[eax]),
                  "=b" (data[ebx]),
                  "=c" (data[ecx]),
                : "=a" (data[eax]),
                  "=b" (data[ebx]),
                  "=c" (data[ecx]),


@@ -156,15 +231,19 @@ cpuid(uint32_t *data)
                  "c"  (data[ecx]),
                  "d"  (data[edx]));
 }
                  "c"  (data[ecx]),
                  "d"  (data[edx]));
 }

+

 static inline void
 do_cpuid(uint32_t selector, uint32_t *data)
 {
 static inline void
 do_cpuid(uint32_t selector, uint32_t *data)
 {

-       asm("cpuid"
+       __asm__ volatile ("cpuid"

                : "=a" (data[0]),
                  "=b" (data[1]),
                  "=c" (data[2]),
                  "=d" (data[3])
                : "=a" (data[0]),
                  "=b" (data[1]),
                  "=c" (data[2]),
                  "=d" (data[3])

-               : "a"(selector));
+               : "a"(selector),
+                 "b" (0),
+                 "c" (0),
+                 "d" (0));

 }
 
 /*
 }
 
 /*


@@ -203,10 +282,22 @@ typedef struct {
        boolean_t       sensor;
        boolean_t       dynamic_acceleration;
        boolean_t       invariant_APIC_timer;
        boolean_t       sensor;
        boolean_t       dynamic_acceleration;
        boolean_t       invariant_APIC_timer;

+       boolean_t       core_power_limits;
+       boolean_t       fine_grain_clock_mod;
+       boolean_t       package_thermal_intr;

        uint32_t        thresholds;
        boolean_t       ACNT_MCNT;
        uint32_t        thresholds;
        boolean_t       ACNT_MCNT;

+       boolean_t       hardware_feedback;
+       boolean_t       energy_policy;

 } cpuid_thermal_leaf_t;
 
 } cpuid_thermal_leaf_t;
 

+
+/* XSAVE Feature Leaf: */
+typedef struct {
+       uint32_t        extended_state[4];      /* eax .. edx */
+} cpuid_xsave_leaf_t;
+
+

 /* Architectural Performance Monitoring Leaf: */
 typedef struct {
        uint8_t         version;
 /* Architectural Performance Monitoring Leaf: */
 typedef struct {
        uint8_t         version;


@@ -234,6 +325,7 @@ typedef struct {
        uint64_t        cpuid_extfeatures;
        uint32_t        cpuid_signature;
        uint8_t         cpuid_brand; 
        uint64_t        cpuid_extfeatures;
        uint32_t        cpuid_signature;
        uint8_t         cpuid_brand; 

+       uint8_t         cpuid_processor_flag;

        
        uint32_t        cache_size[LCACHE_MAX];
        uint32_t        cache_linesize;
        
        uint32_t        cache_size[LCACHE_MAX];
        uint32_t        cache_linesize;


@@ -256,6 +348,7 @@ typedef struct {
 #define cpuid_mwait_sub_Cstates                cpuid_mwait_leaf.sub_Cstates
        cpuid_thermal_leaf_t    cpuid_thermal_leaf;
        cpuid_arch_perf_leaf_t  cpuid_arch_perf_leaf;
 #define cpuid_mwait_sub_Cstates                cpuid_mwait_leaf.sub_Cstates
        cpuid_thermal_leaf_t    cpuid_thermal_leaf;
        cpuid_arch_perf_leaf_t  cpuid_arch_perf_leaf;

+       uint32_t        unused[4];                      /* cpuid_xsave_leaf */

 
        /* Cache details: */
        uint32_t        cpuid_cache_linesize;
 
        /* Cache details: */
        uint32_t        cpuid_cache_linesize;


@@ -288,9 +381,20 @@ typedef struct {
        cpuid_mwait_leaf_t      *cpuid_mwait_leafp;     
        cpuid_thermal_leaf_t    *cpuid_thermal_leafp;
        cpuid_arch_perf_leaf_t  *cpuid_arch_perf_leafp;
        cpuid_mwait_leaf_t      *cpuid_mwait_leafp;     
        cpuid_thermal_leaf_t    *cpuid_thermal_leafp;
        cpuid_arch_perf_leaf_t  *cpuid_arch_perf_leafp;

-
+       cpuid_xsave_leaf_t      *cpuid_xsave_leafp;
+       uint64_t                cpuid_leaf7_features;
+       cpuid_xsave_leaf_t      cpuid_xsave_leaf[2];

 } i386_cpu_info_t;
 
 } i386_cpu_info_t;
 

+#ifdef MACH_KERNEL_PRIVATE
+typedef struct {
+       char            cpuid_vmm_vendor[16];
+       uint32_t        cpuid_vmm_family;
+       uint32_t        cpuid_vmm_bus_frequency;
+       uint32_t        cpuid_vmm_tsc_frequency;
+} i386_vmm_info_t;
+#endif
+

 #ifdef __cplusplus
 extern "C" {
 #endif
 #ifdef __cplusplus
 extern "C" {
 #endif


@@ -305,17 +409,23 @@ extern void               cpuid_feature_display(const char *);
 extern void            cpuid_extfeature_display(const char *);
 extern char *          cpuid_get_feature_names(uint64_t, char *, unsigned);
 extern char *          cpuid_get_extfeature_names(uint64_t, char *, unsigned);
 extern void            cpuid_extfeature_display(const char *);
 extern char *          cpuid_get_feature_names(uint64_t, char *, unsigned);
 extern char *          cpuid_get_extfeature_names(uint64_t, char *, unsigned);

+extern char *          cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);

 
 extern uint64_t                cpuid_features(void);
 extern uint64_t                cpuid_extfeatures(void);
 
 extern uint64_t                cpuid_features(void);
 extern uint64_t                cpuid_extfeatures(void);

+extern uint64_t                cpuid_leaf7_features(void);

 extern uint32_t                cpuid_family(void);
 extern uint32_t                cpuid_cpufamily(void);
        
 extern uint32_t                cpuid_family(void);
 extern uint32_t                cpuid_cpufamily(void);
        

-extern void            cpuid_get_info(i386_cpu_info_t *info_p);

 extern i386_cpu_info_t *cpuid_info(void);
 extern i386_cpu_info_t *cpuid_info(void);

-

 extern void            cpuid_set_info(void);
 
 extern void            cpuid_set_info(void);
 

+#ifdef MACH_KERNEL_PRIVATE
+extern boolean_t       cpuid_vmm_present(void);
+extern i386_vmm_info_t *cpuid_vmm_info(void);
+extern uint32_t                cpuid_vmm_family(void);
+#endif
+

 #ifdef __cplusplus
 }
 #endif
 #ifdef __cplusplus
 }
 #endif