xnu-4903.270.47.tar.gz

[apple/xnu.git] / osfmk / arm / machine_cpuid.c

diff --git a/osfmk/arm/machine_cpuid.c b/osfmk/arm/machine_cpuid.c
index ac54a0be51896b4a024f904322b0d0edad1fae24..b79253632d0393a6d0b0740a49b26cc7be9a8d3e 100644 (file)
--- a/osfmk/arm/machine_cpuid.c
+++ b/osfmk/arm/machine_cpuid.c
@@ -38,10 +38,10 @@ uint32_t
 machine_read_midr(void)
 {
 #if __arm__
-       uint32_t midr = __builtin_arm_mrc(15,0,0,0,0);
+       uint32_t midr = __builtin_arm_mrc(15, 0, 0, 0, 0);
 #else
        uint64_t midr;
-       __asm__ volatile("mrs   %0, MIDR_EL1" : "=r" (midr));
+       __asm__ volatile ("mrs  %0, MIDR_EL1"  : "=r" (midr));
 #endif
        return (uint32_t)midr;
 }
@@ -50,10 +50,10 @@ uint32_t
 machine_read_clidr(void)
 {
 #if __arm__
-       uint32_t clidr = __builtin_arm_mrc(15,1,0,0,1);
+       uint32_t clidr = __builtin_arm_mrc(15, 1, 0, 0, 1);
 #else
        uint64_t clidr;
-       __asm__ volatile("mrs   %0, CLIDR_EL1" : "=r" (clidr));
+       __asm__ volatile ("mrs  %0, CLIDR_EL1"  : "=r" (clidr));
 #endif
        return (uint32_t)clidr;
 }
@@ -62,10 +62,10 @@ uint32_t
 machine_read_ccsidr(void)
 {
 #if __arm__
-       uint32_t ccsidr = __builtin_arm_mrc(15,1,0,0,0);
+       uint32_t ccsidr = __builtin_arm_mrc(15, 1, 0, 0, 0);
 #else
        uint64_t ccsidr;
-       __asm__ volatile("mrs   %0, CCSIDR_EL1" : "=r" (ccsidr));
+       __asm__ volatile ("mrs  %0, CCSIDR_EL1"  : "=r" (ccsidr));
 #endif
        return (uint32_t)ccsidr;
 }
@@ -75,7 +75,7 @@ arm_isa_feat1_reg
 machine_read_isa_feat1(void)
 {
        arm_isa_feat1_reg isa;
-       isa.value = __builtin_arm_mrc(15,0,0,2,1);
+       isa.value = __builtin_arm_mrc(15, 0, 0, 2, 1);
        return isa;
 }
 #endif // __arm__
@@ -85,10 +85,10 @@ machine_write_csselr(csselr_cache_level level, csselr_cache_type type)
 {
 #if __arm__
        uint32_t csselr = (level | type);
-       __builtin_arm_mcr(15,2,csselr,0,0,0);
+       __builtin_arm_mcr(15, 2, csselr, 0, 0, 0);
 #else
        uint64_t csselr = (level | type);
-       __asm__ volatile("msr   CSSELR_EL1, %0" : : "r" (csselr));
+       __asm__ volatile ("msr  CSSELR_EL1, %0"  : : "r" (csselr));
 #endif
        __builtin_arm_isb(ISB_SY);
 }
@@ -101,23 +101,23 @@ machine_do_debugid(void)
        arm_debug_dbgdidr dbgdidr;
 
        /* read CPUID ID_DFR0 */
-       id_dfr0.value = __builtin_arm_mrc(15,0,0,1,2);
+       id_dfr0.value = __builtin_arm_mrc(15, 0, 0, 1, 2);
        /* read DBGDIDR */
-       dbgdidr.value = __builtin_arm_mrc(14,0,0,0,0);
+       dbgdidr.value = __builtin_arm_mrc(14, 0, 0, 0, 0);
 
        cpuid_debug_info.coprocessor_core_debug = id_dfr0.debug_feature.coprocessor_core_debug != 0;
        cpuid_debug_info.memory_mapped_core_debug = (id_dfr0.debug_feature.memory_mapped_core_debug != 0)
            && (getCpuDatap()->cpu_debug_interface_map != 0);
 
        if (cpuid_debug_info.coprocessor_core_debug || cpuid_debug_info.memory_mapped_core_debug) {
-           cpuid_debug_info.num_watchpoint_pairs = dbgdidr.debug_id.wrps + 1;
-           cpuid_debug_info.num_breakpoint_pairs = dbgdidr.debug_id.brps + 1;
+               cpuid_debug_info.num_watchpoint_pairs = dbgdidr.debug_id.wrps + 1;
+               cpuid_debug_info.num_breakpoint_pairs = dbgdidr.debug_id.brps + 1;
        }
 #else
        arm_cpuid_id_aa64dfr0_el1 id_dfr0;
 
        /* read ID_AA64DFR0_EL1 */
-       __asm__ volatile("mrs %0, ID_AA64DFR0_EL1" : "=r"(id_dfr0.value));
+       __asm__ volatile ("mrs %0, ID_AA64DFR0_EL1" : "=r"(id_dfr0.value));
 
        if (id_dfr0.debug_feature.debug_arch_version) {
                cpuid_debug_info.num_watchpoint_pairs = id_dfr0.debug_feature.wrps + 1;
@@ -136,11 +136,11 @@ void
 machine_do_mvfpid()
 {
 #if __arm__
-       arm_mvfr0_info_t        arm_mvfr0_info;
-       arm_mvfr1_info_t        arm_mvfr1_info;
+       arm_mvfr0_info_t        arm_mvfr0_info;
+       arm_mvfr1_info_t        arm_mvfr1_info;
 
-       __asm__ volatile("vmrs  %0, mvfr0":"=r"(arm_mvfr0_info.value));
-       __asm__ volatile("vmrs  %0, mvfr1":"=r"(arm_mvfr1_info.value));
+       __asm__ volatile ("vmrs %0, mvfr0" :"=r"(arm_mvfr0_info.value));
+       __asm__ volatile ("vmrs %0, mvfr1" :"=r"(arm_mvfr1_info.value));
 
        cpuid_mvfp_info.neon = arm_mvfr1_info.bits.SP;
        cpuid_mvfp_info.neon_hpfp = arm_mvfr1_info.bits.HPFP;
@@ -148,7 +148,6 @@ machine_do_mvfpid()
        cpuid_mvfp_info.neon = 1;
        cpuid_mvfp_info.neon_hpfp = 1;
 #endif /* __arm__ */
-
 }
 
 arm_mvfp_info_t *
@@ -156,4 +155,3 @@ machine_arm_mvfp_info(void)
 {
        return &cpuid_mvfp_info;
 }
-