xnu-6153.121.1.tar.gz

[apple/xnu.git] / bsd / dev / i386 / dis_tables.c

diff --git a/bsd/dev/i386/dis_tables.c b/bsd/dev/i386/dis_tables.c
index bfaa4bc799f17b6d361ae87872519d51cf34900a..f167167ca0ee79d0d975ed19ce81c01ff0c3e88d 100644 (file)
--- a/bsd/dev/i386/dis_tables.c
+++ b/bsd/dev/i386/dis_tables.c
@@ -19,28 +19,31 @@
  *
  * CDDL HEADER END
  */
  *
  * CDDL HEADER END
  */

+
+/*
+ * Copyright (c) 2015, Joyent, Inc.
+ * Copyright (c) 2008 Sun Microsystems, Inc.  All rights reserved.
+ */
+

 /*
 /*

- * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
+ * Copyright (c) 2010, Intel Corporation.
+ * All rights reserved.

  */
 
 /*     Copyright (c) 1988 AT&T */
 /*       All Rights Reserved   */
 
  */
 
 /*     Copyright (c) 1988 AT&T */
 /*       All Rights Reserved   */
 

-

 /*
 /*

- * #pragma ident       "@(#)dis_tables.c       1.18    08/05/24 SMI"
+ * APPLE NOTE: There is a copy of this file in userspace in
+ * dtrace:/disassembler/dis_tables.c
+ *
+ * It needs to be in sync with this file.

  */
  */

-#if !defined(__APPLE__)
-#include       "dis_tables.h"
-#else
+

 #include <sys/dtrace.h>
 #include <sys/dtrace_glue.h>
 #include <sys/dtrace.h>
 #include <sys/dtrace_glue.h>

-

 #include <sys/dis_tables.h>
 
 #include <sys/dis_tables.h>
 

-#endif /* __APPLE__ */
-

 /* BEGIN CSTYLED */
 
 /*
 /* BEGIN CSTYLED */
 
 /*


@@ -66,9 +69,7 @@
 #ifdef DIS_TEXT
 extern char *strncpy(char *, const char *, size_t);
 extern size_t strlen(const char *);
 #ifdef DIS_TEXT
 extern char *strncpy(char *, const char *, size_t);
 extern size_t strlen(const char *);

-#if !defined(__APPLE__)

 extern int strcmp(const char *, const char *);
 extern int strcmp(const char *, const char *);

-#endif /* __APPLE__ */

 extern int strncmp(const char *, const char *, size_t);
 extern size_t strlcat(char *, const char *, size_t);
 #endif
 extern int strncmp(const char *, const char *, size_t);
 extern size_t strlcat(char *, const char *, size_t);
 #endif


@@ -92,6 +93,8 @@ typedef struct        instable {
        uint_t          it_always64:1;          /* 64 bit when in 64 bit mode */
        uint_t          it_invalid32:1;         /* invalid in IA32 */
        uint_t          it_stackop:1;           /* push/pop stack operation */
        uint_t          it_always64:1;          /* 64 bit when in 64 bit mode */
        uint_t          it_invalid32:1;         /* invalid in IA32 */
        uint_t          it_stackop:1;           /* push/pop stack operation */

+       uint_t          it_vexwoxmm:1;          /* VEX instructions that don't use XMM/YMM */
+       uint_t          it_avxsuf:1;            /* AVX suffix required */

 } instable_t;
 
 /*
 } instable_t;
 
 /*


@@ -110,16 +113,18 @@ enum {
        Mv,
        Mw,
        M,              /* register or memory */
        Mv,
        Mw,
        M,              /* register or memory */

+       MG9,            /* register or memory in group 9 (prefix optional) */

        Mb,             /* register or memory, always byte sized */
        MO,             /* memory only (no registers) */
        PREF,
        Mb,             /* register or memory, always byte sized */
        MO,             /* memory only (no registers) */
        PREF,

-       SWAPGS,
+       SWAPGS_RDTSCP,

        MONITOR_MWAIT,
        R,
        RA,
        SEG,
        MR,
        RM,
        MONITOR_MWAIT,
        R,
        RA,
        SEG,
        MR,
        RM,

+       RM_66r,         /* RM, but with a required 0x66 prefix */

        IA,
        MA,
        SD,
        IA,
        MA,
        SD,


@@ -164,6 +169,7 @@ enum {
        CRC32,          /* for crc32, with different size operands */
        XADDB,          /* for xaddb */
        MOVSXZ,         /* AMD64 mov sign extend 32 to 64 bit instruction */
        CRC32,          /* for crc32, with different size operands */
        XADDB,          /* for xaddb */
        MOVSXZ,         /* AMD64 mov sign extend 32 to 64 bit instruction */

+       MOVBE,          /* movbe instruction */

 
 /*
  * MMX/SIMD addressing modes.
 
 /*
  * MMX/SIMD addressing modes.


@@ -216,9 +222,41 @@ enum {
         XMMX2I,                /* SIMD                         xmm -> xmm, imm, imm */
         XMM2I,         /* SIMD                         xmm, imm, imm */
        XMMFENCE,       /* SIMD lfence or mfence */
         XMMX2I,                /* SIMD                         xmm -> xmm, imm, imm */
         XMM2I,         /* SIMD                         xmm, imm, imm */
        XMMFENCE,       /* SIMD lfence or mfence */

-       XMMSFNC         /* SIMD sfence (none or mem) */
+       XMMSFNC,        /* SIMD sfence (none or mem) */
+       XGETBV_XSETBV,
+       VEX_NONE,       /* VEX  no operand */
+       VEX_MO,         /* VEX  mod_rm                         -> implicit reg */
+       VEX_RMrX,       /* VEX  VEX.vvvv, mod_rm               -> mod_reg */
+       VEX_VRMrX,      /* VEX  mod_rm, VEX.vvvv               -> mod_rm */
+       VEX_RRX,        /* VEX  VEX.vvvv, mod_reg              -> mod_rm */
+       VEX_RMRX,       /* VEX  VEX.vvvv, mod_rm, imm8[7:4]    -> mod_reg */
+       VEX_MX,         /* VEX  mod_rm                         -> mod_reg */
+       VEX_MXI,        /* VEX  mod_rm, imm8                   -> mod_reg */
+       VEX_XXI,        /* VEX  mod_rm, imm8                   -> VEX.vvvv */
+       VEX_MR,         /* VEX  mod_rm                         -> mod_reg */
+       VEX_RRI,        /* VEX  mod_reg, mod_rm                -> implicit(eflags/r32) */
+       VEX_RX,         /* VEX  mod_reg                        -> mod_rm */
+       VEX_RR,         /* VEX  mod_rm                         -> mod_reg */
+       VEX_RRi,        /* VEX  mod_rm, imm8                   -> mod_reg */
+       VEX_RM,         /* VEX  mod_reg                        -> mod_rm */
+       VEX_RIM,        /* VEX  mod_reg, imm8                  -> mod_rm */
+       VEX_RRM,        /* VEX  VEX.vvvv, mod_reg              -> mod_rm */
+       VEX_RMX,        /* VEX  VEX.vvvv, mod_rm               -> mod_reg */
+       VEX_SbVM,       /* VEX  SIB, VEX.vvvv                  -> mod_rm */
+       VMx,            /* vmcall/vmlaunch/vmresume/vmxoff */
+       VMxo,           /* VMx instruction with optional prefix */
+       SVM,            /* AMD SVM instructions */
+       BLS,            /* BLSR, BLSMSK, BLSI */
+       FMA,            /* FMA instructions, all VEX_RMrX */
+       ADX             /* ADX instructions, support REX.w, mod_rm->mod_reg */

 };
 
 };
 

+/*
+ * VEX prefixes
+ */
+#define VEX_2bytes     0xC5    /* the first byte of two-byte form */
+#define VEX_3bytes     0xC4    /* the first byte of three-byte form */
+

 #define        FILL    0x90    /* Fill byte used for alignment (nop)   */
 
 /*
 #define        FILL    0x90    /* Fill byte used for alignment (nop)   */
 
 /*


@@ -248,32 +286,36 @@ enum {
  *   IND - indirect to another to another table
  *   "T" - means to Terminate indirections (this is the final opcode)
  *   "S" - means "operand length suffix required"
  *   IND - indirect to another to another table
  *   "T" - means to Terminate indirections (this is the final opcode)
  *   "S" - means "operand length suffix required"

+ *   "Sa" - means AVX2 suffix (d/q) required

  *   "NS" - means "no suffix" which is the operand length suffix of the opcode
  *   "Z" - means instruction size arg required
  *   "u" - means the opcode is invalid in IA32 but valid in amd64
  *   "x" - means the opcode is invalid in amd64, but not IA32
  *   "y" - means the operand size is always 64 bits in 64 bit mode
  *   "p" - means push/pop stack operation
  *   "NS" - means "no suffix" which is the operand length suffix of the opcode
  *   "Z" - means instruction size arg required
  *   "u" - means the opcode is invalid in IA32 but valid in amd64
  *   "x" - means the opcode is invalid in amd64, but not IA32
  *   "y" - means the operand size is always 64 bits in 64 bit mode
  *   "p" - means push/pop stack operation

+ *   "vr" - means VEX instruction that operates on normal registers, not fpu

  */
 
 #if defined(DIS_TEXT) && defined(DIS_MEM)
  */
 
 #if defined(DIS_TEXT) && defined(DIS_MEM)

-#define        IND(table)              {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
-#define        INDx(table)             {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
-#define        TNS(name, amode)        {TERM, amode, name, 0, 0, 0, 0, 0, 0}
-#define        TNSu(name, amode)       {TERM, amode, name, 0, 0, 0, 0, 1, 0}
-#define        TNSx(name, amode)       {TERM, amode, name, 0, 0, 1, 0, 0, 0}
-#define        TNSy(name, amode)       {TERM, amode, name, 0, 0, 0, 1, 0, 0}
-#define        TNSyp(name, amode)      {TERM, amode, name, 0, 0, 0, 1, 0, 1}
-#define        TNSZ(name, amode, sz)   {TERM, amode, name, 0, sz, 0, 0, 0, 0}
-#define        TNSZy(name, amode, sz)  {TERM, amode, name, 0, sz, 0, 1, 0, 0}
-#define        TS(name, amode)         {TERM, amode, name, 1, 0, 0, 0, 0, 0}
-#define        TSx(name, amode)        {TERM, amode, name, 1, 0, 1, 0, 0, 0}
-#define        TSy(name, amode)        {TERM, amode, name, 1, 0, 0, 1, 0, 0}
-#define        TSp(name, amode)        {TERM, amode, name, 1, 0, 0, 0, 0, 1}
-#define        TSZ(name, amode, sz)    {TERM, amode, name, 1, sz, 0, 0, 0, 0}
-#define        TSZx(name, amode, sz)   {TERM, amode, name, 1, sz, 1, 0, 0, 0}
-#define        TSZy(name, amode, sz)   {TERM, amode, name, 1, sz, 0, 1, 0, 0}
-#define        INVALID                 {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
+#define        IND(table)              {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0, 0, 0}
+#define        INDx(table)             {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0, 0, 0}
+#define        TNS(name, amode)        {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, 0}
+#define        TNSu(name, amode)       {TERM, amode, name, 0, 0, 0, 0, 1, 0, 0, 0}
+#define        TNSx(name, amode)       {TERM, amode, name, 0, 0, 1, 0, 0, 0, 0, 0}
+#define        TNSy(name, amode)       {TERM, amode, name, 0, 0, 0, 1, 0, 0, 0, 0}
+#define        TNSyp(name, amode)      {TERM, amode, name, 0, 0, 0, 1, 0, 1, 0, 0}
+#define        TNSZ(name, amode, sz)   {TERM, amode, name, 0, sz, 0, 0, 0, 0, 0, 0}
+#define        TNSZy(name, amode, sz)  {TERM, amode, name, 0, sz, 0, 1, 0, 0, 0, 0}
+#define        TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1, 0}
+#define        TS(name, amode)         {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0}
+#define        TSx(name, amode)        {TERM, amode, name, 1, 0, 1, 0, 0, 0, 0, 0}
+#define        TSy(name, amode)        {TERM, amode, name, 1, 0, 0, 1, 0, 0, 0, 0}
+#define        TSp(name, amode)        {TERM, amode, name, 1, 0, 0, 0, 0, 1, 0, 0}
+#define        TSZ(name, amode, sz)    {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 0}
+#define        TSaZ(name, amode, sz)   {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
+#define        TSZx(name, amode, sz)   {TERM, amode, name, 1, sz, 1, 0, 0, 0, 0, 0}
+#define        TSZy(name, amode, sz)   {TERM, amode, name, 1, sz, 0, 1, 0, 0, 0, 0}
+#define        INVALID                 {TERM, UNKNOWN, "", 0, 0, 0, 0, 0, 0, 0, 0}

 #elif defined(DIS_TEXT)
 #define        IND(table)              {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
 #define        INDx(table)             {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
 #elif defined(DIS_TEXT)
 #define        IND(table)              {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
 #define        INDx(table)             {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}


@@ -284,50 +326,56 @@ enum {
 #define        TNSyp(name, amode)      {TERM, amode, name, 0, 0, 1, 0, 1}
 #define        TNSZ(name, amode, sz)   {TERM, amode, name, 0, 0, 0, 0, 0}
 #define        TNSZy(name, amode, sz)  {TERM, amode, name, 0, 0, 1, 0, 0}
 #define        TNSyp(name, amode)      {TERM, amode, name, 0, 0, 1, 0, 1}
 #define        TNSZ(name, amode, sz)   {TERM, amode, name, 0, 0, 0, 0, 0}
 #define        TNSZy(name, amode, sz)  {TERM, amode, name, 0, 0, 1, 0, 0}

+#define        TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}

 #define        TS(name, amode)         {TERM, amode, name, 1, 0, 0, 0, 0}
 #define        TSx(name, amode)        {TERM, amode, name, 1, 1, 0, 0, 0}
 #define        TSy(name, amode)        {TERM, amode, name, 1, 0, 1, 0, 0}
 #define        TSp(name, amode)        {TERM, amode, name, 1, 0, 0, 0, 1}
 #define        TSZ(name, amode, sz)    {TERM, amode, name, 1, 0, 0, 0, 0}
 #define        TS(name, amode)         {TERM, amode, name, 1, 0, 0, 0, 0}
 #define        TSx(name, amode)        {TERM, amode, name, 1, 1, 0, 0, 0}
 #define        TSy(name, amode)        {TERM, amode, name, 1, 0, 1, 0, 0}
 #define        TSp(name, amode)        {TERM, amode, name, 1, 0, 0, 0, 1}
 #define        TSZ(name, amode, sz)    {TERM, amode, name, 1, 0, 0, 0, 0}

+#define        TSaZ(name, amode, sz)   {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}

 #define        TSZx(name, amode, sz)   {TERM, amode, name, 1, 1, 0, 0, 0}
 #define        TSZy(name, amode, sz)   {TERM, amode, name, 1, 0, 1, 0, 0}
 #define        INVALID                 {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
 #elif defined(DIS_MEM)
 #define        IND(table)              {(instable_t *)table, 0, 0, 0, 0, 0, 0}
 #define        INDx(table)             {(instable_t *)table, 0, 0, 1, 0, 0, 0}
 #define        TSZx(name, amode, sz)   {TERM, amode, name, 1, 1, 0, 0, 0}
 #define        TSZy(name, amode, sz)   {TERM, amode, name, 1, 0, 1, 0, 0}
 #define        INVALID                 {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
 #elif defined(DIS_MEM)
 #define        IND(table)              {(instable_t *)table, 0, 0, 0, 0, 0, 0}
 #define        INDx(table)             {(instable_t *)table, 0, 0, 1, 0, 0, 0}

-#define        TNS(name, amode)        {TERM, amode,  0, 0, 0, 0, 0}
-#define        TNSu(name, amode)       {TERM, amode,  0, 0, 0, 1, 0}
-#define        TNSy(name, amode)       {TERM, amode,  0, 0, 1, 0, 0}
-#define        TNSyp(name, amode)      {TERM, amode,  0, 0, 1, 0, 1}
-#define        TNSx(name, amode)       {TERM, amode,  0, 1, 0, 0, 0}
-#define        TNSZ(name, amode, sz)   {TERM, amode, sz, 0, 0, 0, 0}
-#define        TNSZy(name, amode, sz)  {TERM, amode, sz, 0, 1, 0, 0}
-#define        TS(name, amode)         {TERM, amode,  0, 0, 0, 0, 0}
-#define        TSx(name, amode)        {TERM, amode,  0, 1, 0, 0, 0}
-#define        TSy(name, amode)        {TERM, amode,  0, 0, 1, 0, 0}
-#define        TSp(name, amode)        {TERM, amode,  0, 0, 0, 0, 1}
-#define        TSZ(name, amode, sz)    {TERM, amode, sz, 0, 0, 0, 0}
-#define        TSZx(name, amode, sz)   {TERM, amode, sz, 1, 0, 0, 0}
-#define        TSZy(name, amode, sz)   {TERM, amode, sz, 0, 1, 0, 0}
-#define        INVALID                 {TERM, UNKNOWN, 0, 0, 0, 0, 0}
+#define        TNS(name, amode)        {TERM, amode,  0, 0, 0, 0, 0, 0, 0}
+#define        TNSu(name, amode)       {TERM, amode,  0, 0, 0, 1, 0, 0, 0}
+#define        TNSy(name, amode)       {TERM, amode,  0, 0, 1, 0, 0, 0, 0}
+#define        TNSyp(name, amode)      {TERM, amode,  0, 0, 1, 0, 1, 0, 0}
+#define        TNSx(name, amode)       {TERM, amode,  0, 1, 0, 0, 0, 0, 0}
+#define        TNSZ(name, amode, sz)   {TERM, amode, sz, 0, 0, 0, 0, 0, 0}
+#define        TNSZy(name, amode, sz)  {TERM, amode, sz, 0, 1, 0, 0, 0, 0}
+#define        TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1, 0}
+#define        TS(name, amode)         {TERM, amode,  0, 0, 0, 0, 0, 0, 0}
+#define        TSx(name, amode)        {TERM, amode,  0, 1, 0, 0, 0, 0, 0}
+#define        TSy(name, amode)        {TERM, amode,  0, 0, 1, 0, 0, 0, 0}
+#define        TSp(name, amode)        {TERM, amode,  0, 0, 0, 0, 1, 0, 0}
+#define        TSZ(name, amode, sz)    {TERM, amode, sz, 0, 0, 0, 0, 0, 0}
+#define        TSaZ(name, amode, sz)   {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
+#define        TSZx(name, amode, sz)   {TERM, amode, sz, 1, 0, 0, 0, 0 ,0}
+#define        TSZy(name, amode, sz)   {TERM, amode, sz, 0, 1, 0, 0, 0, 0}
+#define        INVALID                 {TERM, UNKNOWN, 0, 0, 0, 0, 0, 0, 0}

 #else
 #else

-#define        IND(table)              {(instable_t *)table, 0, 0, 0, 0, 0}
-#define        INDx(table)             {(instable_t *)table, 0, 1, 0, 0, 0}
-#define        TNS(name, amode)        {TERM, amode,  0, 0, 0, 0}
-#define        TNSu(name, amode)       {TERM, amode,  0, 0, 1, 0}
-#define        TNSy(name, amode)       {TERM, amode,  0, 1, 0, 0}
-#define        TNSyp(name, amode)      {TERM, amode,  0, 1, 0, 1}
-#define        TNSx(name, amode)       {TERM, amode,  1, 0, 0, 0}
-#define        TNSZ(name, amode, sz)   {TERM, amode,  0, 0, 0, 0}
-#define        TNSZy(name, amode, sz)  {TERM, amode,  0, 1, 0, 0}
-#define        TS(name, amode)         {TERM, amode,  0, 0, 0, 0}
-#define        TSx(name, amode)        {TERM, amode,  1, 0, 0, 0}
-#define        TSy(name, amode)        {TERM, amode,  0, 1, 0, 0}
-#define        TSp(name, amode)        {TERM, amode,  0, 0, 0, 1}
-#define        TSZ(name, amode, sz)    {TERM, amode,  0, 0, 0, 0}
-#define        TSZx(name, amode, sz)   {TERM, amode,  1, 0, 0, 0}
-#define        TSZy(name, amode, sz)   {TERM, amode,  0, 1, 0, 0}
-#define        INVALID                 {TERM, UNKNOWN, 0, 0, 0, 0}
+#define        IND(table)              {(instable_t *)table, 0, 0, 0, 0, 0, 0, 0}
+#define        INDx(table)             {(instable_t *)table, 0, 1, 0, 0, 0, 0, 0}
+#define        TNS(name, amode)        {TERM, amode,  0, 0, 0, 0, 0, 0}
+#define        TNSu(name, amode)       {TERM, amode,  0, 0, 1, 0, 0, 0}
+#define        TNSy(name, amode)       {TERM, amode,  0, 1, 0, 0, 0, 0}
+#define        TNSyp(name, amode)      {TERM, amode,  0, 1, 0, 1, 0, 0}
+#define        TNSx(name, amode)       {TERM, amode,  1, 0, 0, 0, 0, 0}
+#define        TNSZ(name, amode, sz)   {TERM, amode,  0, 0, 0, 0, 0, 0}
+#define        TNSZy(name, amode, sz)  {TERM, amode,  0, 1, 0, 0, 0, 0}
+#define        TNSZvr(name, amode, sz) {TERM, amode,  0, 0, 0, 0, 1, 0}
+#define        TS(name, amode)         {TERM, amode,  0, 0, 0, 0, 0, 0}
+#define        TSx(name, amode)        {TERM, amode,  1, 0, 0, 0, 0, 0}
+#define        TSy(name, amode)        {TERM, amode,  0, 1, 0, 0, 0, 0}
+#define        TSp(name, amode)        {TERM, amode,  0, 0, 0, 1, 0, 0}
+#define        TSZ(name, amode, sz)    {TERM, amode,  0, 0, 0, 0, 0, 0}
+#define        TSaZ(name, amode, sz)   {TERM, amode,  0, 0, 0, 0, 0, 1}
+#define        TSZx(name, amode, sz)   {TERM, amode,  1, 0, 0, 0, 0, 0}
+#define        TSZy(name, amode, sz)   {TERM, amode,  0, 1, 0, 0, 0, 0}
+#define        INVALID                 {TERM, UNKNOWN, 0, 0, 0, 0, 0, 0}

 #endif
 
 #ifdef DIS_TEXT
 #endif
 
 #ifdef DIS_TEXT


@@ -374,6 +422,12 @@ const char *const dis_addr64_mode12[16] = {
  */
 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
 
  */
 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
 

+/*
+ * decode for scale from VSIB byte, note that we always include the scale factor
+ * to match gas.
+ */
+const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
+

 /*
  * register decoding for normal references to registers (ie. not addressing)
  */
 /*
  * register decoding for normal references to registers (ie. not addressing)
  */


@@ -427,6 +481,11 @@ const char *const dis_XMMREG[16] = {
     "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
 };
 
     "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
 };
 

+const char *const dis_YMMREG[16] = {
+    "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
+    "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
+};
+

 const char *const dis_SEGREG[16] = {
        "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
        "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
 const char *const dis_SEGREG[16] = {
        "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
        "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"


@@ -439,13 +498,15 @@ const char *const dis_PREDSUFFIX[8] = {
        "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
 };
 
        "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
 };
 

-
+const char *const dis_AVXvgrp7[3][8] = {
+       /*0     1       2               3               4               5       6               7*/
+/*71*/ {"",    "",     "vpsrlw",       "",             "vpsraw",       "",     "vpsllw",       ""},
+/*72*/ {"",    "",     "vpsrld",       "",             "vpsrad",       "",     "vpslld",       ""},
+/*73*/ {"",    "",     "vpsrlq",       "vpsrldq",      "",             "",     "vpsllq",       "vpslldq"}
+};

 
 #endif /* DIS_TEXT */
 
 
 #endif /* DIS_TEXT */
 

-
-
-

 /*
  *     "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
  */
 /*
  *     "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
  */


@@ -471,8 +532,8 @@ const instable_t dis_op0F00[8] = {
  */
 const instable_t dis_op0F01[8] = {
 
  */
 const instable_t dis_op0F01[8] = {
 

-/*  [0]  */    TNSZ("sgdt",MO,6),      TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",MO,6),        TNSZ("lidt",MO,6),
-/*  [4]  */    TNSZ("smsw",M,2),       INVALID,                TNSZ("lmsw",M,2),       TNS("invlpg",SWAPGS),
+/*  [0]  */    TNSZ("sgdt",VMx,6),     TNSZ("sidt",MONITOR_MWAIT,6),   TNSZ("lgdt",XGETBV_XSETBV,6),   TNSZ("lidt",SVM,6),
+/*  [4]  */    TNSZ("smsw",M,2),       INVALID,                TNSZ("lmsw",M,2),       TNS("invlpg",SWAPGS_RDTSCP),

 };
 
 /*
 };
 
 /*


@@ -489,7 +550,7 @@ const instable_t dis_op0F18[8] = {
  */
 const instable_t dis_op0FAE[8] = {
 /*  [0]  */    TNSZ("fxsave",M,512),   TNSZ("fxrstor",M,512),  TNS("ldmxcsr",M),       TNS("stmxcsr",M),
  */
 const instable_t dis_op0FAE[8] = {
 /*  [0]  */    TNSZ("fxsave",M,512),   TNSZ("fxrstor",M,512),  TNS("ldmxcsr",M),       TNS("stmxcsr",M),

-/*  [4]  */    INVALID,                TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
+/*  [4]  */    TNSZ("xsave",M,512),    TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),

 };
 
 /*
 };
 
 /*


@@ -503,15 +564,44 @@ const instable_t dis_op0FBA[8] = {
 };
 
 /*
 };
 
 /*

- *     Decode table for 0x0FC7 opcode
+ *     Decode table for 0x0FC7 opcode (group 9)

  */
 
 const instable_t dis_op0FC7[8] = {
 
 /*  [0]  */    INVALID,                TNS("cmpxchg8b",M),     INVALID,                INVALID,
  */
 
 const instable_t dis_op0FC7[8] = {
 
 /*  [0]  */    INVALID,                TNS("cmpxchg8b",M),     INVALID,                INVALID,

-/*  [4]  */    INVALID,                INVALID,        INVALID,                 INVALID,
+/*  [4]  */    INVALID,                INVALID,                TNS("vmptrld",MG9),     TNS("vmptrst",MG9),
+};
+
+/*
+ *     Decode table for 0x0FC7 opcode (group 9) mode 3
+ */
+
+const instable_t dis_op0FC7m3[8] = {
+
+/*  [0]  */    INVALID,                INVALID,        INVALID,                INVALID,
+/*  [4]  */    INVALID,                INVALID,        TNS("rdrand",MG9),      TNS("rdseed", MG9),
+};
+
+/*
+ *     Decode table for 0x0FC7 opcode with 0x66 prefix
+ */
+
+const instable_t dis_op660FC7[8] = {
+
+/*  [0]  */    INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4]  */    INVALID,                INVALID,                TNS("vmclear",M),       INVALID,

 };
 
 };
 

+/*
+ *     Decode table for 0x0FC7 opcode with 0xF3 prefix
+ */
+
+const instable_t dis_opF30FC7[8] = {
+
+/*  [0]  */    INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4]  */    INVALID,                INVALID,                TNS("vmxon",M),         INVALID,
+};

 
 /*
  *     Decode table for 0x0FC8 opcode -- 486 bswap instruction
 
 /*
  *     Decode table for 0x0FC8 opcode -- 486 bswap instruction


@@ -609,7 +699,7 @@ const instable_t dis_opSIMDdata16[256] = {
 /*  [70]  */   TNSZ("pshufd",XMMP,16), INVALID,                INVALID,                INVALID,
 /*  [74]  */   TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
 /*  [78]  */   TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID,          INVALID,
 /*  [70]  */   TNSZ("pshufd",XMMP,16), INVALID,                INVALID,                INVALID,
 /*  [74]  */   TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
 /*  [78]  */   TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID,          INVALID,

-/*  [7C]  */   INVALID,                INVALID,                TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
+/*  [7C]  */   TNSZ("haddpd",XMM,16),  TNSZ("hsubpd",XMM,16),  TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),

 
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -636,7 +726,7 @@ const instable_t dis_opSIMDdata16[256] = {
 /*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [D0]  */   INVALID,                TNSZ("psrlw",XMM,16),   TNSZ("psrld",XMM,16),   TNSZ("psrlq",XMM,16),
+/*  [D0]  */   TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16),   TNSZ("psrld",XMM,16),   TNSZ("psrlq",XMM,16),

 /*  [D4]  */   TNSZ("paddq",XMM,16),   TNSZ("pmullw",XMM,16),  TNSZ("movq",XMMS,8),    TNS("pmovmskb",XMMX3),
 /*  [D8]  */   TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16),  TNSZ("pand",XMM,16),
 /*  [DC]  */   TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16),  TNSZ("pandn",XMM,16),
 /*  [D4]  */   TNSZ("paddq",XMM,16),   TNSZ("pmullw",XMM,16),  TNSZ("movq",XMMS,8),    TNS("pmovmskb",XMMX3),
 /*  [D8]  */   TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16),  TNSZ("pand",XMM,16),
 /*  [DC]  */   TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16),  TNSZ("pandn",XMM,16),


@@ -652,6 +742,88 @@ const instable_t dis_opSIMDdata16[256] = {
 /*  [FC]  */   TNSZ("paddb",XMM,16),   TNSZ("paddw",XMM,16),   TNSZ("paddd",XMM,16),   INVALID,
 };
 
 /*  [FC]  */   TNSZ("paddb",XMM,16),   TNSZ("paddw",XMM,16),   TNSZ("paddd",XMM,16),   INVALID,
 };
 

+const instable_t dis_opAVX660F[256] = {
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [10]  */   TNSZ("vmovupd",VEX_MX,16),      TNSZ("vmovupd",VEX_RX,16),      TNSZ("vmovlpd",VEX_RMrX,8),     TNSZ("vmovlpd",VEX_RM,8),
+/*  [14]  */   TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   TNSZ("vmovapd",VEX_MX,16),      TNSZ("vmovapd",VEX_RX,16),      INVALID,                TNSZ("vmovntpd",VEX_RM,16),
+/*  [2C]  */   INVALID,                INVALID,                TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
+
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   TNS("vmovmskpd",VEX_MR),        TNSZ("vsqrtpd",VEX_MX,16),      INVALID,                INVALID,
+/*  [54]  */   TNSZ("vandpd",VEX_RMrX,16),     TNSZ("vandnpd",VEX_RMrX,16),    TNSZ("vorpd",VEX_RMrX,16),      TNSZ("vxorpd",VEX_RMrX,16),
+/*  [58]  */   TNSZ("vaddpd",VEX_RMrX,16),     TNSZ("vmulpd",VEX_RMrX,16),     TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
+/*  [5C]  */   TNSZ("vsubpd",VEX_RMrX,16),     TNSZ("vminpd",VEX_RMrX,16),     TNSZ("vdivpd",VEX_RMrX,16),     TNSZ("vmaxpd",VEX_RMrX,16),
+
+/*  [60]  */   TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
+/*  [64]  */   TNSZ("vpcmpgtb",VEX_RMrX,16),   TNSZ("vpcmpgtw",VEX_RMrX,16),   TNSZ("vpcmpgtd",VEX_RMrX,16),   TNSZ("vpackuswb",VEX_RMrX,16),
+/*  [68]  */   TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
+/*  [6C]  */   TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
+
+/*  [70]  */   TNSZ("vpshufd",VEX_MXI,16),     TNSZ("vgrp71",VEX_XXI,16),      TNSZ("vgrp72",VEX_XXI,16),              TNSZ("vgrp73",VEX_XXI,16),
+/*  [74]  */   TNSZ("vpcmpeqb",VEX_RMrX,16),   TNSZ("vpcmpeqw",VEX_RMrX,16),   TNSZ("vpcmpeqd",VEX_RMrX,16),   INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   TNSZ("vhaddpd",VEX_RMrX,16),    TNSZ("vhsubpd",VEX_RMrX,16),    TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                TNSZ("vcmppd",VEX_RMRX,16),     INVALID,
+/*  [C4]  */   TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR),       TNSZ("vshufpd",VEX_RMRX,16),    INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [D0]  */   TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16),       TNSZ("vpsrld",VEX_RMrX,16),     TNSZ("vpsrlq",VEX_RMrX,16),
+/*  [D4]  */   TNSZ("vpaddq",VEX_RMrX,16),     TNSZ("vpmullw",VEX_RMrX,16),    TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
+/*  [D8]  */   TNSZ("vpsubusb",VEX_RMrX,16),   TNSZ("vpsubusw",VEX_RMrX,16),   TNSZ("vpminub",VEX_RMrX,16),    TNSZ("vpand",VEX_RMrX,16),
+/*  [DC]  */   TNSZ("vpaddusb",VEX_RMrX,16),   TNSZ("vpaddusw",VEX_RMrX,16),   TNSZ("vpmaxub",VEX_RMrX,16),    TNSZ("vpandn",VEX_RMrX,16),
+
+/*  [E0]  */   TNSZ("vpavgb",VEX_RMrX,16),     TNSZ("vpsraw",VEX_RMrX,16),     TNSZ("vpsrad",VEX_RMrX,16),     TNSZ("vpavgw",VEX_RMrX,16),
+/*  [E4]  */   TNSZ("vpmulhuw",VEX_RMrX,16),   TNSZ("vpmulhw",VEX_RMrX,16),    TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
+/*  [E8]  */   TNSZ("vpsubsb",VEX_RMrX,16),    TNSZ("vpsubsw",VEX_RMrX,16),    TNSZ("vpminsw",VEX_RMrX,16),    TNSZ("vpor",VEX_RMrX,16),
+/*  [EC]  */   TNSZ("vpaddsb",VEX_RMrX,16),    TNSZ("vpaddsw",VEX_RMrX,16),    TNSZ("vpmaxsw",VEX_RMrX,16),    TNSZ("vpxor",VEX_RMrX,16),
+
+/*  [F0]  */   INVALID,                TNSZ("vpsllw",VEX_RMrX,16),     TNSZ("vpslld",VEX_RMrX,16),     TNSZ("vpsllq",VEX_RMrX,16),
+/*  [F4]  */   TNSZ("vpmuludq",VEX_RMrX,16),   TNSZ("vpmaddwd",VEX_RMrX,16),   TNSZ("vpsadbw",VEX_RMrX,16),    TNS("vmaskmovdqu",VEX_MX),
+/*  [F8]  */   TNSZ("vpsubb",VEX_RMrX,16),     TNSZ("vpsubw",VEX_RMrX,16),     TNSZ("vpsubd",VEX_RMrX,16),     TNSZ("vpsubq",VEX_RMrX,16),
+/*  [FC]  */   TNSZ("vpaddb",VEX_RMrX,16),     TNSZ("vpaddw",VEX_RMrX,16),     TNSZ("vpaddd",VEX_RMrX,16),     INVALID,
+};
+

 /*
  *     Decode table for SIMD instructions with the repnz (0xf2) prefix.
  */
 /*
  *     Decode table for SIMD instructions with the repnz (0xf2) prefix.
  */


@@ -661,7 +833,7 @@ const instable_t dis_opSIMDrepnz[256] = {
 /*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [10]  */   TNSZ("movsd",XMM,8),    TNSZ("movsd",XMMS,8),   INVALID,                INVALID,
+/*  [10]  */   TNSZ("movsd",XMM,8),    TNSZ("movsd",XMMS,8),   TNSZ("movddup",XMM,8),  INVALID,

 /*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -694,7 +866,7 @@ const instable_t dis_opSIMDrepnz[256] = {
 /*  [70]  */   TNSZ("pshuflw",XMMP,16),INVALID,                INVALID,                INVALID,
 /*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [78]  */   TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,                INVALID,
 /*  [70]  */   TNSZ("pshuflw",XMMP,16),INVALID,                INVALID,                INVALID,
 /*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [78]  */   TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,                INVALID,

-/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   TNSZ("haddps",XMM,16),  TNSZ("hsubps",XMM,16),  INVALID,                INVALID,

 
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -721,7 +893,7 @@ const instable_t dis_opSIMDrepnz[256] = {
 /*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D0]  */   TNSZ("addsubps",XMM,16),INVALID,                INVALID,                INVALID,

 /*  [D4]  */   INVALID,                INVALID,                TNS("movdq2q",XMMXM),   INVALID,
 /*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [D4]  */   INVALID,                INVALID,                TNS("movdq2q",XMMXM),   INVALID,
 /*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -731,30 +903,27 @@ const instable_t dis_opSIMDrepnz[256] = {
 /*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F0]  */   TNS("lddqu",XMMM),      INVALID,                INVALID,                INVALID,

 /*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 
 /*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 

-/*
- *     Decode table for SIMD instructions with the repz (0xf3) prefix.
- */
-const instable_t dis_opSIMDrepz[256] = {
+const instable_t dis_opAVXF20F[256] = {

 /*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [10]  */   TNSZ("movss",XMM,4),    TNSZ("movss",XMMS,4),   INVALID,                INVALID,
+/*  [10]  */   TNSZ("vmovsd",VEX_RMrX,8),      TNSZ("vmovsd",VEX_RRX,8),       TNSZ("vmovddup",VEX_MX,8),      INVALID,

 /*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [28]  */   INVALID,                INVALID,                TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
-/*  [2C]  */   TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,           INVALID,
+/*  [28]  */   INVALID,                INVALID,                TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
+/*  [2C]  */   TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID,         INVALID,

 
 /*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -766,20 +935,20 @@ const instable_t dis_opSIMDrepz[256] = {
 /*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [50]  */   INVALID,                TNSZ("sqrtss",XMM,4),   TNSZ("rsqrtss",XMM,4),  TNSZ("rcpss",XMM,4),
+/*  [50]  */   INVALID,                TNSZ("vsqrtsd",VEX_RMrX,8),     INVALID,                INVALID,

 /*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [58]  */   TNSZ("addss",XMM,4),    TNSZ("mulss",XMM,4),    TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
-/*  [5C]  */   TNSZ("subss",XMM,4),    TNSZ("minss",XMM,4),    TNSZ("divss",XMM,4),    TNSZ("maxss",XMM,4),
+/*  [58]  */   TNSZ("vaddsd",VEX_RMrX,8),      TNSZ("vmulsd",VEX_RMrX,8),      TNSZ("vcvtsd2ss",VEX_RMrX,8),   INVALID,
+/*  [5C]  */   TNSZ("vsubsd",VEX_RMrX,8),      TNSZ("vminsd",VEX_RMrX,8),      TNSZ("vdivsd",VEX_RMrX,8),      TNSZ("vmaxsd",VEX_RMrX,8),

 
 /*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [6C]  */   INVALID,                INVALID,                INVALID,                TNSZ("movdqu",XMM,16),
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 

-/*  [70]  */   TNSZ("pshufhw",XMMP,16),INVALID,                INVALID,                INVALID,
+/*  [70]  */   TNSZ("vpshuflw",VEX_MXI,16),INVALID,            INVALID,                INVALID,

 /*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [7C]  */   INVALID,                INVALID,                TNSZ("movq",XMM,8),     TNSZ("movdqu",XMMS,16),
+/*  [7C]  */   TNSZ("vhaddps",VEX_RMrX,8),     TNSZ("vhsubps",VEX_RMrX,8),     INVALID,                INVALID,

 
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -798,52 +967,52 @@ const instable_t dis_opSIMDrepz[256] = {
 
 /*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [B8]  */   TS("popcnt",MRw),       INVALID,                INVALID,                INVALID,
-/*  [BC]  */   INVALID,                TS("lzcnt",MRw),        INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 

-/*  [C0]  */   INVALID,                INVALID,                TNSZ("cmpss",XMMP,4),   INVALID,
+/*  [C0]  */   INVALID,                INVALID,                TNSZ("vcmpsd",VEX_RMRX,8),      INVALID,

 /*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
-/*  [D4]  */   INVALID,                INVALID,                TNS("movq2dq",XMMMX),   INVALID,
+/*  [D0]  */   TNSZ("vaddsubps",VEX_RMrX,8),   INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [E4]  */   INVALID,                INVALID,                TNSZ("cvtdq2pd",XMM,8), INVALID,
+/*  [E4]  */   INVALID,                INVALID,                TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,

 /*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F0]  */   TNSZ("vlddqu",VEX_MX,16),       INVALID,                INVALID,                INVALID,

 /*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 
 /*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 

-const instable_t dis_op0F38[256] = {
-/*  [00]  */   TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
-/*  [04]  */   TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
-/*  [08]  */   TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
+const instable_t dis_opAVXF20F3A[256] = {
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [10]  */   TNSZ("pblendvb",XMM_66r,16),INVALID,            INVALID,                INVALID,
-/*  [14]  */   TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID,        TNSZ("ptest",XMM_66r,16),
+/*  [10]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [1C]  */   TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 

-/*  [20]  */   TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
-/*  [24]  */   TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID,        INVALID,
-/*  [28]  */   TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [30]  */   TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
-/*  [34]  */   TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID,        TNSZ("pcmpgtq",XMM_66r,16),
-/*  [38]  */   TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
-/*  [3C]  */   TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 

-/*  [40]  */   TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID,        INVALID,
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -866,7 +1035,7 @@ const instable_t dis_op0F38[256] = {
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 /*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -898,24 +1067,24 @@ const instable_t dis_op0F38[256] = {
 /*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [F0]  */   TNS("crc32b",CRC32),    TS("crc32",CRC32),      INVALID,                INVALID,
+/*  [F0]  */   TNSZvr("rorx",VEX_MXI,6),INVALID,               INVALID,                INVALID,

 /*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 
 /*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 

-const instable_t dis_op0F3A[256] = {
+const instable_t dis_opAVXF20F38[256] = {

 /*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [08]  */   TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
-/*  [0C]  */   TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 /*  [10]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [10]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [14]  */   TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
+/*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [20]  */   TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [28]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [28]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -925,7 +1094,7 @@ const instable_t dis_op0F3A[256] = {
 /*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [40]  */   TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -935,7 +1104,7 @@ const instable_t dis_op0F3A[256] = {
 /*  [58]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [58]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 

-/*  [60]  */   TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -948,7 +1117,7 @@ const instable_t dis_op0F3A[256] = {
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,

 
 /*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,


@@ -981,104 +1150,786 @@ const instable_t dis_op0F3A[256] = {
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 
 /*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,

-/*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F4]  */   INVALID,                TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),

 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 
 /*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
 };
 

-/*
- *     Decode table for 0x0F opcodes
- */
-
-const instable_t dis_op0F[16][16] = {
-{
-/*  [00]  */   IND(dis_op0F00),        IND(dis_op0F01),        TNS("lar",MR),          TNS("lsl",MR),
-/*  [04]  */   INVALID,                TNS("syscall",NORM),    TNS("clts",NORM),       TNS("sysret",NORM),
-/*  [08]  */   TNS("invd",NORM),       TNS("wbinvd",NORM),     INVALID,                TNS("ud2",NORM),
+const instable_t dis_opAVXF30F38[256] = {
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,

-}, {
-/*  [10]  */   TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8),  TNSZ("movlps",XMMOS,8),
-/*  [14]  */   TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
-/*  [18]  */   IND(dis_op0F18),        INVALID,                INVALID,                INVALID,
-#if !defined(__APPLE__)
+
+/*  [10]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [14]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,

-#else
-/* Need to handle multi-byte NOP */
-/*  [1C]  */   INVALID,                INVALID,                INVALID,                TS("nop",Mw),
-#endif /* __APPLE __ */
-}, {
-/*  [20]  */   TSy("mov",SREG),        TSy("mov",SREG),        TSy("mov",SREG),        TSy("mov",SREG),
-/*  [24]  */   TSx("mov",SREG),        INVALID,                TSx("mov",SREG),        INVALID,
-/*  [28]  */   TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
-/*  [2C]  */   TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
-}, {
-/*  [30]  */   TNS("wrmsr",NORM),      TNS("rdtsc",NORM),      TNS("rdmsr",NORM),      TNS("rdpmc",NORM),
-/*  [34]  */   TNSx("sysenter",NORM),  TNSx("sysexit",NORM),   INVALID,                INVALID,
+
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,

 /*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
 /*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,

-}, {
-/*  [40]  */   TS("cmovx.o",MR),       TS("cmovx.no",MR),      TS("cmovx.b",MR),       TS("cmovx.ae",MR),
-/*  [44]  */   TS("cmovx.e",MR),       TS("cmovx.ne",MR),      TS("cmovx.be",MR),      TS("cmovx.a",MR),
-/*  [48]  */   TS("cmovx.s",MR),       TS("cmovx.ns",MR),      TS("cmovx.pe",MR),      TS("cmovx.po",MR),
-/*  [4C]  */   TS("cmovx.l",MR),       TS("cmovx.ge",MR),      TS("cmovx.le",MR),      TS("cmovx.g",MR),
-}, {
-/*  [50]  */   TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
-/*  [54]  */   TNSZ("andps",XMMO,16),  TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16),   TNSZ("xorps",XMMO,16),
-/*  [58]  */   TNSZ("addps",XMMO,16),  TNSZ("mulps",XMMO,16),  TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
-/*  [5C]  */   TNSZ("subps",XMMO,16),  TNSZ("minps",XMMO,16),  TNSZ("divps",XMMO,16),  TNSZ("maxps",XMMO,16),
-}, {
-/*  [60]  */   TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
-/*  [64]  */   TNSZ("pcmpgtb",MMO,8),  TNSZ("pcmpgtw",MMO,8),  TNSZ("pcmpgtd",MMO,8),  TNSZ("packuswb",MMO,8),
-/*  [68]  */   TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
-/*  [6C]  */   TNSZ("INVALID",MMO,0),  TNSZ("INVALID",MMO,0),  TNSZ("movd",MMO,4),     TNSZ("movq",MMO,8),
-}, {
-/*  [70]  */   TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR),       TNS("psrXXX",MR),       TNS("psrXXX",MR),
-/*  [74]  */   TNSZ("pcmpeqb",MMO,8),  TNSZ("pcmpeqw",MMO,8),  TNSZ("pcmpeqd",MMO,8),  TNS("emms",NORM),
-/*  [78]  */   TNS("INVALID",XMMO),    TNS("INVALID",XMMO),    INVALID,                INVALID,
-/*  [7C]  */   INVALID,                INVALID,                TNSZ("movd",MMOS,4),    TNSZ("movq",MMOS,8),
-}, {
-/*  [80]  */   TNS("jo",D),            TNS("jno",D),           TNS("jb",D),            TNS("jae",D),
-/*  [84]  */   TNS("je",D),            TNS("jne",D),           TNS("jbe",D),           TNS("ja",D),
-/*  [88]  */   TNS("js",D),            TNS("jns",D),           TNS("jp",D),            TNS("jnp",D),
-/*  [8C]  */   TNS("jl",D),            TNS("jge",D),           TNS("jle",D),           TNS("jg",D),
-}, {
-/*  [90]  */   TNS("seto",Mb),         TNS("setno",Mb),        TNS("setb",Mb),         TNS("setae",Mb),
-/*  [94]  */   TNS("sete",Mb),         TNS("setne",Mb),        TNS("setbe",Mb),        TNS("seta",Mb),
-/*  [98]  */   TNS("sets",Mb),         TNS("setns",Mb),        TNS("setp",Mb),         TNS("setnp",Mb),
-/*  [9C]  */   TNS("setl",Mb),         TNS("setge",Mb),        TNS("setle",Mb),        TNS("setg",Mb),
-}, {
-/*  [A0]  */   TSp("push",LSEG),       TSp("pop",LSEG),        TNS("cpuid",NORM),      TS("bt",RMw),
-/*  [A4]  */   TS("shld",DSHIFT),      TS("shld",DSHIFTcl),    INVALID,                INVALID,
-/*  [A8]  */   TSp("push",LSEG),       TSp("pop",LSEG),        TNS("rsm",NORM),        TS("bts",RMw),
-/*  [AC]  */   TS("shrd",DSHIFT),      TS("shrd",DSHIFTcl),    IND(dis_op0FAE),        TS("imul",MRw),
-}, {
-/*  [B0]  */   TNS("cmpxchgb",RMw),    TS("cmpxchg",RMw),      TS("lss",MR),           TS("btr",RMw),
-/*  [B4]  */   TS("lfs",MR),           TS("lgs",MR),           TS("movzb",MOVZ),       TNS("movzwl",MOVZ),
-/*  [B8]  */   TNS("INVALID",MRw),     INVALID,                IND(dis_op0FBA),        TS("btc",RMw),
-/*  [BC]  */   TS("bsf",MRw),          TS("bsr",MRw),          TS("movsb",MOVZ),       TNS("movswl",MOVZ),
-}, {
-/*  [C0]  */   TNS("xaddb",XADDB),     TS("xadd",RMw),         TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
-/*  [C4]  */   TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P),    TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
-/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
-/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
-}, {
-/*  [D0]  */   INVALID,                TNSZ("psrlw",MMO,8),    TNSZ("psrld",MMO,8),    TNSZ("psrlq",MMO,8),
-/*  [D4]  */   TNSZ("paddq",MMO,8),    TNSZ("pmullw",MMO,8),   TNSZ("INVALID",MMO,0),  TNS("pmovmskb",MMOM3),
-/*  [D8]  */   TNSZ("psubusb",MMO,8),  TNSZ("psubusw",MMO,8),  TNSZ("pminub",MMO,8),   TNSZ("pand",MMO,8),
-/*  [DC]  */   TNSZ("paddusb",MMO,8),  TNSZ("paddusw",MMO,8),  TNSZ("pmaxub",MMO,8),   TNSZ("pandn",MMO,8),
-}, {
-/*  [E0]  */   TNSZ("pavgb",MMO,8),    TNSZ("psraw",MMO,8),    TNSZ("psrad",MMO,8),    TNSZ("pavgw",MMO,8),
+
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [70]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F4]  */   INVALID,                TNSZvr("pext",VEX_RMrX,5),INVALID,              TNSZvr("sarx",VEX_VRMrX,5),
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+/*
+ *     Decode table for SIMD instructions with the repz (0xf3) prefix.
+ */
+const instable_t dis_opSIMDrepz[256] = {
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [10]  */   TNSZ("movss",XMM,4),    TNSZ("movss",XMMS,4),   TNSZ("movsldup",XMM,16),INVALID,
+/*  [14]  */   INVALID,                INVALID,                TNSZ("movshdup",XMM,16),INVALID,
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   INVALID,                INVALID,                TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
+/*  [2C]  */   TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,           INVALID,
+
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                TNSZ("sqrtss",XMM,4),   TNSZ("rsqrtss",XMM,4),  TNSZ("rcpss",XMM,4),
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   TNSZ("addss",XMM,4),    TNSZ("mulss",XMM,4),    TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
+/*  [5C]  */   TNSZ("subss",XMM,4),    TNSZ("minss",XMM,4),    TNSZ("divss",XMM,4),    TNSZ("maxss",XMM,4),
+
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                TNSZ("movdqu",XMM,16),
+
+/*  [70]  */   TNSZ("pshufhw",XMMP,16),INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                TNSZ("movq",XMM,8),     TNSZ("movdqu",XMMS,16),
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   TS("popcnt",MRw),       INVALID,                INVALID,                INVALID,
+/*  [BC]  */   TNSZ("tzcnt",MRw,5),    TS("lzcnt",MRw),        INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                TNSZ("cmpss",XMMP,4),   INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                TNS("movq2dq",XMMMX),   INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                TNSZ("cvtdq2pd",XMM,8), INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+
+const instable_t dis_opAVXF30F[256] = {
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [10]  */   TNSZ("vmovss",VEX_RMrX,4),      TNSZ("vmovss",VEX_RRX,4),       TNSZ("vmovsldup",VEX_MX,4),     INVALID,
+/*  [14]  */   INVALID,                INVALID,                TNSZ("vmovshdup",VEX_MX,4),     INVALID,
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   INVALID,                INVALID,                TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
+/*  [2C]  */   TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID,         INVALID,
+
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                TNSZ("vsqrtss",VEX_RMrX,4),     TNSZ("vrsqrtss",VEX_RMrX,4),    TNSZ("vrcpss",VEX_RMrX,4),
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   TNSZ("vaddss",VEX_RMrX,4),      TNSZ("vmulss",VEX_RMrX,4),      TNSZ("vcvtss2sd",VEX_RMrX,4),   TNSZ("vcvttps2dq",VEX_MX,16),
+/*  [5C]  */   TNSZ("vsubss",VEX_RMrX,4),      TNSZ("vminss",VEX_RMrX,4),      TNSZ("vdivss",VEX_RMrX,4),      TNSZ("vmaxss",VEX_RMrX,4),
+
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                TNSZ("vmovdqu",VEX_MX,16),
+
+/*  [70]  */   TNSZ("vpshufhw",VEX_MXI,16),INVALID,            INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16),
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                TNSZ("vcmpss",VEX_RMRX,4),      INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                TNSZ("vcvtdq2pd",VEX_MX,8),     INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+/*
+ * The following two tables are used to encode crc32 and movbe
+ * since they share the same opcodes.
+ */
+const instable_t dis_op0F38F0[2] = {
+/*  [00]  */   TNS("crc32b",CRC32),
+               TS("movbe",MOVBE),
+};
+
+const instable_t dis_op0F38F1[2] = {
+/*  [00]  */   TS("crc32",CRC32),
+               TS("movbe",MOVBE),
+};
+
+/*
+ * The following table is used to distinguish between adox and adcx which share
+ * the same opcodes.
+ */
+const instable_t dis_op0F38F6[2] = {
+/*  [00]  */   TNS("adcx",ADX),
+               TNS("adox",ADX),
+};
+
+const instable_t dis_op0F38[256] = {
+/*  [00]  */   TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
+/*  [04]  */   TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
+/*  [08]  */   TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [10]  */   TNSZ("pblendvb",XMM_66r,16),INVALID,            INVALID,                INVALID,
+/*  [14]  */   TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID,        TNSZ("ptest",XMM_66r,16),
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [1C]  */   TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
+
+/*  [20]  */   TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
+/*  [24]  */   TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID,        INVALID,
+/*  [28]  */   TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
+/*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [30]  */   TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
+/*  [34]  */   TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID,        TNSZ("pcmpgtq",XMM_66r,16),
+/*  [38]  */   TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
+/*  [3C]  */   TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
+
+/*  [40]  */   TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID,        INVALID,
+/*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [70]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [80]  */   TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
+/*  [CC]  */   TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID,            INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                TNSZ("aesimc",XMM_66r,16),
+/*  [DC]  */   TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F0]  */   IND(dis_op0F38F0),      IND(dis_op0F38F1),      INVALID,                INVALID,
+/*  [F4]  */   INVALID,                INVALID,                IND(dis_op0F38F6),      INVALID,
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+
+const instable_t dis_opAVX660F38[256] = {
+/*  [00]  */   TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
+/*  [04]  */   TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16),     TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
+/*  [08]  */   TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
+/*  [0C]  */   TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8),   TNSZ("vtestpd",VEX_RRI,16),
+
+/*  [10]  */   INVALID,                INVALID,                INVALID,                TNSZ("vcvtph2ps",VEX_MX,16),
+/*  [14]  */   INVALID,                INVALID,                TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
+/*  [18]  */   TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
+/*  [1C]  */   TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
+
+/*  [20]  */   TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
+/*  [24]  */   TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID,        INVALID,
+/*  [28]  */   TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
+/*  [2C]  */   TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
+
+/*  [30]  */   TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
+/*  [34]  */   TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
+/*  [38]  */   TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
+/*  [3C]  */   TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
+
+/*  [40]  */   TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID,      INVALID,
+/*  [44]  */   INVALID,                TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
+/*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [70]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID,  INVALID,
+/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [8C]  */   TSaZ("vpmaskmov",VEX_RMrX,16),INVALID,          TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
+
+/*  [90]  */   TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
+/*  [94]  */   INVALID,                INVALID,                TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
+/*  [98]  */   TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
+/*  [9C]  */   TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
+/*  [A8]  */   TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
+/*  [AC]  */   TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
+/*  [B8]  */   TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
+/*  [BC]  */   TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
+
+/*  [C0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                TNSZ("vaesimc",VEX_MX,16),
+/*  [DC]  */   TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F0]  */   IND(dis_op0F38F0),      IND(dis_op0F38F1),      INVALID,                INVALID,
+/*  [F4]  */   INVALID,                INVALID,                INVALID,                TNSZvr("shlx",VEX_VRMrX,5),
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+
+const instable_t dis_op0F3A[256] = {
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
+/*  [0C]  */   TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
+
+/*  [10]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [14]  */   TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [20]  */   TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [40]  */   TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
+/*  [44]  */   TNSZ("pclmulqdq",XMMP_66r,16),INVALID,          INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [60]  */   TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [70]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   TNSZ("sha1rnds4",XMMP,16),INVALID,              INVALID,                INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [DC]  */   INVALID,                INVALID,                INVALID,                TNSZ("aeskeygenassist",XMMP_66r,16),
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+
+const instable_t dis_opAVX660F3A[256] = {
+/*  [00]  */   TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
+/*  [04]  */   TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
+/*  [08]  */   TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
+/*  [0C]  */   TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
+
+/*  [10]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [14]  */   TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
+/*  [18]  */   TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID,         INVALID,
+/*  [1C]  */   INVALID,                TNSZ("vcvtps2ph",VEX_RX,16),            INVALID,                INVALID,
+
+/*  [20]  */   TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [2C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [40]  */   TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
+/*  [44]  */   TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID,         TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
+/*  [48]  */   INVALID,                INVALID,                TNSZ("vblendvps",VEX_RMRX,8),   TNSZ("vblendvpd",VEX_RMRX,16),
+/*  [4C]  */   TNSZ("vpblendvb",VEX_RMRX,16),INVALID,          INVALID,                INVALID,
+
+/*  [50]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [54]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [58]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [5C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [60]  */   TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [70]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [C0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [DC]  */   INVALID,                INVALID,                INVALID,                TNSZ("vaeskeygenassist",VEX_MXI,16),
+
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+
+/*  [F0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+
+/*
+ *     Decode table for 0x0F0D which uses the first byte of the mod_rm to
+ *     indicate a sub-code.
+ */
+const instable_t dis_op0F0D[8] = {
+/*  [00]  */   INVALID,                TNS("prefetchw",PREF),  TNS("prefetchwt1",PREF),INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+};
+
+/*
+ *     Decode table for 0x0F opcodes
+ */
+
+const instable_t dis_op0F[16][16] = {
+{
+/*  [00]  */   IND(dis_op0F00),        IND(dis_op0F01),        TNS("lar",MR),          TNS("lsl",MR),
+/*  [04]  */   INVALID,                TNS("syscall",NORM),    TNS("clts",NORM),       TNS("sysret",NORM),
+/*  [08]  */   TNS("invd",NORM),       TNS("wbinvd",NORM),     INVALID,                TNS("ud2",NORM),
+/*  [0C]  */   INVALID,                IND(dis_op0F0D),        INVALID,                INVALID,
+}, {
+/*  [10]  */   TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8),  TNSZ("movlps",XMMOS,8),
+/*  [14]  */   TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
+/*  [18]  */   IND(dis_op0F18),        INVALID,                INVALID,                INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                TS("nop",Mw),
+}, {
+/*  [20]  */   TSy("mov",SREG),        TSy("mov",SREG),        TSy("mov",SREG),        TSy("mov",SREG),
+/*  [24]  */   TSx("mov",SREG),        INVALID,                TSx("mov",SREG),        INVALID,
+/*  [28]  */   TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
+/*  [2C]  */   TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
+}, {
+/*  [30]  */   TNS("wrmsr",NORM),      TNS("rdtsc",NORM),      TNS("rdmsr",NORM),      TNS("rdpmc",NORM),
+/*  [34]  */   TNSx("sysenter",NORM),  TNSx("sysexit",NORM),   INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [40]  */   TS("cmovx.o",MR),       TS("cmovx.no",MR),      TS("cmovx.b",MR),       TS("cmovx.ae",MR),
+/*  [44]  */   TS("cmovx.e",MR),       TS("cmovx.ne",MR),      TS("cmovx.be",MR),      TS("cmovx.a",MR),
+/*  [48]  */   TS("cmovx.s",MR),       TS("cmovx.ns",MR),      TS("cmovx.pe",MR),      TS("cmovx.po",MR),
+/*  [4C]  */   TS("cmovx.l",MR),       TS("cmovx.ge",MR),      TS("cmovx.le",MR),      TS("cmovx.g",MR),
+}, {
+/*  [50]  */   TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
+/*  [54]  */   TNSZ("andps",XMMO,16),  TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16),   TNSZ("xorps",XMMO,16),
+/*  [58]  */   TNSZ("addps",XMMO,16),  TNSZ("mulps",XMMO,16),  TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
+/*  [5C]  */   TNSZ("subps",XMMO,16),  TNSZ("minps",XMMO,16),  TNSZ("divps",XMMO,16),  TNSZ("maxps",XMMO,16),
+}, {
+/*  [60]  */   TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
+/*  [64]  */   TNSZ("pcmpgtb",MMO,8),  TNSZ("pcmpgtw",MMO,8),  TNSZ("pcmpgtd",MMO,8),  TNSZ("packuswb",MMO,8),
+/*  [68]  */   TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
+/*  [6C]  */   TNSZ("INVALID",MMO,0),  TNSZ("INVALID",MMO,0),  TNSZ("movd",MMO,4),     TNSZ("movq",MMO,8),
+}, {
+/*  [70]  */   TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR),       TNS("psrXXX",MR),       TNS("psrXXX",MR),
+/*  [74]  */   TNSZ("pcmpeqb",MMO,8),  TNSZ("pcmpeqw",MMO,8),  TNSZ("pcmpeqd",MMO,8),  TNS("emms",NORM),
+/*  [78]  */   TNSy("vmread",RM),      TNSy("vmwrite",MR),     INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                TNSZ("movd",MMOS,4),    TNSZ("movq",MMOS,8),
+}, {
+/*  [80]  */   TNS("jo",D),            TNS("jno",D),           TNS("jb",D),            TNS("jae",D),
+/*  [84]  */   TNS("je",D),            TNS("jne",D),           TNS("jbe",D),           TNS("ja",D),
+/*  [88]  */   TNS("js",D),            TNS("jns",D),           TNS("jp",D),            TNS("jnp",D),
+/*  [8C]  */   TNS("jl",D),            TNS("jge",D),           TNS("jle",D),           TNS("jg",D),
+}, {
+/*  [90]  */   TNS("seto",Mb),         TNS("setno",Mb),        TNS("setb",Mb),         TNS("setae",Mb),
+/*  [94]  */   TNS("sete",Mb),         TNS("setne",Mb),        TNS("setbe",Mb),        TNS("seta",Mb),
+/*  [98]  */   TNS("sets",Mb),         TNS("setns",Mb),        TNS("setp",Mb),         TNS("setnp",Mb),
+/*  [9C]  */   TNS("setl",Mb),         TNS("setge",Mb),        TNS("setle",Mb),        TNS("setg",Mb),
+}, {
+/*  [A0]  */   TSp("push",LSEG),       TSp("pop",LSEG),        TNS("cpuid",NORM),      TS("bt",RMw),
+/*  [A4]  */   TS("shld",DSHIFT),      TS("shld",DSHIFTcl),    INVALID,                INVALID,
+/*  [A8]  */   TSp("push",LSEG),       TSp("pop",LSEG),        TNS("rsm",NORM),        TS("bts",RMw),
+/*  [AC]  */   TS("shrd",DSHIFT),      TS("shrd",DSHIFTcl),    IND(dis_op0FAE),        TS("imul",MRw),
+}, {
+/*  [B0]  */   TNS("cmpxchgb",RMw),    TS("cmpxchg",RMw),      TS("lss",MR),           TS("btr",RMw),
+/*  [B4]  */   TS("lfs",MR),           TS("lgs",MR),           TS("movzb",MOVZ),       TNS("movzwl",MOVZ),
+/*  [B8]  */   TNS("INVALID",MRw),     INVALID,                IND(dis_op0FBA),        TS("btc",RMw),
+/*  [BC]  */   TS("bsf",MRw),          TS("bsr",MRw),          TS("movsb",MOVZ),       TNS("movswl",MOVZ),
+}, {
+/*  [C0]  */   TNS("xaddb",XADDB),     TS("xadd",RMw),         TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
+/*  [C4]  */   TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P),    TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [D0]  */   INVALID,                TNSZ("psrlw",MMO,8),    TNSZ("psrld",MMO,8),    TNSZ("psrlq",MMO,8),
+/*  [D4]  */   TNSZ("paddq",MMO,8),    TNSZ("pmullw",MMO,8),   TNSZ("INVALID",MMO,0),  TNS("pmovmskb",MMOM3),
+/*  [D8]  */   TNSZ("psubusb",MMO,8),  TNSZ("psubusw",MMO,8),  TNSZ("pminub",MMO,8),   TNSZ("pand",MMO,8),
+/*  [DC]  */   TNSZ("paddusb",MMO,8),  TNSZ("paddusw",MMO,8),  TNSZ("pmaxub",MMO,8),   TNSZ("pandn",MMO,8),
+}, {
+/*  [E0]  */   TNSZ("pavgb",MMO,8),    TNSZ("psraw",MMO,8),    TNSZ("psrad",MMO,8),    TNSZ("pavgw",MMO,8),

 /*  [E4]  */   TNSZ("pmulhuw",MMO,8),  TNSZ("pmulhw",MMO,8),   TNS("INVALID",XMMO),    TNSZ("movntq",MMOMS,8),
 /*  [E8]  */   TNSZ("psubsb",MMO,8),   TNSZ("psubsw",MMO,8),   TNSZ("pminsw",MMO,8),   TNSZ("por",MMO,8),
 /*  [EC]  */   TNSZ("paddsb",MMO,8),   TNSZ("paddsw",MMO,8),   TNSZ("pmaxsw",MMO,8),   TNSZ("pxor",MMO,8),
 }, {
 /*  [E4]  */   TNSZ("pmulhuw",MMO,8),  TNSZ("pmulhw",MMO,8),   TNS("INVALID",XMMO),    TNSZ("movntq",MMOMS,8),
 /*  [E8]  */   TNSZ("psubsb",MMO,8),   TNSZ("psubsw",MMO,8),   TNSZ("pminsw",MMO,8),   TNSZ("por",MMO,8),
 /*  [EC]  */   TNSZ("paddsb",MMO,8),   TNSZ("paddsw",MMO,8),   TNSZ("pmaxsw",MMO,8),   TNSZ("pxor",MMO,8),
 }, {

-/*  [F0]  */   INVALID,                TNSZ("psllw",MMO,8),    TNSZ("pslld",MMO,8),    TNSZ("psllq",MMO,8),
-/*  [F4]  */   TNSZ("pmuludq",MMO,8),  TNSZ("pmaddwd",MMO,8),  TNSZ("psadbw",MMO,8),   TNSZ("maskmovq",MMOIMPL,8),
-/*  [F8]  */   TNSZ("psubb",MMO,8),    TNSZ("psubw",MMO,8),    TNSZ("psubd",MMO,8),    TNSZ("psubq",MMO,8),
-/*  [FC]  */   TNSZ("paddb",MMO,8),    TNSZ("paddw",MMO,8),    TNSZ("paddd",MMO,8),    INVALID,
+/*  [F0]  */   INVALID,                TNSZ("psllw",MMO,8),    TNSZ("pslld",MMO,8),    TNSZ("psllq",MMO,8),
+/*  [F4]  */   TNSZ("pmuludq",MMO,8),  TNSZ("pmaddwd",MMO,8),  TNSZ("psadbw",MMO,8),   TNSZ("maskmovq",MMOIMPL,8),
+/*  [F8]  */   TNSZ("psubb",MMO,8),    TNSZ("psubw",MMO,8),    TNSZ("psubd",MMO,8),    TNSZ("psubq",MMO,8),
+/*  [FC]  */   TNSZ("paddb",MMO,8),    TNSZ("paddw",MMO,8),    TNSZ("paddd",MMO,8),    INVALID,
+} };
+
+const instable_t dis_opAVX0F[16][16] = {
+{
+/*  [00]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [04]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [08]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [0C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [10]  */   TNSZ("vmovups",VEX_MX,16),      TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8),   TNSZ("vmovlps",VEX_RM,8),
+/*  [14]  */   TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
+/*  [18]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [1C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [20]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [24]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [28]  */   TNSZ("vmovaps",VEX_MX,16),      TNSZ("vmovaps",VEX_RX,16),INVALID,              TNSZ("vmovntps",VEX_RM,16),
+/*  [2C]  */   INVALID,                INVALID,                TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
+}, {
+/*  [30]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [34]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [38]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [3C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [40]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [44]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [48]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [4C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [50]  */   TNS("vmovmskps",VEX_MR),        TNSZ("vsqrtps",VEX_MX,16),      TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
+/*  [54]  */   TNSZ("vandps",VEX_RMrX,16),     TNSZ("vandnps",VEX_RMrX,16),    TNSZ("vorps",VEX_RMrX,16),      TNSZ("vxorps",VEX_RMrX,16),
+/*  [58]  */   TNSZ("vaddps",VEX_RMrX,16),     TNSZ("vmulps",VEX_RMrX,16),     TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
+/*  [5C]  */   TNSZ("vsubps",VEX_RMrX,16),     TNSZ("vminps",VEX_RMrX,16),     TNSZ("vdivps",VEX_RMrX,16),     TNSZ("vmaxps",VEX_RMrX,16),
+}, {
+/*  [60]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [64]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [68]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [6C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [70]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [74]  */   INVALID,                INVALID,                INVALID,                TNS("vzeroupper", VEX_NONE),
+/*  [78]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [7C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [80]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [84]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [88]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [8C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [90]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [94]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [98]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [9C]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [A0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [A8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [AC]  */   INVALID,                INVALID,                TNSZ("vldmxcsr",VEX_MO,2),              INVALID,
+}, {
+/*  [B0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [B8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [BC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [C0]  */   INVALID,                INVALID,                TNSZ("vcmpps",VEX_RMRX,16),INVALID,
+/*  [C4]  */   INVALID,                INVALID,                TNSZ("vshufps",VEX_RMRX,16),INVALID,
+/*  [C8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [CC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [D0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [D8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [DC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [E0]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E4]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [E8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [EC]  */   INVALID,                INVALID,                INVALID,                INVALID,
+}, {
+/*  [F0]  */   INVALID,                INVALID,                TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
+/*  [F4]  */   INVALID,                TNSZvr("bzhi",VEX_VRMrX,5),INVALID,             TNSZvr("bextr",VEX_VRMrX,5),
+/*  [F8]  */   INVALID,                INVALID,                INVALID,                INVALID,
+/*  [FC]  */   INVALID,                INVALID,                INVALID,                INVALID,

 } };
 
 } };
 

-

 /*
  *     Decode table for 0x80 opcodes
  */
 /*
  *     Decode table for 0x80 opcodes
  */


@@ -1237,19 +2088,19 @@ const instable_t dis_opFP1n2[8][8] = {
 /*  [2,0]  */  TNS("fiaddl",M),        TNS("fimull",M),        TNS("ficoml",M),        TNS("ficompl",M),
 /*  [2,4]  */  TNS("fisubl",M),        TNS("fisubrl",M),       TNS("fidivl",M),        TNS("fidivrl",M),
 }, {
 /*  [2,0]  */  TNS("fiaddl",M),        TNS("fimull",M),        TNS("ficoml",M),        TNS("ficompl",M),
 /*  [2,4]  */  TNS("fisubl",M),        TNS("fisubrl",M),       TNS("fidivl",M),        TNS("fidivrl",M),
 }, {

-/*  [3,0]  */  TNS("fildl",M),         INVALID,                TNS("fistl",M),         TNS("fistpl",M),
+/*  [3,0]  */  TNS("fildl",M),         TNSZ("tisttpl",M,4),    TNS("fistl",M),         TNS("fistpl",M),

 /*  [3,4]  */  INVALID,                TNSZ("fldt",M,10),      INVALID,                TNSZ("fstpt",M,10),
 }, {
 /*  [4,0]  */  TNSZ("faddl",M,8),      TNSZ("fmull",M,8),      TNSZ("fcoml",M,8),      TNSZ("fcompl",M,8),
 /*  [4,1]  */  TNSZ("fsubl",M,8),      TNSZ("fsubrl",M,8),     TNSZ("fdivl",M,8),      TNSZ("fdivrl",M,8),
 }, {
 /*  [3,4]  */  INVALID,                TNSZ("fldt",M,10),      INVALID,                TNSZ("fstpt",M,10),
 }, {
 /*  [4,0]  */  TNSZ("faddl",M,8),      TNSZ("fmull",M,8),      TNSZ("fcoml",M,8),      TNSZ("fcompl",M,8),
 /*  [4,1]  */  TNSZ("fsubl",M,8),      TNSZ("fsubrl",M,8),     TNSZ("fdivl",M,8),      TNSZ("fdivrl",M,8),
 }, {

-/*  [5,0]  */  TNSZ("fldl",M,8),       INVALID,                TNSZ("fstl",M,8),       TNSZ("fstpl",M,8),
+/*  [5,0]  */  TNSZ("fldl",M,8),       TNSZ("fisttpll",M,8),   TNSZ("fstl",M,8),       TNSZ("fstpl",M,8),

 /*  [5,4]  */  TNSZ("frstor",M,108),   INVALID,                TNSZ("fnsave",M,108),   TNSZ("fnstsw",M,2),
 }, {
 /*  [6,0]  */  TNSZ("fiadd",M,2),      TNSZ("fimul",M,2),      TNSZ("ficom",M,2),      TNSZ("ficomp",M,2),
 /*  [6,4]  */  TNSZ("fisub",M,2),      TNSZ("fisubr",M,2),     TNSZ("fidiv",M,2),      TNSZ("fidivr",M,2),
 }, {
 /*  [5,4]  */  TNSZ("frstor",M,108),   INVALID,                TNSZ("fnsave",M,108),   TNSZ("fnstsw",M,2),
 }, {
 /*  [6,0]  */  TNSZ("fiadd",M,2),      TNSZ("fimul",M,2),      TNSZ("ficom",M,2),      TNSZ("ficomp",M,2),
 /*  [6,4]  */  TNSZ("fisub",M,2),      TNSZ("fisubr",M,2),     TNSZ("fidiv",M,2),      TNSZ("fidivr",M,2),
 }, {

-/*  [7,0]  */  TNSZ("fild",M,2),       INVALID,                TNSZ("fist",M,2),       TNSZ("fistp",M,2),
+/*  [7,0]  */  TNSZ("fild",M,2),       TNSZ("fisttp",M,2),     TNSZ("fist",M,2),       TNSZ("fistp",M,2),

 /*  [7,4]  */  TNSZ("fbld",M,10),      TNSZ("fildll",M,8),     TNSZ("fbstp",M,10),     TNSZ("fistpll",M,8),
 } };
 
 /*  [7,4]  */  TNSZ("fbld",M,10),      TNSZ("fildll",M,8),     TNSZ("fbstp",M,10),     TNSZ("fistpll",M,8),
 } };
 


@@ -1336,30 +2187,14 @@ const instable_t dis_distable[16][16] = {
 /* [1,C] */    TNS("sbbb",IA),         TS("sbb",IA),           TSx("push",SEG),        TSx("pop",SEG),
 }, {
 /* [2,0] */    TNS("andb",RMw),        TS("and",RMw),          TNS("andb",MRw),        TS("and",MRw),
 /* [1,C] */    TNS("sbbb",IA),         TS("sbb",IA),           TSx("push",SEG),        TSx("pop",SEG),
 }, {
 /* [2,0] */    TNS("andb",RMw),        TS("and",RMw),          TNS("andb",MRw),        TS("and",MRw),

-#if !defined(__APPLE__)
-/* [2,4] */    TNS("andb",IA),         TS("and",IA),           TNSx("%es:",OVERRIDE),  TNSx("daa",NORM),
-#else

 /* [2,4] */    TNS("andb",IA),         TS("and",IA),           TNS("%es:",OVERRIDE),   TNSx("daa",NORM),
 /* [2,4] */    TNS("andb",IA),         TS("and",IA),           TNS("%es:",OVERRIDE),   TNSx("daa",NORM),

-#endif /* __APPLE__ */

 /* [2,8] */    TNS("subb",RMw),        TS("sub",RMw),          TNS("subb",MRw),        TS("sub",MRw),
 /* [2,8] */    TNS("subb",RMw),        TS("sub",RMw),          TNS("subb",MRw),        TS("sub",MRw),

-#if !defined(__APPLE__)
-/* [2,C] */    TNS("subb",IA),         TS("sub",IA),           TNSx("%cs:",OVERRIDE),  TNSx("das",NORM),
-#else

 /* [2,C] */    TNS("subb",IA),         TS("sub",IA),           TNS("%cs:",OVERRIDE),   TNSx("das",NORM),
 /* [2,C] */    TNS("subb",IA),         TS("sub",IA),           TNS("%cs:",OVERRIDE),   TNSx("das",NORM),

-#endif /* __APPLE__ */

 }, {
 /* [3,0] */    TNS("xorb",RMw),        TS("xor",RMw),          TNS("xorb",MRw),        TS("xor",MRw),
 }, {
 /* [3,0] */    TNS("xorb",RMw),        TS("xor",RMw),          TNS("xorb",MRw),        TS("xor",MRw),

-#if !defined(__APPLE__)
-/* [3,4] */    TNS("xorb",IA),         TS("xor",IA),           TNSx("%ss:",OVERRIDE),  TNSx("aaa",NORM),
-#else

 /* [3,4] */    TNS("xorb",IA),         TS("xor",IA),           TNS("%ss:",OVERRIDE),   TNSx("aaa",NORM),
 /* [3,4] */    TNS("xorb",IA),         TS("xor",IA),           TNS("%ss:",OVERRIDE),   TNSx("aaa",NORM),

-#endif /* __APPLE__ */

 /* [3,8] */    TNS("cmpb",RMw),        TS("cmp",RMw),          TNS("cmpb",MRw),        TS("cmp",MRw),
 /* [3,8] */    TNS("cmpb",RMw),        TS("cmp",RMw),          TNS("cmpb",MRw),        TS("cmp",MRw),

-#if !defined(__APPLE__)
-/* [3,C] */    TNS("cmpb",IA),         TS("cmp",IA),           TNSx("%ds:",OVERRIDE),  TNSx("aas",NORM),
-#else

 /* [3,C] */    TNS("cmpb",IA),         TS("cmp",IA),           TNS("%ds:",OVERRIDE),   TNSx("aas",NORM),
 /* [3,C] */    TNS("cmpb",IA),         TS("cmp",IA),           TNS("%ds:",OVERRIDE),   TNSx("aas",NORM),

-#endif /* __APPLE__ */

 }, {
 /* [4,0] */    TSx("inc",R),           TSx("inc",R),           TSx("inc",R),           TSx("inc",R),
 /* [4,4] */    TSx("inc",R),           TSx("inc",R),           TSx("inc",R),           TSx("inc",R),
 }, {
 /* [4,0] */    TSx("inc",R),           TSx("inc",R),           TSx("inc",R),           TSx("inc",R),
 /* [4,4] */    TSx("inc",R),           TSx("inc",R),           TSx("inc",R),           TSx("inc",R),


@@ -1389,7 +2224,7 @@ const instable_t dis_distable[16][16] = {
 /* [9,0] */    TNS("nop",NORM),        TS("xchg",RA),          TS("xchg",RA),          TS("xchg",RA),
 /* [9,4] */    TS("xchg",RA),          TS("xchg",RA),          TS("xchg",RA),          TS("xchg",RA),
 /* [9,8] */    TNS("cXtX",CBW),        TNS("cXtX",CWD),        TNSx("lcall",SO),       TNS("fwait",NORM),
 /* [9,0] */    TNS("nop",NORM),        TS("xchg",RA),          TS("xchg",RA),          TS("xchg",RA),
 /* [9,4] */    TS("xchg",RA),          TS("xchg",RA),          TS("xchg",RA),          TS("xchg",RA),
 /* [9,8] */    TNS("cXtX",CBW),        TNS("cXtX",CWD),        TNSx("lcall",SO),       TNS("fwait",NORM),

-/* [9,C] */    TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNSx("sahf",NORM),      TNSx("lahf",NORM),
+/* [9,C] */    TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM),       TNS("lahf",NORM),

 }, {
 /* [A,0] */    TNS("movb",OA),         TS("mov",OA),           TNS("movb",AO),         TS("mov",AO),
 /* [A,4] */    TNSZ("movsb",SD,1),     TS("movs",SD),          TNSZ("cmpsb",SD,1),     TS("cmps",SD),
 }, {
 /* [A,0] */    TNS("movb",OA),         TS("mov",OA),           TNS("movb",AO),         TS("mov",AO),
 /* [A,4] */    TNSZ("movsb",SD,1),     TS("movs",SD),          TNSZ("cmpsb",SD,1),     TS("cmps",SD),


@@ -1445,6 +2280,29 @@ const instable_t dis_distable[16][16] = {
 #define        REX_X 0x02      /* high order bit extension of SIB index field */
 #define        REX_B 0x01      /* extends ModRM r_m, SIB base, or opcode reg */
 
 #define        REX_X 0x02      /* high order bit extension of SIB index field */
 #define        REX_B 0x01      /* extends ModRM r_m, SIB base, or opcode reg */
 

+/*
+ * These are the individual fields of a VEX prefix.
+ */
+#define        VEX_R 0x08      /* REX.R in 1's complement form */
+#define        VEX_X 0x04      /* REX.X in 1's complement form */
+#define        VEX_B 0x02      /* REX.B in 1's complement form */
+/* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
+#define        VEX_L 0x04
+#define        VEX_W 0x08      /* opcode specific, use like REX.W */
+#define        VEX_m 0x1F      /* VEX m-mmmm field */
+#define        VEX_v 0x78      /* VEX register specifier */
+#define        VEX_p 0x03      /* VEX pp field, opcode extension */
+
+/* VEX m-mmmm field, only used by three bytes prefix */
+#define        VEX_m_0F 0x01   /* implied 0F leading opcode byte */
+#define        VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
+#define        VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
+
+/* VEX pp field, providing equivalent functionality of a SIMD prefix */
+#define        VEX_p_66 0x01
+#define        VEX_p_F3 0x02
+#define        VEX_p_F2 0x03
+

 /*
  * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
  */
 /*
  * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
  */


@@ -1471,6 +2329,81 @@ static int isize64[] = {1, 2, 4, 8};
 #define        DEBUG_OPND      6       /* "value" used to indicate a debug reg */
 #define        TEST_OPND       7       /* "value" used to indicate a test reg */
 #define        WORD_OPND       8       /* w-bit value indicating word size reg */
 #define        DEBUG_OPND      6       /* "value" used to indicate a debug reg */
 #define        TEST_OPND       7       /* "value" used to indicate a test reg */
 #define        WORD_OPND       8       /* w-bit value indicating word size reg */

+#define        YMM_OPND        9       /* "value" used to indicate a ymm reg */
+
+/*
+ * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
+ * there's not really a consistent scheme that we can use to know what the mode
+ * is supposed to be for a given type. Various instructions, like VPGATHERDD,
+ * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
+ * some registers match VEX_L, but the VSIB is always XMM.
+ *
+ * The simplest way to deal with this is to just define a table based on the
+ * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
+ * them.
+ *
+ * We further have to subdivide this based on the value of VEX_W and the value
+ * of VEX_L. The array is constructed to be indexed as:
+ *     [opcode - 0x90][VEX_W][VEX_L].
+ */
+/* w = 0, 0x90 */
+typedef struct dis_gather_regs {
+       uint_t dgr_arg0;        /* src reg */
+       uint_t dgr_arg1;        /* vsib reg */
+       uint_t dgr_arg2;        /* dst reg */
+       const char *dgr_suffix; /* suffix to append */
+} dis_gather_regs_t;
+
+static dis_gather_regs_t dis_vgather[4][2][2] = {
+       {
+               /* op 0x90, W.0 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
+                       { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
+               },
+               /* op 0x90, W.1 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
+                       { YMM_OPND, XMM_OPND, YMM_OPND, "q" }
+               }
+       },
+       {
+               /* op 0x91, W.0 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
+                       { XMM_OPND, YMM_OPND, XMM_OPND, "d" },
+               },
+               /* op 0x91, W.1 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
+                       { YMM_OPND, YMM_OPND, YMM_OPND, "q" },
+               }
+       },
+       {
+               /* op 0x92, W.0 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
+                       { YMM_OPND, YMM_OPND, YMM_OPND, "s" }
+               },
+               /* op 0x92, W.1 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
+                       { YMM_OPND, XMM_OPND, YMM_OPND, "d" }
+               }
+       },
+       {
+               /* op 0x93, W.0 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
+                       { XMM_OPND, YMM_OPND, XMM_OPND, "s" }
+               },
+               /* op 0x93, W.1 */
+               {
+                       { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
+                       { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
+               }
+       }
+};

 
 /*
  * Get the next byte and separate the op code into the high and low nibbles.
 
 /*
  * Get the next byte and separate the op code into the high and low nibbles.


@@ -1555,6 +2488,26 @@ dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
        }
 }
 
        }
 }
 

+/*
+ * Adjust register selection based on any VEX prefix bits present.
+ * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
+ */
+/*ARGSUSED*/
+static void
+dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
+{
+#pragma unused (mode)
+       if (reg != NULL && r_m == NULL) {
+               if (!(vex_byte1 & VEX_B))
+                       *reg += 8;
+       } else {
+               if (reg != NULL && ((VEX_R & vex_byte1) == 0))
+                       *reg += 8;
+               if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
+                       *r_m += 8;
+       }
+}
+

 /*
  * Get an immediate operand of the given size, with sign extension.
  */
 /*
  * Get an immediate operand of the given size, with sign extension.
  */


@@ -1563,7 +2516,7 @@ dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
 {
        int i;
        int byte;
 {
        int i;
        int byte;

-       int valsize;
+       int valsize = 0;

 
        if (x->d86_numopnds < (uint_t)opindex + 1)
                x->d86_numopnds = (uint_t)opindex + 1;
 
        if (x->d86_numopnds < (uint_t)opindex + 1)
                x->d86_numopnds = (uint_t)opindex + 1;


@@ -1582,6 +2535,7 @@ dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
                break;
        case MM_OPND:
        case XMM_OPND:
                break;
        case MM_OPND:
        case XMM_OPND:

+       case YMM_OPND:

        case SEG_OPND:
        case CONTROL_OPND:
        case DEBUG_OPND:
        case SEG_OPND:
        case CONTROL_OPND:
        case DEBUG_OPND:


@@ -1696,6 +2650,9 @@ dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
                case XMM_OPND:
                        (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
                        break;
                case XMM_OPND:
                        (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
                        break;

+               case YMM_OPND:
+                       (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
+                       break;

                case SEG_OPND:
                        (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
                        break;
                case SEG_OPND:
                        (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
                        break;


@@ -1825,16 +2782,29 @@ dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
        } else {
                uint_t need_paren = 0;
                char **regs;
        } else {
                uint_t need_paren = 0;
                char **regs;

+               char **bregs;
+               const char *const *sf;

                if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
                        regs = (char **)dis_REG32;
                else
                        regs = (char **)dis_REG64;
 
                if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
                        regs = (char **)dis_REG32;
                else
                        regs = (char **)dis_REG64;
 

+               if (x->d86_vsib != 0) {
+                       if (wbit == YMM_OPND) /* NOTE this is not addr_size! */
+                               bregs = (char **)dis_YMMREG;
+                       else
+                               bregs = (char **)dis_XMMREG;
+                       sf = dis_vscale_factor;
+               } else {
+                       bregs = regs;
+                       sf = dis_scale_factor;
+               }
+

                /*
                 * print the base (if any)
                 */
                if (base == EBP_REGNO && mode == 0) {
                /*
                 * print the base (if any)
                 */
                if (base == EBP_REGNO && mode == 0) {

-                       if (index != ESP_REGNO) {
+                       if (index != ESP_REGNO || x->d86_vsib != 0) {

                                (void) strlcat(opnd, "(", OPLEN);
                                need_paren = 1;
                        }
                                (void) strlcat(opnd, "(", OPLEN);
                                need_paren = 1;
                        }


@@ -1847,10 +2817,10 @@ dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
                /*
                 * print the index (if any)
                 */
                /*
                 * print the index (if any)
                 */

-               if (index != ESP_REGNO) {
+               if (index != ESP_REGNO || x->d86_vsib) {

                        (void) strlcat(opnd, ",", OPLEN);
                        (void) strlcat(opnd, ",", OPLEN);

-                       (void) strlcat(opnd, regs[index], OPLEN);
-                       (void) strlcat(opnd, dis_scale_factor[ss], OPLEN);
+                       (void) strlcat(opnd, bregs[index], OPLEN);
+                       (void) strlcat(opnd, sf[ss], OPLEN);

                } else
                        if (need_paren)
                                (void) strlcat(opnd, ")", OPLEN);
                } else
                        if (need_paren)
                                (void) strlcat(opnd, ")", OPLEN);


@@ -1948,16 +2918,16 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
        uint_t w2;              /* wbit value for second operand */
        uint_t vbit;
        uint_t mode = 0;        /* mode value from ModRM byte */
        uint_t w2;              /* wbit value for second operand */
        uint_t vbit;
        uint_t mode = 0;        /* mode value from ModRM byte */

-       uint_t reg;             /* reg value from ModRM byte */
-       uint_t r_m;             /* r_m value from ModRM byte */
-
-       uint_t opcode1;         /* high nibble of 1st byte */
-       uint_t opcode2;         /* low nibble of 1st byte */
-       uint_t opcode3;         /* extra opcode bits usually from ModRM byte */
-       uint_t opcode4;         /* high nibble of 2nd byte */
-       uint_t opcode5;         /* low nibble of 2nd byte */
-       uint_t opcode6;         /* high nibble of 3rd byte */
-       uint_t opcode7;         /* low nibble of 3rd byte */
+       uint_t reg = 0;         /* reg value from ModRM byte */
+       uint_t r_m = 0;         /* r_m value from ModRM byte */
+
+       uint_t opcode1 = 0;             /* high nibble of 1st byte */
+       uint_t opcode2 = 0;             /* low nibble of 1st byte */
+       uint_t opcode3 = 0;             /* extra opcode bits usually from ModRM byte */
+       uint_t opcode4 = 0;             /* high nibble of 2nd byte */
+       uint_t opcode5 = 0;             /* low nibble of 2nd byte */
+       uint_t opcode6 = 0;             /* high nibble of 3rd byte */
+       uint_t opcode7 = 0;             /* low nibble of 3rd byte */

        uint_t opcode_bytes = 1;
 
        /*
        uint_t opcode_bytes = 1;
 
        /*


@@ -1969,6 +2939,41 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
        uint_t  lock_prefix = 0;
        uint_t  rep_prefix = 0;
        uint_t  rex_prefix = 0; /* amd64 register extension prefix */
        uint_t  lock_prefix = 0;
        uint_t  rep_prefix = 0;
        uint_t  rex_prefix = 0; /* amd64 register extension prefix */

+
+       /*
+        * Intel VEX instruction encoding prefix and fields
+        */
+
+       /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
+       uint_t vex_prefix = 0;
+
+       /*
+        * VEX prefix byte 1, includes vex.r, vex.x and vex.b
+        * (for 3 bytes prefix)
+        */
+       uint_t vex_byte1 = 0;
+
+       /*
+        * For 32-bit mode, it should prefetch the next byte to
+        * distinguish between AVX and les/lds
+        */
+       uint_t vex_prefetch = 0;
+
+       uint_t vex_m = 0;
+       uint_t vex_v = 0;
+       uint_t vex_p = 0;
+       uint_t vex_R = 1;
+       uint_t vex_X = 1;
+       uint_t vex_B = 1;
+       uint_t vex_W = 0;
+       uint_t vex_L = 0;
+       dis_gather_regs_t *vreg;
+
+#ifdef DIS_TEXT
+       /* Instruction name for BLS* family of instructions */
+       char *blsinstr;
+#endif
+

        size_t  off;
 
        instable_t dp_mmx;
        size_t  off;
 
        instable_t dp_mmx;


@@ -1988,8 +2993,10 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                x->d86_opnd[i].d86_mode = MODE_NONE;
        }
 #endif
                x->d86_opnd[i].d86_mode = MODE_NONE;
        }
 #endif

-       x->d86_error = 0;
+       x->d86_rex_prefix = 0;
+       x->d86_got_modrm = 0;

        x->d86_memsize = 0;
        x->d86_memsize = 0;

+       x->d86_vsib = 0;

 
        if (cpu_mode == SIZE16) {
                opnd_size = SIZE16;
 
        if (cpu_mode == SIZE16) {
                opnd_size = SIZE16;


@@ -2013,7 +3020,6 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
            x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
 #ifdef DIS_TEXT
                (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
            x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
 #ifdef DIS_TEXT
                (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);

-               x->d86_mnem[OPLEN - 1] = '\0';

 #endif
                goto done;
        }
 #endif
                goto done;
        }


@@ -2069,6 +3075,164 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                        if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
                                goto error;
                        dp = (instable_t *)&dis_distable[opcode1][opcode2];
                        if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
                                goto error;
                        dp = (instable_t *)&dis_distable[opcode1][opcode2];

+               } else if (opcode1 == 0xC &&
+                   (opcode2 == 0x4 || opcode2 == 0x5)) {
+                       /* AVX instructions */
+                       vex_prefix = (opcode1 << 4) | opcode2;
+                       x->d86_rex_prefix = 0x40;
+               }
+       } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
+               /* LDS, LES or AVX */
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               vex_prefetch = 1;
+
+               if (mode == REG_ONLY) {
+                       /* AVX */
+                       vex_prefix = (opcode1 << 4) | opcode2;
+                       x->d86_rex_prefix = 0x40;
+                       opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
+                       opcode4 = ((reg << 3) | r_m) & 0x0F;
+               }
+       }
+
+       if (vex_prefix == VEX_2bytes) {
+               if (!vex_prefetch) {
+                       if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
+                               goto error;
+               }
+               vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
+               vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
+               vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
+               vex_p = opcode4 & VEX_p;
+               /*
+                * The vex.x and vex.b bits are not defined in two bytes
+                * mode vex prefix, their default values are 1
+                */
+               vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
+
+               if (vex_R == 0)
+                       x->d86_rex_prefix |= REX_R;
+
+               if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
+                       goto error;
+
+               switch (vex_p) {
+                       case VEX_p_66:
+                               dp = (instable_t *)
+                                   &dis_opAVX660F[(opcode1 << 4) | opcode2];
+                               break;
+                       case VEX_p_F3:
+                               dp = (instable_t *)
+                                   &dis_opAVXF30F[(opcode1 << 4) | opcode2];
+                               break;
+                       case VEX_p_F2:
+                               dp = (instable_t *)
+                                   &dis_opAVXF20F [(opcode1 << 4) | opcode2];
+                               break;
+                       default:
+                               dp = (instable_t *)
+                                   &dis_opAVX0F[opcode1][opcode2];
+
+               }
+
+       } else if (vex_prefix == VEX_3bytes) {
+               if (!vex_prefetch) {
+                       if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
+                               goto error;
+               }
+               vex_R = (opcode3 & VEX_R) >> 3;
+               vex_X = (opcode3 & VEX_X) >> 2;
+               vex_B = (opcode3 & VEX_B) >> 1;
+               vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
+               vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
+
+               if (vex_R == 0)
+                       x->d86_rex_prefix |= REX_R;
+               if (vex_X == 0)
+                       x->d86_rex_prefix |= REX_X;
+               if (vex_B == 0)
+                       x->d86_rex_prefix |= REX_B;
+
+               if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
+                       goto error;
+               vex_W = (opcode5 & VEX_W) >> 3;
+               vex_L = (opcode6 & VEX_L) >> 2;
+               vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
+               vex_p = opcode6 & VEX_p;
+
+               if (vex_W)
+                       x->d86_rex_prefix |= REX_W;
+
+               /* Only these three vex_m values valid; others are reserved */
+               if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
+                   (vex_m != VEX_m_0F3A))
+                       goto error;
+
+               if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
+                       goto error;
+
+               switch (vex_p) {
+                       case VEX_p_66:
+                               if (vex_m == VEX_m_0F) {
+                                       dp = (instable_t *)
+                                           &dis_opAVX660F
+                                           [(opcode1 << 4) | opcode2];
+                               } else if (vex_m == VEX_m_0F38) {
+                                       dp = (instable_t *)
+                                           &dis_opAVX660F38
+                                           [(opcode1 << 4) | opcode2];
+                               } else if (vex_m == VEX_m_0F3A) {
+                                       dp = (instable_t *)
+                                           &dis_opAVX660F3A
+                                           [(opcode1 << 4) | opcode2];
+                               } else {
+                                       goto error;
+                               }
+                               break;
+                       case VEX_p_F3:
+                               if (vex_m == VEX_m_0F) {
+                                       dp = (instable_t *)
+                                           &dis_opAVXF30F
+                                           [(opcode1 << 4) | opcode2];
+                               } else if (vex_m == VEX_m_0F38) {
+                                       dp = (instable_t *)
+                                           &dis_opAVXF30F38
+                                           [(opcode1 << 4) | opcode2];
+                               } else {
+                                       goto error;
+                               }
+                               break;
+                       case VEX_p_F2:
+                               if (vex_m == VEX_m_0F) {
+                                       dp = (instable_t *)
+                                           &dis_opAVXF20F
+                                           [(opcode1 << 4) | opcode2];
+                               } else if (vex_m == VEX_m_0F3A) {
+                                       dp = (instable_t *)
+                                           &dis_opAVXF20F3A
+                                           [(opcode1 << 4) | opcode2];
+                               } else if (vex_m == VEX_m_0F38) {
+                                       dp = (instable_t *)
+                                           &dis_opAVXF20F38
+                                           [(opcode1 << 4) | opcode2];
+                               } else {
+                                       goto error;
+                               }
+                               break;
+                       default:
+                               dp = (instable_t *)
+                                   &dis_opAVX0F[opcode1][opcode2];
+
+               }
+       }
+       if (vex_prefix) {
+               if (dp->it_vexwoxmm) {
+                       wbit = LONG_OPND;
+               } else {
+                       if (vex_L)
+                               wbit = YMM_OPND;
+                       else
+                               wbit = XMM_OPND;

                }
        }
 
                }
        }
 


@@ -2078,7 +3242,7 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
         * ignored.
         */
        if (cpu_mode == SIZE64) {
         * ignored.
         */
        if (cpu_mode == SIZE64) {

-               if (rex_prefix & REX_W)
+               if ((rex_prefix & REX_W) || vex_W)

                        opnd_size = SIZE64;
                else if (opnd_size_prefix)
                        opnd_size = SIZE16;
                        opnd_size = SIZE64;
                else if (opnd_size_prefix)
                        opnd_size = SIZE16;


@@ -2096,7 +3260,6 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                if (addr_size_prefix)
                        addr_size = SIZE32;
        }
                if (addr_size_prefix)
                        addr_size = SIZE32;
        }

-

        /*
         * The pause instruction - a repz'd nop.  This doesn't fit
         * with any of the other prefix goop added for SSE, so we'll
        /*
         * The pause instruction - a repz'd nop.  This doesn't fit
         * with any of the other prefix goop added for SSE, so we'll


@@ -2139,6 +3302,8 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                                goto error;
 #endif
                        switch (dp->it_adrmode) {
                                goto error;
 #endif
                        switch (dp->it_adrmode) {

+                               case XMMP:
+                                       break;

                                case XMMP_66r:
                                case XMMPRM_66r:
                                case XMM3PM_66r:
                                case XMMP_66r:
                                case XMMPRM_66r:
                                case XMM3PM_66r:


@@ -2165,11 +3330,66 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                        if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
                                goto error;
                        dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
                        if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
                                goto error;
                        dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];

+
+                       /*
+                        * Both crc32 and movbe have the same 3rd opcode
+                        * byte of either 0xF0 or 0xF1, so we use another
+                        * indirection to distinguish between the two.
+                        */
+                       if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
+                           dp->it_indirect == (instable_t *)dis_op0F38F1) {
+
+                               dp = dp->it_indirect;
+                               if (rep_prefix != 0xF2) {
+                                       /* It is movbe */
+                                       dp++;
+                               }
+                       }
+
+                       /*
+                        * The adx family of instructions (adcx and adox)
+                        * continue the classic Intel tradition of abusing
+                        * arbitrary prefixes without actually meaning the
+                        * prefix bit. Therefore, if we find either the
+                        * opnd_size_prefix or rep_prefix we end up zeroing it
+                        * out after making our determination so as to ensure
+                        * that we don't get confused and accidentally print
+                        * repz prefixes and the like on these instructions.
+                        *
+                        * In addition, these instructions are actually much
+                        * closer to AVX instructions in semantics. Importantly,
+                        * they always default to having 32-bit operands.
+                        * However, if the CPU is in 64-bit mode, then and only
+                        * then, does it use REX.w promotes things to 64-bits
+                        * and REX.r allows 64-bit mode to use register r8-r15.
+                        */
+                       if (dp->it_indirect == (instable_t *)dis_op0F38F6) {
+                               dp = dp->it_indirect;
+                               if (opnd_size_prefix == 0 &&
+                                   rep_prefix == 0xf3) {
+                                       /* It is adox */
+                                       dp++;
+                               } else if (opnd_size_prefix != 0x66 &&
+                                   rep_prefix != 0) {
+                                       /* It isn't adcx */
+                                       goto error;
+                               }
+                               opnd_size_prefix = 0;
+                               rep_prefix = 0;
+                               opnd_size = SIZE32;
+                               if (rex_prefix & REX_W)
+                                       opnd_size = SIZE64;
+                       }
+

 #ifdef DIS_TEXT
                        if (LIT_STRNEQL(dp->it_name, "INVALID"))
                                goto error;
 #endif
                        switch (dp->it_adrmode) {
 #ifdef DIS_TEXT
                        if (LIT_STRNEQL(dp->it_name, "INVALID"))
                                goto error;
 #endif
                        switch (dp->it_adrmode) {

+                               case ADX:
+                               case XMM:
+                                       break;
+                               case RM_66r:

                                case XMM_66r:
                                case XMMM_66r:
                                        if (opnd_size_prefix == 0) {
                                case XMM_66r:
                                case XMMM_66r:
                                        if (opnd_size_prefix == 0) {


@@ -2193,6 +3413,11 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                                        }
                                        rep_prefix = 0;
                                        break;
                                        }
                                        rep_prefix = 0;
                                        break;

+                               case MOVBE:
+                                       if (rep_prefix != 0x0) {
+                                               goto error;
+                                       }
+                                       break;

                                default:
                                        goto error;
                        }
                                default:
                                        goto error;
                        }


@@ -2239,8 +3464,11 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
         * In amd64 bit mode, ARPL opcode is changed to MOVSXD
         * (sign extend 32bit to 64 bit)
         */
         * In amd64 bit mode, ARPL opcode is changed to MOVSXD
         * (sign extend 32bit to 64 bit)
         */

-       if (cpu_mode == SIZE64 && opcode1 == 0x6 && opcode2 == 0x3)
+       if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
+           opcode1 == 0x6 && opcode2 == 0x3)
+       {

                dp = (instable_t *)&dis_opMOVSLD;
                dp = (instable_t *)&dis_opMOVSLD;

+       }

 
        /*
         * at this point we should have a correct (or invalid) opcode
 
        /*
         * at this point we should have a correct (or invalid) opcode


@@ -2252,9 +3480,12 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                goto error;
 
        /*
                goto error;
 
        /*

-        * deal with MMX/SSE opcodes which are changed by prefixes
+        * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
+        * need to include UNKNOWN below, as we may have instructions that
+        * actually have a prefix, but don't exist in any other form.

         */
        switch (dp->it_adrmode) {
         */
        switch (dp->it_adrmode) {

+       case UNKNOWN:

        case MMO:
        case MMOIMPL:
        case MMO3P:
        case MMO:
        case MMOIMPL:
        case MMO3P:


@@ -2313,6 +3544,59 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                }
                break;
 
                }
                break;
 

+       case MG9:
+               /*
+                * More horribleness: the group 9 (0xF0 0xC7) instructions are
+                * allowed an optional prefix of 0x66 or 0xF3.  This is similar
+                * to the SIMD business described above, but with a different
+                * addressing mode (and an indirect table), so we deal with it
+                * separately (if similarly).
+                *
+                * Intel further complicated this with the release of Ivy Bridge
+                * where they overloaded these instructions based on the ModR/M
+                * bytes. The VMX instructions have a mode of 0 since they are
+                * memory instructions but rdrand instructions have a mode of
+                * 0b11 (REG_ONLY) because they only operate on registers. While
+                * there are different prefix formats, for now it is sufficient
+                * to use a single different table.
+                */
+
+               /*
+                * Calculate our offset in dis_op0FC7 (the group 9 table)
+                */
+               if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
+                       goto error;
+
+               off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
+                   sizeof (instable_t);
+
+               /*
+                * If we have a mode of 0b11 then we have to rewrite this.
+                */
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               if (mode == REG_ONLY) {
+                       dp = (instable_t *)&dis_op0FC7m3[off];
+                       break;
+               }
+
+               /*
+                * Rewrite if this instruction used one of the magic prefixes.
+                */
+               if (rep_prefix) {
+                       if (rep_prefix == 0xf3)
+                               dp = (instable_t *)&dis_opF30FC7[off];
+                       else
+                               goto error;
+                       rep_prefix = 0;
+               } else if (opnd_size_prefix) {
+                       dp = (instable_t *)&dis_op660FC7[off];
+                       opnd_size_prefix = 0;
+                       if (opnd_size == SIZE16)
+                               opnd_size = SIZE32;
+               }
+               break;
+
+

        case MMOSH:
                /*
                 * As with the "normal" SIMD instructions, the MMX
        case MMOSH:
                /*
                 * As with the "normal" SIMD instructions, the MMX


@@ -2390,7 +3674,10 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                if (LIT_STRNEQL(dp->it_name, "INVALID"))
                        goto error;
                (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
                if (LIT_STRNEQL(dp->it_name, "INVALID"))
                        goto error;
                (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);

-               if (dp->it_suffix) {
+               if (dp->it_avxsuf && dp->it_suffix) {
+                       (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
+                           OPLEN);
+               } else if (dp->it_suffix) {

                        char *types[] = {"", "w", "l", "q"};
                        if (opcode_bytes == 2 && opcode4 == 4) {
                                /* It's a cmovx.yy. Replace the suffix x */
                        char *types[] = {"", "w", "l", "q"};
                        if (opcode_bytes == 2 && opcode4 == 4) {
                                /* It's a cmovx.yy. Replace the suffix x */


@@ -2418,7 +3705,11 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
         * Process operands based on the addressing modes.
         */
        x->d86_mode = cpu_mode;
         * Process operands based on the addressing modes.
         */
        x->d86_mode = cpu_mode;

-       x->d86_rex_prefix = rex_prefix;
+       /*
+        * In vex mode the rex_prefix has no meaning
+        */
+       if (!vex_prefix)
+               x->d86_rex_prefix = rex_prefix;

        x->d86_opnd_size = opnd_size;
        x->d86_addr_size = addr_size;
        vbit = 0;               /* initialize for mem/reg -> reg */
        x->d86_opnd_size = opnd_size;
        x->d86_addr_size = addr_size;
        vbit = 0;               /* initialize for mem/reg -> reg */


@@ -2475,6 +3766,27 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
                        x->d86_opnd_size = opnd_size = SIZE16;
                dtrace_get_operand(x, mode, r_m, wbit, 0);
                break;
                        x->d86_opnd_size = opnd_size = SIZE16;
                dtrace_get_operand(x, mode, r_m, wbit, 0);
                break;

+       case MOVBE:
+               opnd_size = SIZE32;
+               if (rex_prefix & REX_W)
+                       opnd_size = SIZE64;
+               x->d86_opnd_size = opnd_size;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
+               wbit = WBIT(opcode7);
+               if (opnd_size_prefix)
+                       x->d86_opnd_size = opnd_size = SIZE16;
+               if (wbit) {
+                       /* reg -> mem */
+                       dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
+                       dtrace_get_operand(x, mode, r_m, wbit, 1);
+               } else {
+                       /* mem -> reg */
+                       dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
+                       dtrace_get_operand(x, mode, r_m, wbit, 0);
+               }
+               break;

 
        /*
         * imul instruction, with either 8-bit or longer immediate
 
        /*
         * imul instruction, with either 8-bit or longer immediate


@@ -2488,6 +3800,7 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
 
        /* memory or register operand to register, with 'w' bit */
        case MRw:
 
        /* memory or register operand to register, with 'w' bit */
        case MRw:

+       case ADX:

                wbit = WBIT(opcode2);
                STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
                break;
                wbit = WBIT(opcode2);
                STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
                break;


@@ -2670,15 +3983,22 @@ just_mem:
                dtrace_get_operand(x, mode, r_m, wbit, 0);
                break;
 
                dtrace_get_operand(x, mode, r_m, wbit, 0);
                break;
 

-       case SWAPGS:
+       case SWAPGS_RDTSCP:

                if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
 #ifdef DIS_TEXT
                        (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
                        x->d86_mnem[OPLEN - 1] = '\0';
                if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
 #ifdef DIS_TEXT
                        (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
                        x->d86_mnem[OPLEN - 1] = '\0';

+#endif
+                       NOMEM;
+                       break;
+               } else if (mode == 3 && r_m == 1) {
+#ifdef DIS_TEXT
+                       (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);

 #endif
                        NOMEM;
                        break;
                }
 #endif
                        NOMEM;
                        break;
                }

+

                /*FALLTHROUGH*/
 
        /* prefetch instruction - memory operand, but no memory acess */
                /*FALLTHROUGH*/
 
        /* prefetch instruction - memory operand, but no memory acess */


@@ -2688,6 +4008,7 @@ just_mem:
 
        /* single memory or register operand */
        case M:
 
        /* single memory or register operand */
        case M:

+       case MG9:

                wbit = LONG_OPND;
                goto just_mem;
 
                wbit = LONG_OPND;
                goto just_mem;
 


@@ -2696,6 +4017,76 @@ just_mem:
                wbit = BYTE_OPND;
                goto just_mem;
 
                wbit = BYTE_OPND;
                goto just_mem;
 

+       case VMx:
+               if (mode == 3) {
+#ifdef DIS_TEXT
+                       char *vminstr;
+
+                       switch (r_m) {
+                       case 1:
+                               vminstr = "vmcall";
+                               break;
+                       case 2:
+                               vminstr = "vmlaunch";
+                               break;
+                       case 3:
+                               vminstr = "vmresume";
+                               break;
+                       case 4:
+                               vminstr = "vmxoff";
+                               break;
+                       default:
+                               goto error;
+                       }
+
+                       (void) strncpy(x->d86_mnem, vminstr, OPLEN);
+#else
+                       if (r_m < 1 || r_m > 4)
+                               goto error;
+#endif
+
+                       NOMEM;
+                       break;
+               }
+               /*FALLTHROUGH*/
+       case SVM:
+               if (mode == 3) {
+#if DIS_TEXT
+                       char *vinstr;
+
+                       switch (r_m) {
+                       case 0:
+                               vinstr = "vmrun";
+                               break;
+                       case 1:
+                               vinstr = "vmmcall";
+                               break;
+                       case 2:
+                               vinstr = "vmload";
+                               break;
+                       case 3:
+                               vinstr = "vmsave";
+                               break;
+                       case 4:
+                               vinstr = "stgi";
+                               break;
+                       case 5:
+                               vinstr = "clgi";
+                               break;
+                       case 6:
+                               vinstr = "skinit";
+                               break;
+                       case 7:
+                               vinstr = "invlpga";
+                               break;
+                       }
+
+                       (void) strncpy(x->d86_mnem, vinstr, OPLEN);
+#endif
+                       NOMEM;
+                       break;
+               }
+               /*FALLTHROUGH*/

        case MONITOR_MWAIT:
                if (mode == 3) {
                        if (r_m == 0) {
        case MONITOR_MWAIT:
                if (mode == 3) {
                        if (r_m == 0) {


@@ -2709,6 +4100,18 @@ just_mem:
 #ifdef DIS_TEXT
                                (void) strncpy(x->d86_mnem, "mwait", OPLEN);
                                x->d86_mnem[OPLEN - 1] = '\0';
 #ifdef DIS_TEXT
                                (void) strncpy(x->d86_mnem, "mwait", OPLEN);
                                x->d86_mnem[OPLEN - 1] = '\0';

+#endif
+                               NOMEM;
+                               break;
+                       } else if (r_m == 2) {
+#ifdef DIS_TEXT
+                               (void) strncpy(x->d86_mnem, "clac", OPLEN);
+#endif
+                               NOMEM;
+                               break;
+                       } else if (r_m == 3) {
+#ifdef DIS_TEXT
+                               (void) strncpy(x->d86_mnem, "stac", OPLEN);

 #endif
                                NOMEM;
                                break;
 #endif
                                NOMEM;
                                break;


@@ -2717,7 +4120,26 @@ just_mem:
                        }
                }
                /*FALLTHROUGH*/
                        }
                }
                /*FALLTHROUGH*/

+       case XGETBV_XSETBV:
+               if (mode == 3) {
+                       if (r_m == 0) {
+#ifdef DIS_TEXT
+                               (void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
+#endif
+                               NOMEM;
+                               break;
+                       } else if (r_m == 1) {
+#ifdef DIS_TEXT
+                               (void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
+#endif
+                               NOMEM;
+                               break;
+                       } else {
+                               goto error;
+                       }

 
 

+               }
+               /*FALLTHROUGH*/

        case MO:
                /* Similar to M, but only memory (no direct registers) */
                wbit = LONG_OPND;
        case MO:
                /* Similar to M, but only memory (no direct registers) */
                wbit = LONG_OPND;


@@ -2810,11 +4232,14 @@ just_mem:
 
        /* memory or register operand to register */
        case MR:
 
        /* memory or register operand to register */
        case MR:

+               if (vex_prefetch)
+                       x->d86_got_modrm = 1;

                wbit = LONG_OPND;
                STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
                break;
 
        case RM:
                wbit = LONG_OPND;
                STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
                break;
 
        case RM:

+       case RM_66r:

                wbit = LONG_OPND;
                STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
                break;
                wbit = LONG_OPND;
                STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
                break;


@@ -2915,13 +4340,13 @@ xmmprm:
                 * movhps and movlhps behave similarly.
                 */
                if (mode == REG_ONLY) {
                 * movhps and movlhps behave similarly.
                 */
                if (mode == REG_ONLY) {

-                       if (LIT_STRNEQL(dp->it_name, "movlps"))
+                       if (LIT_STRNEQL(dp->it_name, "movlps")) {

                                (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
                                x->d86_mnem[OPLEN - 1] = '\0';
                                (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
                                x->d86_mnem[OPLEN - 1] = '\0';

-                       } else if (LIT_STRNEQL(dp->it_name, "movhps")) {
+                       } else if (strcmp(dp->it_name, "movhps") == 0) {

                                (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
                                x->d86_mnem[OPLEN - 1] = '\0';
                                (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
                                x->d86_mnem[OPLEN - 1] = '\0';

-               }
+                       }

                }
 #endif
                if (dp->it_adrmode == XMMXIMPL)
                }
 #endif
                if (dp->it_adrmode == XMMXIMPL)


@@ -2936,8 +4361,8 @@ xmmprm:
                dtrace_get_modrm(x, &mode, &reg, &r_m);
 #ifdef DIS_TEXT
                if ((LIT_STRNEQL(dp->it_name, "movlps") ||
                dtrace_get_modrm(x, &mode, &reg, &r_m);
 #ifdef DIS_TEXT
                if ((LIT_STRNEQL(dp->it_name, "movlps") ||

-                   LIT_STRNEQL(dp->it_name, "movhps") ||
-                   LIT_STRNEQL(dp->it_name, "movntps")) &&
+                    LIT_STRNEQL(dp->it_name, "movhps") ||
+                    LIT_STRNEQL(dp->it_name, "movntps")) &&

                    mode == REG_ONLY)
                        goto error;
 #endif
                    mode == REG_ONLY)
                        goto error;
 #endif


@@ -3313,7 +4738,7 @@ xmmprm:
 #else
                if (mode != REG_ONLY) {
                        dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
 #else
                if (mode != REG_ONLY) {
                        dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);

-                       dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
+                       dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);

                        NOMEM;
                }
 #endif
                        NOMEM;
                }
 #endif


@@ -3332,18 +4757,29 @@ xmmprm:
 
        case XMMFENCE:
                /*
 
        case XMMFENCE:
                /*

-                * Only the following exact byte sequences are allowed:
-                *
-                *      0f ae e8        lfence
-                *      0f ae f0        mfence
+                * XRSTOR and LFENCE share the same opcode but differ in mode

                 */
                 */

-               if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
-                   (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
-                       goto error;
+               dtrace_get_modrm(x, &mode, &reg, &r_m);

 
 

+               if (mode == REG_ONLY) {
+                       /*
+                        * Only the following exact byte sequences are allowed:
+                        *
+                        *      0f ae e8        lfence
+                        *      0f ae f0        mfence
+                        */
+                       if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
+                           (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
+                               goto error;
+               } else {
+#ifdef DIS_TEXT
+                       (void) strncpy(x->d86_mnem, "xrstor", OPLEN);
+#endif
+                       dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
+                       dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
+               }

                break;
 
                break;
 

-

        /* float reg */
        case F:
 #ifdef DIS_TEXT
        /* float reg */
        case F:
 #ifdef DIS_TEXT


@@ -3368,6 +4804,484 @@ xmmprm:
                NOMEM;
                break;
 
                NOMEM;
                break;
 

+       /* AVX instructions */
+       case VEX_MO:
+               /* op(ModR/M.r/m) */
+               x->d86_numopnds = 1;
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+#ifdef DIS_TEXT
+               if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
+                       (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
+#endif
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, mode, r_m, wbit, 0);
+               break;
+       case VEX_RMrX:
+       case FMA:
+               /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
+               x->d86_numopnds = 3;
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               /*
+                * In classic Intel fashion, the opcodes for all of the FMA
+                * instructions all have two possible mnemonics which vary by
+                * one letter, which is selected based on the value of the wbit.
+                * When wbit is one, they have the 'd' suffix and when 'wbit' is
+                * 0, they have the 's' suffix. Otherwise, the FMA instructions
+                * are all a standard VEX_RMrX.
+                */
+#ifdef DIS_TEXT
+               if (dp->it_adrmode == FMA) {
+                       size_t len = strlen(dp->it_name);
+                       (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
+                       if (len + 1 < OPLEN) {
+                               (void) strncpy(x->d86_mnem + len,
+                                   vex_W != 0 ? "d" : "s", OPLEN - len);
+                       }
+               }
+#endif
+
+               if (mode != REG_ONLY) {
+                       if ((dp == &dis_opAVXF20F[0x10]) ||
+                           (dp == &dis_opAVXF30F[0x10])) {
+                               /* vmovsd <m64>, <xmm> */
+                               /* or vmovss <m64>, <xmm> */
+                               x->d86_numopnds = 2;
+                               goto L_VEX_MX;
+                       }
+               }
+
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
+               /*
+                * VEX prefix uses the 1's complement form to encode the
+                * XMM/YMM regs
+                */
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
+
+               if ((dp == &dis_opAVXF20F[0x2A]) ||
+                   (dp == &dis_opAVXF30F[0x2A])) {
+                       /*
+                        * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
+                        * <xmm>, <xmm>
+                        */
+                       wbit = LONG_OPND;
+               }
+#ifdef DIS_TEXT
+               else if ((mode == REG_ONLY) &&
+                   (dp == &dis_opAVX0F[0x1][0x6])) {   /* vmovlhps */
+                       (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
+               } else if ((mode == REG_ONLY) &&
+                   (dp == &dis_opAVX0F[0x1][0x2])) {   /* vmovhlps */
+                       (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
+               }
+#endif
+               dtrace_get_operand(x, mode, r_m, wbit, 0);
+
+               break;
+
+       case VEX_VRMrX:
+               /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
+               x->d86_numopnds = 3;
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
+               /*
+                * VEX prefix uses the 1's complement form to encode the
+                * XMM/YMM regs
+                */
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
+
+               dtrace_get_operand(x, mode, r_m, wbit, 1);
+               break;
+
+       case VEX_SbVM:
+               /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
+               x->d86_numopnds = 3;
+               x->d86_vsib = 1;
+
+               /*
+                * All instructions that use VSIB are currently a mess. See the
+                * comment around the dis_gather_regs_t structure definition.
+                */
+
+               vreg = &dis_vgather[opcode2][vex_W][vex_L];
+
+#ifdef DIS_TEXT
+               (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
+               (void) strlcat(x->d86_mnem + strlen(dp->it_name),
+                   vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
+#endif
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
+               /*
+                * VEX prefix uses the 1's complement form to encode the
+                * XMM/YMM regs
+                */
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
+                   0);
+               dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
+               break;
+
+       case VEX_RRX:
+               /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               if (mode != REG_ONLY) {
+                       if ((dp == &dis_opAVXF20F[0x11]) ||
+                           (dp == &dis_opAVXF30F[0x11])) {
+                               /* vmovsd <xmm>, <m64> */
+                               /* or vmovss <xmm>, <m64> */
+                               x->d86_numopnds = 2;
+                               goto L_VEX_RM;
+                       }
+               }
+
+               dtrace_get_operand(x, mode, r_m, wbit, 2);
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
+               break;
+
+       case VEX_RMRX:
+               /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
+               x->d86_numopnds = 4;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
+               if (dp == &dis_opAVX660F3A[0x18]) {
+                       /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
+                       dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
+               } else if ((dp == &dis_opAVX660F3A[0x20]) ||
+                   (dp == & dis_opAVX660F[0xC4])) {
+                       /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
+                       /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
+                       dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
+               } else if (dp == &dis_opAVX660F3A[0x22]) {
+                       /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
+#ifdef DIS_TEXT
+                       if (vex_W)
+                               x->d86_mnem[6] = 'q';
+#endif
+                       dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
+               } else {
+                       dtrace_get_operand(x, mode, r_m, wbit, 1);
+               }
+
+               /* one byte immediate number */
+               dtrace_imm_opnd(x, wbit, 1, 0);
+
+               /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
+               if ((dp == &dis_opAVX660F3A[0x4A]) ||
+                   (dp == &dis_opAVX660F3A[0x4B]) ||
+                   (dp == &dis_opAVX660F3A[0x4C])) {
+#ifdef DIS_TEXT
+                       int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
+#endif
+                       x->d86_opnd[0].d86_mode = MODE_NONE;
+#ifdef DIS_TEXT
+                       if (vex_L)
+                               (void) strncpy(x->d86_opnd[0].d86_opnd,
+                                   dis_YMMREG[regnum], OPLEN);
+                       else
+                               (void) strncpy(x->d86_opnd[0].d86_opnd,
+                                   dis_XMMREG[regnum], OPLEN);
+#endif
+               }
+               break;
+
+       case VEX_MX:
+               /* ModR/M.reg := op(ModR/M.rm) */
+               x->d86_numopnds = 2;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+L_VEX_MX:
+
+               if ((dp == &dis_opAVXF20F[0xE6]) ||
+                   (dp == &dis_opAVX660F[0x5A]) ||
+                   (dp == &dis_opAVX660F[0xE6])) {
+                       /* vcvtpd2dq <ymm>, <xmm> */
+                       /* or vcvtpd2ps <ymm>, <xmm> */
+                       /* or vcvttpd2dq <ymm>, <xmm> */
+                       dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
+                       dtrace_get_operand(x, mode, r_m, wbit, 0);
+               } else if ((dp == &dis_opAVXF30F[0xE6]) ||
+                   (dp == &dis_opAVX0F[0x5][0xA]) ||
+                   (dp == &dis_opAVX660F38[0x13]) ||
+                   (dp == &dis_opAVX660F38[0x18]) ||
+                   (dp == &dis_opAVX660F38[0x19]) ||
+                   (dp == &dis_opAVX660F38[0x58]) ||
+                   (dp == &dis_opAVX660F38[0x78]) ||
+                   (dp == &dis_opAVX660F38[0x79]) ||
+                   (dp == &dis_opAVX660F38[0x59])) {
+                       /* vcvtdq2pd <xmm>, <ymm> */
+                       /* or vcvtps2pd <xmm>, <ymm> */
+                       /* or vcvtph2ps <xmm>, <ymm> */
+                       /* or vbroadcasts* <xmm>, <ymm> */
+                       dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+                       dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
+               } else if (dp == &dis_opAVX660F[0x6E]) {
+                       /* vmovd/q <reg/mem 32/64>, <xmm> */
+#ifdef DIS_TEXT
+                       if (vex_W)
+                               x->d86_mnem[4] = 'q';
+#endif
+                       dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+                       dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
+               } else {
+                       dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+                       dtrace_get_operand(x, mode, r_m, wbit, 0);
+               }
+
+               break;
+
+       case VEX_MXI:
+               /* ModR/M.reg := op(ModR/M.rm, imm8) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
+               dtrace_get_operand(x, mode, r_m, wbit, 1);
+
+               /* one byte immediate number */
+               dtrace_imm_opnd(x, wbit, 1, 0);
+               break;
+
+       case VEX_XXI:
+               /* VEX.vvvv := op(ModR/M.rm, imm8) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+#ifdef DIS_TEXT
+               (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
+                   OPLEN);
+#endif
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
+               dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
+
+               /* one byte immediate number */
+               dtrace_imm_opnd(x, wbit, 1, 0);
+               break;
+
+       case VEX_MR:
+               /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
+               if (dp == &dis_opAVX660F[0xC5]) {
+                       /* vpextrw <imm8>, <xmm>, <reg> */
+                       x->d86_numopnds = 2;
+                       vbit = 2;
+               } else {
+                       x->d86_numopnds = 2;
+                       vbit = 1;
+               }
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
+               dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
+
+               if (vbit == 2)
+                       dtrace_imm_opnd(x, wbit, 1, 0);
+
+               break;
+
+       case VEX_RRI:
+               /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
+               x->d86_numopnds = 2;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+               dtrace_get_operand(x, mode, r_m, wbit, 0);
+               break;
+
+       case VEX_RX:
+               /* ModR/M.rm := op(ModR/M.reg) */
+               /* vextractf128 || vcvtps2ph */
+               if (dp == &dis_opAVX660F3A[0x19] ||
+                   dp == &dis_opAVX660F3A[0x1d]) {
+                       x->d86_numopnds = 3;
+
+                       dtrace_get_modrm(x, &mode, &reg, &r_m);
+                       dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+                       dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
+                       dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+
+                       /* one byte immediate number */
+                       dtrace_imm_opnd(x, wbit, 1, 0);
+                       break;
+               }
+
+               x->d86_numopnds = 2;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, mode, r_m, wbit, 1);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
+               break;
+
+       case VEX_RR:
+               /* ModR/M.rm := op(ModR/M.reg) */
+               x->d86_numopnds = 2;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               if (dp == &dis_opAVX660F[0x7E]) {
+                       /* vmovd/q <reg/mem 32/64>, <xmm> */
+#ifdef DIS_TEXT
+                       if (vex_W)
+                               x->d86_mnem[4] = 'q';
+#endif
+                       dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
+               } else
+                       dtrace_get_operand(x, mode, r_m, wbit, 1);
+
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
+               break;
+
+       case VEX_RRi:
+               /* ModR/M.rm := op(ModR/M.reg, imm) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+#ifdef DIS_TEXT
+               if (dp == &dis_opAVX660F3A[0x16]) {
+                       /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
+                       if (vex_W)
+                               x->d86_mnem[6] = 'q';
+               }
+#endif
+               dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+
+               /* one byte immediate number */
+               dtrace_imm_opnd(x, wbit, 1, 0);
+               break;
+       case VEX_RIM:
+               /* ModR/M.rm := op(ModR/M.reg, imm) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+               /* one byte immediate number */
+               dtrace_imm_opnd(x, wbit, 1, 0);
+               break;
+
+       case VEX_RM:
+               /* ModR/M.rm := op(ModR/M.reg) */
+               if (dp == &dis_opAVX660F3A[0x17]) {     /* vextractps */
+                       x->d86_numopnds = 3;
+
+                       dtrace_get_modrm(x, &mode, &reg, &r_m);
+                       dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+                       dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
+                       dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
+                       /* one byte immediate number */
+                       dtrace_imm_opnd(x, wbit, 1, 0);
+                       break;
+               }
+               x->d86_numopnds = 2;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+L_VEX_RM:
+               vbit = 1;
+               dtrace_get_operand(x, mode, r_m, wbit, vbit);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
+
+               break;
+
+       case VEX_RRM:
+               /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, mode, r_m, wbit, 2);
+               /* VEX use the 1's complement form encode the XMM/YMM regs */
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
+               break;
+
+       case VEX_RMX:
+               /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
+               x->d86_numopnds = 3;
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+               dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
+               dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
+               break;
+
+       case VEX_NONE:
+#ifdef DIS_TEXT
+               if (vex_L)
+                       (void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
+#endif
+               break;
+       case BLS: {
+
+               /*
+                * The BLS instructions are VEX instructions that are based on
+                * VEX.0F38.F3; however, they are considered special group 17
+                * and like everything else, they use the bits in 3-5 of the
+                * MOD R/M to determine the sub instruction. Unlike many others
+                * like the VMX instructions, these are valid both for memory
+                * and register forms.
+                */
+
+               dtrace_get_modrm(x, &mode, &reg, &r_m);
+               dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
+
+               switch (reg) {
+               case 1:
+#ifdef DIS_TEXT
+                       blsinstr = "blsr";
+#endif
+                       break;
+               case 2:
+#ifdef DIS_TEXT
+                       blsinstr = "blsmsk";
+#endif
+                       break;
+               case 3:
+#ifdef DIS_TEXT
+                       blsinstr = "blsi";
+#endif
+                       break;
+               default:
+                       goto error;
+               }
+
+               x->d86_numopnds = 2;
+#ifdef DIS_TEXT
+               (void) strncpy(x->d86_mnem, blsinstr, OPLEN);
+#endif
+               dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
+               dtrace_get_operand(x, mode, r_m, wbit, 0);
+               break;
+       }

        /* an invalid op code */
        case AM:
        case DM:
        /* an invalid op code */
        case AM:
        case DM: