set_cr4(cr4 & ~CR4_PGE);
/* flush TLBs */
- flush_tlb();
+ flush_tlb_raw();
if (CACHE_CONTROL_PAT == cache_control_type) {
/* Change PA6 attribute field to WC */
/* flush all caches and TLBs a second time */
wbinvd();
- flush_tlb();
+ flush_tlb_raw();
/* restore normal cache mode */
set_cr0(cr0);
return KERN_NOT_SUPPORTED;
}
-
/* check memory type (GPF exception for undefined types) */
if ((type != MTRR_TYPE_UNCACHEABLE) &&
(type != MTRR_TYPE_WRITECOMBINE) &&