xnu-3789.70.16.tar.gz

[apple/xnu.git] / osfmk / i386 / mtrr.c

diff --git a/osfmk/i386/mtrr.c b/osfmk/i386/mtrr.c
index 9129f40c64f165a06bd008366ad5b28784f1f825..30df3db47345794cf8a11c6949c3b32d6e1cee74 100644 (file)
--- a/osfmk/i386/mtrr.c
+++ b/osfmk/i386/mtrr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2000-2011 Apple Computer, Inc. All rights reserved.
  *
  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
  * 
@@ -34,6 +34,7 @@
 #include <i386/mp.h>
 #include <i386/proc_reg.h>
 #include <i386/mtrr.h>
+#include <i386/machine_check.h>
 
 struct mtrr_var_range {
        uint64_t  base;         /* in IA32_MTRR_PHYSBASE format */
@@ -62,6 +63,7 @@ decl_simple_lock_data(static, mtrr_lock);
 #define MTRR_LOCK()    simple_lock(&mtrr_lock);
 #define MTRR_UNLOCK()  simple_unlock(&mtrr_lock);
 
+//#define MTRR_DEBUG 1
 #if    MTRR_DEBUG
 #define DBG(x...)      kprintf(x)
 #else
@@ -333,7 +335,7 @@ mtrr_update_action(void * cache_control_type)
                set_cr4(cr4 & ~CR4_PGE);
 
        /* flush TLBs */
-       flush_tlb();   
+       flush_tlb_raw();
 
        if (CACHE_CONTROL_PAT == cache_control_type) {
                /* Change PA6 attribute field to WC */
@@ -365,7 +367,7 @@ mtrr_update_action(void * cache_control_type)
 
        /* flush all caches and TLBs a second time */
        wbinvd();
-       flush_tlb();
+       flush_tlb_raw();
 
        /* restore normal cache mode */
        set_cr0(cr0);
@@ -486,7 +488,6 @@ mtrr_range_add(addr64_t address, uint64_t length, uint32_t type)
                return KERN_NOT_SUPPORTED;
        }
 
-
        /* check memory type (GPF exception for undefined types) */
        if ((type != MTRR_TYPE_UNCACHEABLE)  &&
            (type != MTRR_TYPE_WRITECOMBINE) &&