*
* @APPLE_LICENSE_HEADER_START@
*
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License"). You may not use this file except in compliance with the
- * License. Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
*
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this
+ * file.
+ *
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
*/
+
+#define __APPLE_API_PRIVATE
+
#include <cpus.h>
#include <mach_kdb.h>
#include <mach_kdp.h>
#include <ppc/asm.h>
#include <ppc/proc_reg.h>
#include <ppc/spec_reg.h>
+#include <machine/cpu_capabilities.h>
#include <mach/ppc/vm_param.h>
#include <assym.s>
-#define ptFilter 0
-#define ptVersion 4
-#define ptRevision 6
-#define ptFeatures 8
-#define ptInitRout 12
-#define ptRptdProc 16
-#define ptTempMax 20
-#define ptTempThr 24
-#define ptLineSize 28
-#define ptl1iSize 32
-#define ptl1dSize 36
-#define ptSize 40
+#define ptFilter 0
+#define ptVersion 4
+#define ptRevision 6
+#define ptFeatures 8
+#define ptCPUCap 12
+#define ptInitRout 16
+#define ptRptdProc 20
+#define ptTempMax 24
+#define ptTempThr 28
+#define ptLineSize 32
+#define ptl1iSize 36
+#define ptl1dSize 40
+#define ptSize 44
#define bootCPU 10
#define firstInit 9
#define firstBoot 8
-/* Defines for PVRs */
-#define PROCESSOR_VERSION_601 1
-#define PROCESSOR_VERSION_603 3
-#define PROCESSOR_VERSION_604 4
-#define PROCESSOR_VERSION_603e 6
-#define PROCESSOR_VERSION_750 8
-#define PROCESSOR_VERSION_750FX 0x7000 /* ? */
-#define PROCESSOR_VERSION_604e 9
-#define PROCESSOR_VERSION_604ev 10 /* ? */
-#define PROCESSOR_VERSION_7400 12 /* ? */
-#define PROCESSOR_VERSION_7410 0x800C /* ? */
-#define PROCESSOR_VERSION_7450 0x8000 /* ? */
-#define PROCESSOR_VERSION_7455 0x8001 /* ? */
-
/*
* Interrupt and bootup stack for initial processor
*/
#endif /* MACH_KDP || MACH_KDB */
+
/*
* All CPUs start here.
*
ori r20,r20,LOW_ADDR(fwdisplock) ; Get address of the firmware display lock
stw r19,0(r20) ; Make sure the lock is free
-allstart: mr r31,r3 ; Save away arguments
+allstart:
+ mr r31,r3 ; Save away arguments
+
+ crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
+
lis r23,hi16(EXT(per_proc_info)) ; Set base per_proc
ori r23,r23,lo16(EXT(per_proc_info)) ; Set base per_proc
donePVR: lwz r20,ptInitRout(r26) ; Grab the special init routine
mtlr r20 ; Setup to call the init
- bf firstInit,notFirst ; Not first boot, go...
+ bf firstBoot,notFirst ; Not first boot, go...
;
; The following code just does a general initialization of the features just
; We are just setting defaults. The specific initialization code will modify these
; if necessary.
;
+ lis r13,hi16(EXT(_cpu_capabilities)) ; Get the address of _cpu_capabilities
+ ori r13,r13,lo16(EXT(_cpu_capabilities))
+ lwz r17,ptCPUCap(r26) ; Get the default cpu capabilities
+ stw r17, 0(r13) ; Save the default value in _cpu_capabilities
lwz r17,ptFeatures(r26) ; Pick up the features
doOurInit:
mr. r20,r20 ; See if initialization routine
- crand firstBoot,bootCPU,firstInit ; Indicate if we are on the initial first processor startup
bnelrl ; Do the initialization
ori r17,r17,lo16(pfValid) ; Set the valid bit
stw r11,pfMSSCR0(r30) ; Save the MSSCR0 value
mfspr r11,msscr1 ; Get the msscr1 register
stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
+
blr ; Return...
i7400nb:
bne+ init745Xhl2 ; Yes...
rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
-init745Xhl2: lis r14,hi16(256*1024) ; Base L2 size
+init745Xhl2:
+ mfpvr r14 ; Get processor version
+ rlwinm r14,r14,16,16,31 ; Isolate processor version
+ cmpli cr0, r14, PROCESSOR_VERSION_7457
+ lis r14,hi16(512*1024) ; 512KB L2
+ beq init745Xhl2_2
+
+ lis r14,hi16(256*1024) ; Base L2 size
rlwinm r15,r13,22,12,13 ; Convert to 256k, 512k, or 768k
add r14,r14,r15 ; Add in minimum
-
+
+init745Xhl2_2:
stw r13,pfl2crOriginal(r30) ; Shadow the L2CR
stw r13,pfl2cr(r30) ; Shadow the L2CR
stw r14,pfl2Size(r30) ; Set the L2 size
stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
mfspr r11,pir ; Get the pir register
stw r11,pfBootConfig(r30) ; Save the BootConfig value
+
blr ; Return....
; .short ptVersion - Version code from PVR. Always start with 0 which is default
; .short ptRevision - Revision code from PVR. A zero value denotes the generic attributes if not specific
; .long ptFeatures - Available features
+; .long ptCPUCap - Default value for _cpu_capabilities
; .long ptInitRout - Initilization routine. Can modify any of the other attributes.
; .long ptRptdProc - Processor type reported
; .long ptTempMax - Maximum operating temprature
.align 2
processor_types:
-
-; 601 (generic)
-
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_601
- .short 0
- .long pfFloat | pfSMPcap | pfL1i | pfL1d
- .long 0
- .long CPU_SUBTYPE_POWERPC_ALL
- .long 0
- .long 0
- .long 32
- .long 32*1024
- .long 32*1024
-
-; 603 (generic)
-
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_603
- .short 0
- .long pfFloat | pfL1i | pfL1d
- .long 0
- .long CPU_SUBTYPE_POWERPC_603
- .long 0
- .long 0
- .long 32
- .long 32*1024
- .long 32*1024
-
-; 603e (generic)
-
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_603e
- .short 0
- .long pfFloat | pfL1i | pfL1d
- .long 0
- .long CPU_SUBTYPE_POWERPC_603e
- .long 0
- .long 0
- .long 32
- .long 32*1024
- .long 32*1024
-
-; 604 (generic)
-
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_604
- .short 0
- .long pfFloat | pfSMPcap | pfL1i | pfL1d
- .long 0
- .long CPU_SUBTYPE_POWERPC_604
- .long 0
- .long 0
- .long 32
- .long 32*1024
- .long 32*1024
-
-; 604e (generic)
-
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_604e
- .short 0
- .long pfFloat | pfSMPcap | pfL1i | pfL1d
- .long 0
- .long CPU_SUBTYPE_POWERPC_604e
- .long 0
- .long 0
- .long 32
- .long 32*1024
- .long 32*1024
-
-; 604ev (generic)
-
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_604ev
- .short 0
- .long pfFloat | pfSMPcap | pfL1i | pfL1d
- .long 0
- .long CPU_SUBTYPE_POWERPC_604e
- .long 0
- .long 0
- .long 32
- .long 32*1024
- .long 32*1024
-
; 750 (ver 2.2)
- .align 2
- .long 0xFFFFFFFF ; Exact match
- .short PROCESSOR_VERSION_750
- .short 0x4202
- .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
- .long init750
- .long CPU_SUBTYPE_POWERPC_750
- .long 105
- .long 90
- .long 32
- .long 32*1024
- .long 32*1024
+ .align 2
+ .long 0xFFFFFFFF ; Exact match
+ .short PROCESSOR_VERSION_750
+ .short 0x4202
+ .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
+ .long kCache32 | kHasGraphicsOps | kHasStfiwx
+ .long init750
+ .long CPU_SUBTYPE_POWERPC_750
+ .long 105
+ .long 90
+ .long 32
+ .long 32*1024
+ .long 32*1024
; 750CX (ver 2.x)
- .align 2
- .long 0xFFFF0F00 ; 2.x vers
- .short PROCESSOR_VERSION_750
- .short 0x0200
- .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
- .long init750CX
- .long CPU_SUBTYPE_POWERPC_750
- .long 105
- .long 90
- .long 32
- .long 32*1024
- .long 32*1024
+ .align 2
+ .long 0xFFFF0F00 ; 2.x vers
+ .short PROCESSOR_VERSION_750
+ .short 0x0200
+ .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
+ .long kCache32 | kHasGraphicsOps | kHasStfiwx
+ .long init750CX
+ .long CPU_SUBTYPE_POWERPC_750
+ .long 105
+ .long 90
+ .long 32
+ .long 32*1024
+ .long 32*1024
; 750 (generic)
.short PROCESSOR_VERSION_750
.short 0
.long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL2
+ .long kCache32 | kHasGraphicsOps | kHasStfiwx
.long init750
.long CPU_SUBTYPE_POWERPC_750
.long 105
; 750FX (ver 1.x)
- .align 2
- .long 0xFFFF0F00 ; 1.x vers
- .short PROCESSOR_VERSION_750FX
- .short 0x0100
- .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
- .long init750FX
- .long CPU_SUBTYPE_POWERPC_750
- .long 105
- .long 90
- .long 32
- .long 32*1024
- .long 32*1024
+ .align 2
+ .long 0xFFFF0F00 ; 1.x vers
+ .short PROCESSOR_VERSION_750FX
+ .short 0x0100
+ .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
+ .long kCache32 | kHasGraphicsOps | kHasStfiwx
+ .long init750FX
+ .long CPU_SUBTYPE_POWERPC_750
+ .long 105
+ .long 90
+ .long 32
+ .long 32*1024
+ .long 32*1024
; 750FX (generic)
- .align 2
- .long 0xFFFF0000 ; All revisions
- .short PROCESSOR_VERSION_750FX
- .short 0
- .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
- .long init750FXV2
- .long CPU_SUBTYPE_POWERPC_750
- .long 105
- .long 90
- .long 32
- .long 32*1024
- .long 32*1024
+ .align 2
+ .long 0xFFFF0000 ; All revisions
+ .short PROCESSOR_VERSION_750FX
+ .short 0
+ .long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
+ .long kCache32 | kHasGraphicsOps | kHasStfiwx
+ .long init750FXV2
+ .long CPU_SUBTYPE_POWERPC_750
+ .long 105
+ .long 90
+ .long 32
+ .long 32*1024
+ .long 32*1024
; 7400 (ver 2.0 - ver 2.7)
.short PROCESSOR_VERSION_7400
.short 0x0200
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7400v2_7
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.short PROCESSOR_VERSION_7400
.short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7400
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.short PROCESSOR_VERSION_7400
.short 0x1101
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7410
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.short PROCESSOR_VERSION_7410
.short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7410
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.short PROCESSOR_VERSION_7450
.short 0x0100
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.short PROCESSOR_VERSION_7450
.short 0x0200
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.short PROCESSOR_VERSION_7450
.short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.short PROCESSOR_VERSION_7455
.short 0x0100
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init745X
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.short PROCESSOR_VERSION_7455
.short 0x0200
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init745X
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.short PROCESSOR_VERSION_7455
.short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
+ .long init745X
+ .long CPU_SUBTYPE_POWERPC_7450
+ .long 105
+ .long 90
+ .long 32
+ .long 32*1024
+ .long 32*1024
+
+; 7457
+
+ .align 2
+ .long 0xFFFF0000 ; All other revisions
+ .short PROCESSOR_VERSION_7457
+ .short 0
+ .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long kHasAltivec | kCache32 | kDcbaAvailable | kDataStreamsRecommended | kDataStreamsAvailable | kHasGraphicsOps | kHasStfiwx
.long init745X
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.short 0
.short 0
.long pfFloat | pfL1i | pfL1d
+ .long kCache32 | kHasGraphicsOps | kHasStfiwx
.long 0
.long CPU_SUBTYPE_POWERPC_ALL
.long 105
projects / apple / xnu.git / blobdiff