xnu-344.21.73.tar.gz

[apple/xnu.git] / osfmk / ppc / misc_asm.s

diff --git a/osfmk/ppc/misc_asm.s b/osfmk/ppc/misc_asm.s
index f4668f2ef3ad900ca8f6a9232eda9b6f9698ab90..3d6c1974a86da29ba18128d9bee0f40ae6c6def0 100644 (file)
--- a/osfmk/ppc/misc_asm.s
+++ b/osfmk/ppc/misc_asm.s
@@ -3,19 +3,22 @@
  *
  * @APPLE_LICENSE_HEADER_START@
  * 
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License").  You may not use this file except in compliance with the
- * License.  Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
  * 
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this
+ * file.
+ * 
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.
  * 
  * @APPLE_LICENSE_HEADER_END@
  */
@@ -47,13 +50,13 @@ ENTRY(getrpc, TAG_NO_FRAME_USED)
 
 /* Mask and unmask interrupts at the processor level */        
 ENTRY(interrupt_disable, TAG_NO_FRAME_USED)
-       mfmsr   r0
-       rlwinm  r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1       ; Force floating point off
-       rlwinm  r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1     ; Force vectors off
-       rlwinm  r0,     r0,     0,      MSR_EE_BIT+1,   MSR_EE_BIT-1
-       mtmsr   r0
-       isync
-       blr
+                       lis             r8,hi16(MASK(MSR_VEC))                  ; Get the vector flag
+                       mfmsr   r0                                                              ; Save the MSR 
+                       ori             r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_FP))   ; Add the FP flag
+                       andc    r0,r0,r8                                                ; Clear VEC, FP, DR, and EE
+                       mtmsr   r0
+                       isync
+                       blr
 
 ENTRY(interrupt_enable, TAG_NO_FRAME_USED)
 
@@ -70,13 +73,13 @@ ENTRY(interrupt_enable, TAG_NO_FRAME_USED)
 
 /* Mask and unmask interrupts at the processor level */        
 ENTRY(db_interrupt_disable, TAG_NO_FRAME_USED)
-       mfmsr   r0
-       rlwinm  r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1       ; Force floating point off
-       rlwinm  r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1     ; Force vectors off
-       rlwinm  r0,     r0,     0,      MSR_EE_BIT+1,   MSR_EE_BIT-1
-       mtmsr   r0
-       isync
-       blr
+                       lis             r8,hi16(MASK(MSR_VEC))                  ; Get the vector flag
+                       mfmsr   r0                                                              ; Save the MSR 
+                       ori             r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_FP))   ; Add the FP flag
+                       andc    r0,r0,r8                                                ; Clear VEC, FP, DR, and EE
+                       mtmsr   r0
+                       isync
+                       blr
 
 ENTRY(db_interrupt_enable, TAG_NO_FRAME_USED)
        mfmsr   r0
@@ -92,11 +95,12 @@ ENTRY(db_interrupt_enable, TAG_NO_FRAME_USED)
  
 ENTRY(Call_Debugger, TAG_NO_FRAME_USED)
 
+
+                       lis             r8,hi16(MASK(MSR_VEC))                  ; Get the vector flag
                        mfmsr   r7                              ; Get the current MSR
-                       rlwinm  r7,r7,0,MSR_FP_BIT+1,MSR_FP_BIT-1       ; Force floating point off
-                       rlwinm  r7,r7,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1     ; Force vectors off
+                       ori             r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_FP))   ; Add the FP flag
                        mflr    r0                              ; Save the return
-                       rlwinm  r7,r7,0,MSR_EE_BIT+1,MSR_EE_BIT-1       ; Turn off interruptions
+                       andc    r7,r7,r8                                                ; Clear VEC and FP
                        mtmsr   r7                              ; Do it 
                        isync
                        mfsprg  r8,0                    ; Get the per_proc block
@@ -119,9 +123,11 @@ cdNewDeb:  li              r0,0                    ; Clear this out
                        
                        bl              EXT(Call_DebuggerC)     ; Call the "C" phase of this
                
-                       mfmsr   r0                              ; Get the MSR just in case it was enabled
+                       lis             r8,hi16(MASK(MSR_VEC))                  ; Get the vector flag
+                       mfmsr   r0                              ; Get the current MSR
+                       ori             r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_FP))   ; Add the FP flag
                        addi    r1,r1,FM_SIZE   ; Pop off first stack frame
-                       rlwinm  r0,r0,0,MSR_EE_BIT+1,MSR_EE_BIT-1       ; Turn off interruptions enable bit
+                       andc    r0,r0,r8                ; Turn off all the interesting stuff
                        mtmsr   r0
                
                        mfsprg  r8,0                    ; Get the per_proc block address
@@ -189,6 +195,10 @@ ENTRY(mtdec, TAG_NO_FRAME_USED)
        mtdec   ARG0
        blr
 
+ENTRY(cntlzw, TAG_NO_FRAME_USED)
+       cntlzw  r3,r3
+       blr
+
 /* Decrementer frequency and realtime|timebase processor registers
  * are different between ppc601 and ppc603/4, we define them all.
  */
@@ -288,3 +298,11 @@ ENTRY(mfsda, TAG_NO_FRAME_USED)
        mfspr   r3,sda
        blr
 
+       .globl  EXT(hid0get64)
+       
+LEXT(hid0get64)
+
+       mfspr   r4,hid0                                 ; Get the HID0
+       srdi    r3,r4,32                                ; Move top down
+       rlwinm  r4,r4,0,0,31                    ; Clean top
+       blr