*
* @APPLE_LICENSE_HEADER_START@
*
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License"). You may not use this file except in compliance with the
- * License. Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
*
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this
+ * file.
+ *
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
#include <ppc/machine_routines.h>
/* Per processor CPU features */
+#pragma pack(4) /* Make sure the structure stays as we defined it */
struct procFeatures {
- unsigned int Available;
+ unsigned int Available; /* 0x000 */
#define pfFloat 0x80000000
#define pfFloatb 0
#define pfAltivec 0x40000000
#define pfThermalb 7
#define pfThermInt 0x00800000
#define pfThermIntb 8
-#define pfNoL2PFNap 0x00008000
-#define pfNoL2PFNapb 16
-#define pfSlowNap 0x00004000
-#define pfSlowNapb 17
-#define pfNoMuMMCK 0x00002000
-#define pfNoMuMMCKb 18
+#define pfSlowNap 0x00400000
+#define pfSlowNapb 9
+#define pfNoMuMMCK 0x00200000
+#define pfNoMuMMCKb 10
+#define pfNoL2PFNap 0x00100000
+#define pfNoL2PFNapb 11
+#define pfSCOMFixUp 0x00080000
+#define pfSCOMFixUpb 12
+#define pfHasDcba 0x00040000
+#define pfHasDcbab 13
+#define pfL1fa 0x00010000
+#define pfL1fab 15
+#define pfL2 0x00008000
+#define pfL2b 16
+#define pfL2fa 0x00004000
+#define pfL2fab 17
+#define pfL2i 0x00002000
+#define pfL2ib 18
#define pfLClck 0x00001000
#define pfLClckb 19
#define pfWillNap 0x00000800
#define pfNoMSRirb 21
#define pfL3pdet 0x00000200
#define pfL3pdetb 22
-#define pfL1i 0x00000100
-#define pfL1ib 23
-#define pfL1d 0x00000080
-#define pfL1db 24
-#define pfL1fa 0x00000040
-#define pfL1fab 25
-#define pfL2 0x00000020
-#define pfL2b 26
-#define pfL2fa 0x00000010
-#define pfL2fab 27
-#define pfL2i 0x00000008
-#define pfL2ib 28
+#define pf128Byte 0x00000080
+#define pf128Byteb 24
+#define pf32Byte 0x00000020
+#define pf32Byteb 26
+#define pf64Bit 0x00000010
+#define pf64Bitb 27
#define pfL3 0x00000004
#define pfL3b 29
#define pfL3fa 0x00000002
#define pfL3fab 30
#define pfValid 0x00000001
#define pfValidb 31
- unsigned short rptdProc;
- unsigned short lineSize;
- unsigned int l1iSize;
- unsigned int l1dSize;
- unsigned int l2cr;
- unsigned int l2Size;
- unsigned int l3cr;
- unsigned int l3Size;
- unsigned int pfHID0;
- unsigned int pfHID1;
- unsigned int pfHID2;
- unsigned int pfHID3;
- unsigned int pfMSSCR0;
- unsigned int pfMSSCR1;
- unsigned int pfICTRL;
- unsigned int pfLDSTCR;
- unsigned int pfLDSTDB;
- unsigned int l2crOriginal;
- unsigned int l3crOriginal;
- unsigned int pfBootConfig;
- unsigned int reserved[4];
+ unsigned short rptdProc; /* 0x004 */
+ unsigned short lineSize; /* 0x006 */
+ unsigned int l1iSize; /* 0x008 */
+ unsigned int l1dSize; /* 0x00C */
+ unsigned int l2cr; /* 0x010 */
+ unsigned int l2Size; /* 0x014 */
+ unsigned int l3cr; /* 0x018 */
+ unsigned int l3Size; /* 0x01C */
+ unsigned int pfMSSCR0; /* 0x020 */
+ unsigned int pfMSSCR1; /* 0x024 */
+ unsigned int pfICTRL; /* 0x028 */
+ unsigned int pfLDSTCR; /* 0x02C */
+ unsigned int pfLDSTDB; /* 0x030 */
+ unsigned int pfMaxVAddr; /* 0x034 */
+ unsigned int pfMaxPAddr; /* 0x038 */
+ unsigned int pfPTEG; /* 0x03C */
+ uint64_t pfHID0; /* 0x040 */
+ uint64_t pfHID1; /* 0x048 */
+ uint64_t pfHID2; /* 0x050 */
+ uint64_t pfHID3; /* 0x058 */
+ uint64_t pfHID4; /* 0x060 */
+ uint64_t pfHID5; /* 0x068 */
+ unsigned int l2crOriginal; /* 0x070 */
+ unsigned int l3crOriginal; /* 0x074 */
+ unsigned int pfBootConfig; /* 0x07C */
+ unsigned int reserved[1]; /* 0x80 */
};
+#pragma pack()
typedef struct procFeatures procFeatures;
+#pragma pack(4) /* Make sure the structure stays as we defined it */
struct thrmControl {
unsigned int maxTemp; /* Maximum temprature before damage */
unsigned int throttleTemp; /* Temprature at which to throttle down */
unsigned int thrm3val; /* Value for thrm3 register */
unsigned int rsvd[3]; /* Pad to cache line */
};
+#pragma pack()
typedef struct thrmControl thrmControl;
+/*
+ *
+ * Various performance counters
+ */
+#pragma pack(4) /* Make sure the structure stays as we defined it */
+struct hwCtrs {
+
+ unsigned int hwInVains; /* In vain */
+ unsigned int hwResets; /* Reset */
+ unsigned int hwMachineChecks; /* Machine check */
+ unsigned int hwDSIs; /* DSIs */
+ unsigned int hwISIs; /* ISIs */
+ unsigned int hwExternals; /* Externals */
+ unsigned int hwAlignments; /* Alignment */
+ unsigned int hwPrograms; /* Program */
+ unsigned int hwFloatPointUnavailable; /* Floating point */
+ unsigned int hwDecrementers; /* Decrementer */
+ unsigned int hwIOErrors; /* I/O error */
+ unsigned int hwrsvd0; /* Reserved */
+ unsigned int hwSystemCalls; /* System call */
+ unsigned int hwTraces; /* Trace */
+ unsigned int hwFloatingPointAssists; /* Floating point assist */
+ unsigned int hwPerformanceMonitors; /* Performance monitor */
+ unsigned int hwAltivecs; /* VMX */
+ unsigned int hwrsvd1; /* Reserved */
+ unsigned int hwrsvd2; /* Reserved */
+ unsigned int hwrsvd3; /* Reserved */
+ unsigned int hwInstBreakpoints; /* Instruction breakpoint */
+ unsigned int hwSystemManagements; /* System management */
+ unsigned int hwAltivecAssists; /* Altivec Assist */
+ unsigned int hwThermal; /* Thermals */
+ unsigned int hwrsvd5; /* Reserved */
+ unsigned int hwrsvd6; /* Reserved */
+ unsigned int hwrsvd7; /* Reserved */
+ unsigned int hwrsvd8; /* Reserved */
+ unsigned int hwrsvd9; /* Reserved */
+ unsigned int hwrsvd10; /* Reserved */
+ unsigned int hwrsvd11; /* Reserved */
+ unsigned int hwrsvd12; /* Reserved */
+ unsigned int hwrsvd13; /* Reserved */
+ unsigned int hwTrace601; /* Trace */
+ unsigned int hwSIGPs; /* SIGP */
+ unsigned int hwPreemptions; /* Preemption */
+ unsigned int hwContextSwitchs; /* Context switch */
+ unsigned int hwShutdowns; /* Shutdowns */
+ unsigned int hwChokes; /* System ABENDs */
+ unsigned int hwDataSegments; /* Data Segment Interruptions */
+ unsigned int hwInstructionSegments; /* Instruction Segment Interruptions */
+ unsigned int hwSoftPatches; /* Soft Patch interruptions */
+ unsigned int hwMaintenances; /* Maintenance interruptions */
+ unsigned int hwInstrumentations; /* Instrumentation interruptions */
+ unsigned int hwrsvd14; /* Reswerved */
+/* 0x0B4 */
+
+ unsigned int hwspare0[17]; /* Reserved */
+ unsigned int hwRedrives; /* Number of redriven interrupts */
+ unsigned int hwSteals; /* PTE Steals */
+/* 0x100 */
+
+ unsigned int hwMckHang; /* ? */
+ unsigned int hwMckSLBPE; /* ? */
+ unsigned int hwMckTLBPE; /* ? */
+ unsigned int hwMckERCPE; /* ? */
+ unsigned int hwMckL1DPE; /* ? */
+ unsigned int hwMckL1TPE; /* ? */
+ unsigned int hwMckUE; /* ? */
+ unsigned int hwMckIUE; /* ? */
+ unsigned int hwMckIUEr; /* ? */
+ unsigned int hwMckDUE; /* ? */
+ unsigned int hwMckDTW; /* ? */
+ unsigned int hwMckUnk; /* ? */
+ unsigned int hwMckExt; /* ? */
+ unsigned int hwMckICachePE; /* ? */
+ unsigned int hwMckITagPE; /* ? */
+ unsigned int hwMckIEratPE; /* ? */
+ unsigned int hwMckDEratPE; /* ? */
+ unsigned int hwspare2[15]; /* Pad to next 128 bndry */
+/* 0x180 */
+
+ unsigned int napStamp[2]; /* Time base when we napped */
+ unsigned int napTotal[2]; /* Total nap time in ticks */
+ unsigned int numSIGPast; /* Number of SIGP asts recieved */
+ unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
+ unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
+ unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
+ unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
+ unsigned int numSIGPmast; /* Number of SIGPast messages merged */
+ unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
+
+ unsigned int hwspare3[21]; /* Pad to 512 */
+
+};
+#pragma pack()
+
+typedef struct hwCtrs hwCtrs;
+
+struct patch_entry {
+ unsigned int *addr;
+ unsigned int data;
+ unsigned int type;
+ unsigned int value;
+};
+
+typedef struct patch_entry patch_entry_t;
+
+#define PATCH_INVALID 0
+#define PATCH_PROCESSOR 1
+#define PATCH_FEATURE 2
+
+#define PATCH_TABLE_SIZE 12
+
+#define PatchExt32 0x80000000
+#define PatchExt32b 0
+#define PatchLwsync 0x40000000
+#define PatchLwsyncb 1
+
/* When an exception is taken, this info is accessed via sprg0 */
/* We should always have this one on a cache line boundary */
+
+#pragma pack(4) /* Make sure the structure stays as we defined it */
struct per_proc_info {
unsigned short cpu_number;
unsigned short cpu_flags; /* Various low-level flags */
vm_offset_t debstackptr;
vm_offset_t debstack_top_ss;
- unsigned int tempwork1; /* Temp work area - monitor use carefully */
- unsigned int save_exception_type;
+ unsigned int spcFlags; /* Special thread flags */
+ unsigned int Uassist; /* User Assist Word */
unsigned int old_thread;
/* PPC cache line boundary here - 020 */
- unsigned int active_kloaded; /* pointer to active_kloaded[CPU_NO] */
- unsigned int active_stacks; /* pointer to active_stacks[CPU_NO] */
+ unsigned int rsrvd020[2];
unsigned int need_ast; /* pointer to need_ast[CPU_NO] */
/*
* Note: the following two pairs of words need to stay in order and each pair must
* be in the same reservation (line) granule
*/
- struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
- unsigned int pprsv1;
- struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
- unsigned int pprsv2;
- unsigned int next_savearea; /* pointer to the next savearea */
+ struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
+ unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
+ struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
+ unsigned int holdQFret; /* Hold off releasing quickfret list */
+ unsigned int save_exception_type;
/* PPC cache line boundary here - 040 */
- unsigned int quickfret; /* List of saveareas to release */
- unsigned int lclfree; /* Pointer to local savearea list */
+ addr64_t quickfret; /* List of saveareas to release */
+ addr64_t lclfree; /* Pointer to local savearea list */
unsigned int lclfreecnt; /* Entries in local savearea list */
- unsigned int Lastpmap; /* Last user pmap loaded */
- unsigned int userspace; /* Last loaded user memory space ID */
- unsigned int userpmap; /* User pmap - real address */
- unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
- unsigned int spcFlags; /* Special thread flags */
+ unsigned int spcTRc; /* Special trace count */
+ unsigned int spcTRp; /* Special trace buffer pointer */
+ unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
/* PPC cache line boundary here - 060 */
boolean_t interrupts_enabled;
- unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
IOInterruptHandler interrupt_handler;
void * interrupt_nub;
unsigned int interrupt_source;
void * interrupt_target;
void * interrupt_refCon;
- time_base_enable_t time_base_enable;
+ uint64_t next_savearea; /* pointer to the next savearea */
/* PPC cache line boundary here - 080 */
unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
#define SIGPwake 3 /* Wake up a sleeping processor */
#define CPRQtemp 0 /* Get temprature of processor */
#define CPRQtimebase 1 /* Get timebase of processor */
+#define CPRQsegload 2 /* Segment registers reload */
+#define CPRQscom 3 /* SCOM */
+#define CPRQchud 4 /* CHUD perfmon */
unsigned int MPsigpParm0; /* SIGP parm 0 */
unsigned int MPsigpParm1; /* SIGP parm 1 */
unsigned int MPsigpParm2; /* SIGP parm 2 */
/* PPC cache line boundary here - 0A0 */
procFeatures pf; /* Processor features */
- /* PPC cache line boundary here - 100 */
- thrmControl thrm; /* Thermal controls */
-
/* PPC cache line boundary here - 120 */
- unsigned int napStamp[2]; /* Time base when we napped */
- unsigned int napTotal[2]; /* Total nap time in ticks */
- unsigned int numSIGPast; /* Number of SIGP asts recieved */
- unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
- unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
- unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
+ thrmControl thrm; /* Thermal controls */
/* PPC cache line boundary here - 140 */
- unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
- unsigned int numSIGPmast; /* Number of SIGPast messages merged */
- unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
- unsigned int spcTRc; /* Special trace count */
- unsigned int spcTRp; /* Special trace buffer pointer */
- unsigned int Uassist; /* User Assist Word */
- unsigned int rsrvd158[2]; /* Reserved slots */
+ unsigned int ppRsvd140[8]; /* Reserved */
/* PPC cache line boundary here - 160 */
+ time_base_enable_t time_base_enable;
+ unsigned int ppRsvd164[4]; /* Reserved */
cpu_data_t pp_cpu_data; /* cpu data info */
- unsigned int rsrvd170[4]; /* Reserved slots */
/* PPC cache line boundary here - 180 */
- unsigned int rsrvd180[8]; /* Reserved slots */
+ unsigned int ppRsvd180[2]; /* Reserved */
+ uint64_t validSegs; /* Valid SR/STB slots */
+ addr64_t ppUserPmap; /* Current user state pmap (physical address) */
+ unsigned int ppUserPmapVirt; /* Current user state pmap (virtual address) */
+ unsigned int ppMapFlags; /* Mapping flags */
/* PPC cache line boundary here - 1A0 */
- unsigned int rsrvd1A0[8]; /* Reserved slots */
+ unsigned short ppInvSeg; /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
+ unsigned short ppCurSeg; /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
+ unsigned int ppSegSteal; /* Count of segment slot steals */
+ ppnum_t VMMareaPhys; /* vmm state page physical addr */
+ unsigned int VMMXAFlgs; /* vmm extended flags */
+ unsigned int FAMintercept; /* vmm FAM Exceptions to intercept */
+ unsigned int rsrvd1B4[3]; /* Reserved slots */
/* PPC cache line boundary here - 1C0 */
- unsigned int rsrvd1C0[8]; /* Reserved slots */
+ unsigned int ppCIOmp[16]; /* Linkage mapping for copyin/out - 64 bytes */
+
+ /* PPC cache line boundary here - 200 */
+ uint64_t tempr0; /* temporary savearea */
+ uint64_t tempr1;
+ uint64_t tempr2;
+ uint64_t tempr3;
+
+ uint64_t tempr4;
+ uint64_t tempr5;
+ uint64_t tempr6;
+ uint64_t tempr7;
+
+ uint64_t tempr8;
+ uint64_t tempr9;
+ uint64_t tempr10;
+ uint64_t tempr11;
+
+ uint64_t tempr12;
+ uint64_t tempr13;
+ uint64_t tempr14;
+ uint64_t tempr15;
+
+ uint64_t tempr16;
+ uint64_t tempr17;
+ uint64_t tempr18;
+ uint64_t tempr19;
+
+ uint64_t tempr20;
+ uint64_t tempr21;
+ uint64_t tempr22;
+ uint64_t tempr23;
+
+ uint64_t tempr24;
+ uint64_t tempr25;
+ uint64_t tempr26;
+ uint64_t tempr27;
- /* PPC cache line boundary here - 1E0 */
+ uint64_t tempr28;
+ uint64_t tempr29;
+ uint64_t tempr30;
+ uint64_t tempr31;
+
+
+ /* PPC cache line boundary here - 300 */
double emfp0; /* Copies of floating point registers */
double emfp1; /* Used for emulation purposes */
double emfp2;
double emfp30;
double emfp31;
-/* - 2E0 */
+/* - 400 */
unsigned int emfpscr_pad;
unsigned int emfpscr;
unsigned int empadfp[6];
-/* - 300 */
+/* - 420 */
unsigned int emvr0[4]; /* Copies of vector registers used both */
unsigned int emvr1[4]; /* for full vector emulation or */
unsigned int emvr2[4]; /* as saveareas while assisting denorms */
unsigned int emvr31[4];
unsigned int emvscr[4];
unsigned int empadvr[4];
-/* - 520 */
+/* - 640 */
+/* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
+ addr64_t skipListPrev[28]; /* prev ptrs saved as side effect of calling mapSearchFull() */
+
+/* - 720 */
unsigned int patcharea[56];
-/* - 600 */
+/* - 800 */
+
+ hwCtrs hwCtr; /* Hardware exception counters */
+/* - A00 */
+
+ unsigned int pppadpage[384]; /* Pad to end of page */
+/* - 1000 */
+
};
-#define pp_active_thread pp_cpu_data.active_thread
#define pp_preemption_count pp_cpu_data.preemption_level
#define pp_simple_lock_count pp_cpu_data.simple_lock_count
#define pp_interrupt_level pp_cpu_data.interrupt_level
+#pragma pack()
+
extern struct per_proc_info per_proc_info[NCPUS];
+
extern char *trap_type[];
-#endif /* ndef ASSEMBLER */
-/* with this savearea should be redriven */
+#endif /* ndef ASSEMBLER */ /* with this savearea should be redriven */
/* cpu_flags defs */
#define SIGPactive 0x8000
#define turnEEon 0x2000
#define traceBE 0x1000 /* user mode BE tracing in enabled */
#define traceBEb 3 /* bit number for traceBE */
-#define BootDone 0x0100
+#define SleepState 0x0800
+#define SleepStateb 4
+#define mcountOff 0x0400
#define SignalReady 0x0200
+#define BootDone 0x0100
#define loadMSR 0x7FF4
#define T_VECTOR_SIZE 4 /* function pointer size */
#define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
#define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
#define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
-#define T_INVALID_EXCP13 (0x20 * T_VECTOR_SIZE)
+#define T_EMULATE (0x20 * T_VECTOR_SIZE)
#define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
#define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
#define T_CHOKE (0x26 * T_VECTOR_SIZE)
+#define T_DATA_SEGMENT (0x27 * T_VECTOR_SIZE)
+#define T_INSTRUCTION_SEGMENT (0x28 * T_VECTOR_SIZE)
+
+#define T_SOFT_PATCH (0x29 * T_VECTOR_SIZE)
+#define T_MAINTENANCE (0x2A * T_VECTOR_SIZE)
+#define T_INSTRUMENTATION (0x2B * T_VECTOR_SIZE)
+#define T_ARCHDEP0 (0x2C * T_VECTOR_SIZE)
+
#define T_AST (0x100 * T_VECTOR_SIZE)
#define T_MAX T_CHOKE /* Maximum exception no */
-#define EXCEPTION_VECTOR(exception) (exception * 0x100 /T_VECTOR_SIZE )
+#define T_FAM 0x00004000
+
+#define EXCEPTION_VECTOR(exception) (exception * 0x100 / T_VECTOR_SIZE )
/*
* System choke (failure) codes
#define failNoSavearea 4
#define failSaveareaCorr 5
#define failBadLiveContext 6
+#define failSkipLists 7
+#define failUnalignedStk 8
/* Always must be last - update failNames table in model_dep.c as well */
-#define failUnknown 7
+#define failUnknown 9
#ifndef ASSEMBLER
+#pragma pack(4) /* Make sure the structure stays as we defined it */
typedef struct resethandler {
unsigned int type;
vm_offset_t call_paddr;
vm_offset_t arg__paddr;
} resethandler_t;
+#pragma pack()
extern resethandler_t ResetHandler;
#define RESET_HANDLER_NULL 0x0
#define RESET_HANDLER_START 0x1
+#define RESET_HANDLER_BUPOR 0x2
+#define RESET_HANDLER_IGNORE 0x3
#endif /* _PPC_EXCEPTION_H_ */
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