/*
* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
*
- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License"). You may not use this file except in compliance with the
- * License. Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.
*
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
+ *
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.
*
- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
#ifndef _I386_FP_SAVE_H_
#define _I386_FP_SAVE_H_
-/*
- * Floating point registers and status, as saved
- * and restored by FP save/restore instructions.
- */
-struct i386_fp_save {
- unsigned short fp_control; /* control */
- unsigned short fp_unused_1;
- unsigned short fp_status; /* status */
- unsigned short fp_unused_2;
- unsigned short fp_tag; /* register tags */
- unsigned short fp_unused_3;
- unsigned int fp_eip; /* eip at failed instruction */
- unsigned short fp_cs; /* cs at failed instruction */
- unsigned short fp_opcode; /* opcode of failed instruction */
- unsigned int fp_dp; /* data address */
- unsigned short fp_ds; /* data segment */
- unsigned short fp_unused_4;
-};
+#ifdef MACH_KERNEL_PRIVATE
-struct i386_fp_regs {
- unsigned short fp_reg_word[5][8];
- /* space for 8 80-bit FP registers */
-};
-/* note when allocating this data structure, it must be 16 byte aligned. */
-struct i386_fx_save {
- unsigned short fx_control; /* control */
- unsigned short fx_status; /* status */
- unsigned char fx_tag; /* register tags */
- unsigned char fx_bbz1; /* better be zero when calling fxrtstor */
- unsigned short fx_opcode;
- unsigned int fx_eip; /* eip instruction */
- unsigned short fx_cs; /* cs instruction */
- unsigned short fx_bbz2; /* better be zero when calling fxrtstor */
- unsigned int fx_dp; /* data address */
- unsigned short fx_ds; /* data segment */
- unsigned short fx_bbz3; /* better be zero when calling fxrtstor */
- unsigned int fx_MXCSR;
- unsigned int fx_MXCSR_MASK;
- unsigned short fx_reg_word[8][8]; /* STx/MMx registers */
- unsigned short fx_XMM_reg[8][8]; /* XMM0-XMM7 */
- unsigned char fx_reserved[16*14]; /* reserved by intel for future expansion */
+struct x86_fx_thread_state {
+ unsigned short fx_control; /* control */
+ unsigned short fx_status; /* status */
+ unsigned char fx_tag; /* register tags */
+ unsigned char fx_bbz1; /* better be zero when calling fxrtstor */
+ unsigned short fx_opcode;
+ union {
+ struct { /* 32-bit layout: */
+ unsigned int fx_eip; /* eip instruction */
+ unsigned short fx_cs; /* cs instruction */
+ unsigned short fx_bbz2; /* better be zero when calling fxrtstor */
+ unsigned int fx_dp; /* data address */
+ unsigned short fx_ds; /* data segment */
+ unsigned short fx_bbz3; /* better be zero when calling fxrtstor */
+ };
+ struct { /* 64-bit layout: */
+ uint64_t fx_rip; /* instruction pointer */
+ uint64_t fx_rdp; /* data pointer */
+ };
+ };
+ unsigned int fx_MXCSR;
+ unsigned int fx_MXCSR_MASK;
+ unsigned short fx_reg_word[8][8]; /* STx/MMx registers */
+ unsigned short fx_XMM_reg[8][16]; /* XMM0-XMM15 on 64 bit processors */
+ /* XMM0-XMM7 on 32 bit processors... unused storage reserved */
+
+ unsigned char fx_reserved[16*5]; /* reserved by intel for future
+ * expansion */
+ unsigned int fp_valid;
+ unsigned int fp_save_layout;
+ unsigned char fx_pad[8];
+}__attribute__ ((packed));
+
+struct xsave_header {
+ uint64_t xstate_bv;
+ uint64_t xcomp_bv;
+ uint8_t xhrsvd[48];
};
+typedef struct { uint64_t lo64, hi64; }__attribute__ ((packed)) reg128_t;
+typedef struct { reg128_t lo128, hi128; }__attribute__ ((packed)) reg256_t;
+typedef struct { reg256_t lo256, hi256; }__attribute__ ((packed)) reg512_t;
+
+struct x86_avx_thread_state {
+ struct x86_fx_thread_state fp;
+ struct xsave_header _xh; /* Offset 512, xsave header */
+ reg128_t x_YMM_Hi128[16]; /* Offset 576, high YMMs `*/
+ /* Offset 832, end */
+}__attribute__ ((packed));
+
+struct x86_avx512_thread_state {
+ struct x86_fx_thread_state fp;
+ struct xsave_header _xh; /* Offset 512, xsave header */
+ reg128_t x_YMM_Hi128[16]; /* Offset 576, high YMMs */
+
+ uint64_t x_pad[16]; /* Offset 832, unused AMD LWP */
+ uint64_t x_BNDREGS[8]; /* Offset 960, unused MPX */
+ uint64_t x_BNDCTL[8]; /* Offset 1024, unused MPX */
+
+ uint64_t x_Opmask[8]; /* Offset 1088, K0-K7 */
+ reg256_t x_ZMM_Hi256[16]; /* Offset 1152, ZMM0..15[511:256] */
+ reg512_t x_Hi16_ZMM[16]; /* Offset 1664, ZMM16..31[511:0] */
+ /* Offset 2688, end */
+}__attribute__ ((packed));
+
+typedef union {
+ struct x86_fx_thread_state fx;
+ struct x86_avx_thread_state avx;
+#if !defined(RC_HIDE_XNU_J137)
+ struct x86_avx512_thread_state avx512;
+#endif
+} x86_ext_thread_state_t;
+
+#define EVEX_PREFIX 0x62 /* AVX512's EVEX vector operation prefix */
+#define VEX2_PREFIX 0xC5 /* VEX 2-byte prefix for Opmask instructions */
+#define VEX3_PREFIX 0xC4 /* VEX 3-byte prefix for Opmask instructions */
+#endif /* MACH_KERNEL_PRIVATE */
/*
* Control register
*/
projects / apple / xnu.git / blobdiff