xnu-1504.9.17.tar.gz

[apple/xnu.git] / osfmk / i386 / cpuid.h

diff --git a/osfmk/i386/cpuid.h b/osfmk/i386/cpuid.h
index 135ededc36f7ef0122995c6d47e9d11bf7c20c4a..ce8b2a3785fdc2c0973320a1be222e97199fa675 100644 (file)
--- a/osfmk/i386/cpuid.h
+++ b/osfmk/i386/cpuid.h
@@ -84,6 +84,8 @@
 #define CPUID_FEATURE_PBE     _Bit(31) /* Pend Break Enable */
 
 #define CPUID_FEATURE_SSE3    _HBit(0) /* Streaming SIMD extensions 3 */
 #define CPUID_FEATURE_PBE     _Bit(31) /* Pend Break Enable */
 
 #define CPUID_FEATURE_SSE3    _HBit(0) /* Streaming SIMD extensions 3 */

+#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ Instruction */
+

 #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
 #define CPUID_FEATURE_DSCPL   _HBit(4) /* Debug Store CPL */
 #define CPUID_FEATURE_VMX     _HBit(5) /* VMX */
 #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
 #define CPUID_FEATURE_DSCPL   _HBit(4) /* Debug Store CPL */
 #define CPUID_FEATURE_VMX     _HBit(5) /* VMX */


@@ -95,11 +97,13 @@
 #define CPUID_FEATURE_CX16    _HBit(13)        /* CmpXchg16b instruction */
 #define CPUID_FEATURE_xTPR    _HBit(14)        /* Send Task PRiority msgs */
 #define CPUID_FEATURE_PDCM    _HBit(15)        /* Perf/Debug Capability MSR */
 #define CPUID_FEATURE_CX16    _HBit(13)        /* CmpXchg16b instruction */
 #define CPUID_FEATURE_xTPR    _HBit(14)        /* Send Task PRiority msgs */
 #define CPUID_FEATURE_PDCM    _HBit(15)        /* Perf/Debug Capability MSR */

+

 #define CPUID_FEATURE_DCA     _HBit(18)        /* Direct Cache Access */
 #define CPUID_FEATURE_SSE4_1  _HBit(19)        /* Streaming SIMD extensions 4.1 */
 #define CPUID_FEATURE_SSE4_2  _HBit(20)        /* Streaming SIMD extensions 4.2 */
 #define CPUID_FEATURE_xAPIC   _HBit(21)        /* Extended APIC Mode */
 #define CPUID_FEATURE_POPCNT  _HBit(23)        /* POPCNT instruction */
 #define CPUID_FEATURE_DCA     _HBit(18)        /* Direct Cache Access */
 #define CPUID_FEATURE_SSE4_1  _HBit(19)        /* Streaming SIMD extensions 4.1 */
 #define CPUID_FEATURE_SSE4_2  _HBit(20)        /* Streaming SIMD extensions 4.2 */
 #define CPUID_FEATURE_xAPIC   _HBit(21)        /* Extended APIC Mode */
 #define CPUID_FEATURE_POPCNT  _HBit(23)        /* POPCNT instruction */

+#define CPUID_FEATURE_AES     _HBit(25)        /* AES instructions */

 #define CPUID_FEATURE_VMM     _HBit(31)        /* VMM (Hypervisor) present */
 
 /*
 #define CPUID_FEATURE_VMM     _HBit(31)        /* VMM (Hypervisor) present */
 
 /*


@@ -108,10 +112,12 @@
  */
 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)    /* SYSCALL/sysret */
 #define CPUID_EXTFEATURE_XD       _Bit(20)     /* eXecute Disable */
  */
 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)    /* SYSCALL/sysret */
 #define CPUID_EXTFEATURE_XD       _Bit(20)     /* eXecute Disable */

+
+#define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)     /* 1G-Byte Page support */

 #define CPUID_EXTFEATURE_RDTSCP           _Bit(27)     /* RDTSCP */
 #define CPUID_EXTFEATURE_EM64T    _Bit(29)     /* Extended Mem 64 Technology */
 
 #define CPUID_EXTFEATURE_RDTSCP           _Bit(27)     /* RDTSCP */
 #define CPUID_EXTFEATURE_EM64T    _Bit(29)     /* Extended Mem 64 Technology */
 

-#define CPUID_EXTFEATURE_LAHF     _HBit(20)    /* LAFH/SAHF instructions */
+#define CPUID_EXTFEATURE_LAHF     _HBit(0)     /* LAHF/SAHF instructions */

 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values


@@ -128,10 +134,12 @@
 #define CPUID_MODEL_MEROM      15
 #define CPUID_MODEL_PENRYN     23
 #define CPUID_MODEL_NEHALEM    26
 #define CPUID_MODEL_MEROM      15
 #define CPUID_MODEL_PENRYN     23
 #define CPUID_MODEL_NEHALEM    26

-#define CPUID_MODEL_ATOM       28

 #define CPUID_MODEL_FIELDS     30      /* Lynnfield, Clarksfield, Jasper */
 #define CPUID_MODEL_DALES      31      /* Havendale, Auburndale */
 #define CPUID_MODEL_NEHALEM_EX 46
 #define CPUID_MODEL_FIELDS     30      /* Lynnfield, Clarksfield, Jasper */
 #define CPUID_MODEL_DALES      31      /* Havendale, Auburndale */
 #define CPUID_MODEL_NEHALEM_EX 46

+#define CPUID_MODEL_DALES_32NM 37      /* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE   44      /* Gulftown, Westmere-EP, Westmere-WS */
+#define CPUID_MODEL_WESTMERE_EX        47

 
 #ifndef ASSEMBLER
 #include <stdint.h>
 
 #ifndef ASSEMBLER
 #include <stdint.h>


@@ -200,6 +208,7 @@ typedef struct {
 typedef struct {
        boolean_t       sensor;
        boolean_t       dynamic_acceleration;
 typedef struct {
        boolean_t       sensor;
        boolean_t       dynamic_acceleration;

+       boolean_t       invariant_APIC_timer;

        uint32_t        thresholds;
        boolean_t       ACNT_MCNT;
 } cpuid_thermal_leaf_t;
        uint32_t        thresholds;
        boolean_t       ACNT_MCNT;
 } cpuid_thermal_leaf_t;