xnu-792.25.20.tar.gz

[apple/xnu.git] / osfmk / i386 / commpage / cacheflush.s

diff --git a/osfmk/i386/commpage/cacheflush.s b/osfmk/i386/commpage/cacheflush.s
index 078494ec626d51317dc577a792aa98f392930557..876597fac1bad72bd5c919fed7fdb550c0bdc36f 100644 (file)
--- a/osfmk/i386/commpage/cacheflush.s
+++ b/osfmk/i386/commpage/cacheflush.s
@@ -1,5 +1,5 @@
 /*
 /*

- * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2003-2006 Apple Computer, Inc. All rights reserved.

  *
  * @APPLE_LICENSE_HEADER_START@
  * 
  *
  * @APPLE_LICENSE_HEADER_START@
  * 


@@ -20,19 +20,59 @@
  * @APPLE_LICENSE_HEADER_END@
  */
 
  * @APPLE_LICENSE_HEADER_END@
  */
 

-#include <sys/appleapiopts.h>

 #include <machine/cpu_capabilities.h>
 #include <machine/commpage.h>
 
         .text
         .align  2, 0x90
 
 #include <machine/cpu_capabilities.h>
 #include <machine/commpage.h>
 
         .text
         .align  2, 0x90
 

+// void sysFlushDcache( void *p, size_t len );
+// 32-bit version
+

 Lsys_flush_dcache:
 Lsys_flush_dcache:

+       movl    4(%esp),%ecx            // get length
+       movl    8(%esp),%edx            // get ptr
+       testl   %ecx,%ecx               // length 0?
+       jz      2f                      // yes
+       mfence                          // ensure previous stores make it to memory
+1:
+       clflush (%edx)                  // flush a line
+       addl    $64,%edx
+       subl    $64,%ecx
+       jnc     1b
+       mfence                          // make sure memory is updated before we return
+2:
+       ret
+
+       COMMPAGE_DESCRIPTOR(sys_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,kCache64,0)
+
+
+// void sysFlushDcache( void *p, size_t len );
+// 64-bit version
+       .code64
+Lsys_flush_dcache_64:                  // %rdi = ptr,  %rsi = length
+       testq   %rsi,%rsi               // length 0?
+       jz      2f                      // yes
+       mfence                          // ensure previous stores make it to memory
+1:
+       clflush (%rdi)                  // flush a line
+       addq    $64,%rdi
+       subq    $64,%rsi
+       jnc     1b
+       mfence                          // make sure memory is updated before we return
+2:

        ret
        ret

+       .code32
+       COMMPAGE_DESCRIPTOR(sys_flush_dcache_64,_COMM_PAGE_FLUSH_DCACHE,kCache64,0)
+

 
 

-       COMMPAGE_DESCRIPTOR(sys_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0)
+// void sysIcacheInvalidate( void *p, size_t len );

 
 Lsys_icache_invalidate:
 
 Lsys_icache_invalidate:

+       // This is a NOP on intel processors, since the intent of the API
+       // is to make data executable, and Intel L1Is are coherent with L1D.
+       // We can use same routine both in 32 and 64-bit mode, since it is
+       // just a RET instruction.

        ret
 
        COMMPAGE_DESCRIPTOR(sys_icache_invalidate,_COMM_PAGE_FLUSH_ICACHE,0,0)
        ret
 
        COMMPAGE_DESCRIPTOR(sys_icache_invalidate,_COMM_PAGE_FLUSH_ICACHE,0,0)