-#define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
-#define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
-#define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
-#define ARM_PTE_IS_COMPRESSED(x) \
- ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
- ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
- ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
- (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
- &(x), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
-
-#define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
-#define ARM_PTE_TYPE 0x00000002 /* small page entry type */
-#define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
-
-#define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
-#define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
-
-#define ARM_PTE_SHSHIFT 10
-#define ARM_PTE_SH_MASK 0x00000400 /* shared (SMP) mapping mask */
-#define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
-
-#define ARM_PTE_CBSHIFT 2
-#define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
-#define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
-
-#define ARM_PTE_AP0SHIFT 4
-#define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
-#define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
-
-#define ARM_PTE_AP1SHIFT 5
-#define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
-#define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
-
-#define ARM_PTE_AP2SHIFT 9
-#define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
-#define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
-
- /* access protections */
-#define ARM_PTE_AP(ap) ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) \
- | ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
-
- /* mask access protections */
-#define ARM_PTE_APMASK (ARM_PTE_AP1_MASK \
- | ARM_PTE_AP2_MASK)
-
-#define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
-#define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
-
-#define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
-#define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
-
-#define ARM_PTE_NXSHIFT 0
-#define ARM_PTE_NX 0x00000001 /* small page no execute */
-#define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
-
-#define ARM_PTE_PNXSHIFT 0
-#define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
-#define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
-
-#define ARM_PTE_TEX0SHIFT 6
-#define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
-#define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
-
-#define ARM_PTE_TEX1SHIFT 7
-#define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
-#define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
-
-#define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
-#define ARM_PTE_WRITEABLE ARM_PTE_TEX1
-#define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
-
-#define ARM_PTE_TEX2SHIFT 8
-#define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
-#define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
-
-#define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
-#define ARM_PTE_WIRED ARM_PTE_TEX2
-#define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
-
- /* mask memory attributes index */
-#define ARM_PTE_ATTRINDX(indx) ((((indx)&0x3)<<ARM_PTE_CBSHIFT) \
- | ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
-
- /* mask memory attributes index */
-#define ARM_PTE_ATTRINDXMASK (ARM_PTE_CB_MASK \
- | ARM_PTE_TEX0_MASK)
-
-#define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
-#define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
-#define ARM_SECTION_SIZE (1024*1024) /* 1MB */
-#define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
-
+#define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
+#define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
+#define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
+#define ARM_PTE_IS_COMPRESSED(x, p) \
+ ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
+ ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
+ ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
+ (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
+ (p), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
+
+#define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
+#define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */
+
+#define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */
+
+#define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
+#define ARM_PTE_TYPE_VALID 0x00000002 /* valid L2 entry */
+#define ARM_PTE_TYPE 0x00000002 /* small page entry type */
+#define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
+
+#define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
+#define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
+
+#define ARM_PTE_SHSHIFT 10
+#define ARM_PTE_SHMASK 0x00000400 /* shared (SMP) mapping mask */
+#define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
+
+#define ARM_PTE_CBSHIFT 2
+#define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
+#define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
+
+#define ARM_PTE_AP0SHIFT 4
+#define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
+#define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
+
+#define ARM_PTE_AP1SHIFT 5
+#define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
+#define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
+
+#define ARM_PTE_AP2SHIFT 9
+#define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
+#define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
+
+/* access protections */
+#define ARM_PTE_AP(ap) \
+ ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) | \
+ ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
+
+/* mask access protections */
+#define ARM_PTE_APMASK \
+ (ARM_PTE_AP1_MASK | ARM_PTE_AP2_MASK)
+
+#define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
+#define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
+
+#define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
+#define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
+
+#define ARM_PTE_NXSHIFT 0
+#define ARM_PTE_NX 0x00000001 /* small page no execute */
+#define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
+
+#define ARM_PTE_PNXSHIFT 0
+#define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
+#define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
+
+#define ARM_PTE_TEX0SHIFT 6
+#define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
+#define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
+
+#define ARM_PTE_TEX1SHIFT 7
+#define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
+#define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
+
+#define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
+#define ARM_PTE_WRITEABLE ARM_PTE_TEX1
+#define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
+
+#define ARM_PTE_TEX2SHIFT 8
+#define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
+#define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
+
+#define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
+#define ARM_PTE_WIRED ARM_PTE_TEX2
+#define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
+
+/* mask memory attributes index */
+#define ARM_PTE_ATTRINDX(indx) \
+ ((((indx)&0x3)<<ARM_PTE_CBSHIFT) | \
+ ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
+
+/* mask memory attributes index */
+#define ARM_PTE_ATTRINDXMASK \
+ (ARM_PTE_CB_MASK | ARM_PTE_TEX0_MASK)
+
+#define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
+#define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
+#define ARM_SECTION_SIZE (1024*1024) /* 1MB */
+#define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
+
+#define TLBI_ADDR_SHIFT (12)
+#define TLBI_ADDR_SIZE (20)
+#define TLBI_ADDR_MASK (((1ULL << TLBI_ADDR_SIZE) - 1))
+#define TLBI_ASID_SHIFT (0)
+#define TLBI_ASID_SIZE (8)
+#define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1))
projects / apple / xnu.git / blobdiff