- scc_write_reg(regs, chan, 3, SCC_WR3_RX_8_BITS|SCC_WR3_RX_ENABLE); /* (TEST/DEBUG) */
- sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE; /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 1, sr->wr1); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 15, SCC_WR15_ENABLE_ESCC); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 7, SCC_WR7P_RX_FIFO); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 9, SCC_WR9_MASTER_IE|SCC_WR9_NV); /* (TEST/DEBUG) */
- scc_read_reg_zero(regs, 0, bits); /* (TEST/DEBUG) */
- sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE; /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 1, sr->wr1); /* (TEST/DEBUG) */
- scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR); /* (TEST/DEBUG) */
- simple_unlock(&scc_stomp); /* (TEST/DEBUG) */
- splx(s); /* (TEST/DEBUG) */
- return 0; /* (TEST/DEBUG) */
+ scc_write_reg(regs, chan, 3, SCC_WR3_RX_8_BITS|SCC_WR3_RX_ENABLE);
+ sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE;
+ scc_write_reg(regs, chan, 1, sr->wr1);
+ scc_write_reg(regs, chan, 15, SCC_WR15_ENABLE_ESCC);
+ scc_write_reg(regs, chan, 7, SCC_WR7P_RX_FIFO);
+ scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR);
+ scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP);
+ scc_write_reg(regs, chan, 0, SCC_RESET_EXT_IP);
+ scc_write_reg(regs, chan, 9, SCC_WR9_MASTER_IE|SCC_WR9_NV);
+ scc_read_reg_zero(regs, 0, bits);
+ sr->wr1 = SCC_WR1_RXI_FIRST_CHAR | SCC_WR1_EXT_IE;
+ scc_write_reg(regs, chan, 1, sr->wr1);
+ scc_write_reg(regs, chan, 0, SCC_IE_NEXT_CHAR);
+ simple_unlock(&scc_stomp);
+ splx(s);
+ return 0;