/*
* CR4
*/
+#define CR4_SEE 0x00008000 /* Secure Enclave Enable XXX */
+#define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Protect */
#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execute Protect */
#define CR4_OSXSAVE 0x00040000 /* OS supports XSAVE */
#define CR4_PCIDE 0x00020000 /* PCID Enable */
/*
* XCR0 - XFEATURE_ENABLED_MASK (a.k.a. XFEM) register
*/
-#define XCR0_YMM 0x0000000000000004ULL /* YMM state available */
-#define XFEM_YMM XCR0_YMM
-#define XCR0_SSE 0x0000000000000002ULL /* SSE supported by XSAVE/XRESTORE */
-#define XCR0_X87 0x0000000000000001ULL /* x87, FPU/MMX (always set) */
-#define XFEM_SSE XCR0_SSE
-#define XFEM_X87 XCR0_X87
+#define XCR0_X87 (1ULL << 0) /* x87, FPU/MMX (always set) */
+#define XCR0_SSE (1ULL << 1) /* SSE supported by XSAVE/XRESTORE */
+#define XCR0_YMM (1ULL << 2) /* YMM state available */
+#define XCR0_BNDREGS (1ULL << 3) /* MPX Bounds register state */
+#define XCR0_BNDCSR (1ULL << 4) /* MPX Bounds configuration/state */
+#if !defined(RC_HIDE_XNU_J137)
+#define XCR0_OPMASK (1ULL << 5) /* Opmask register state */
+#define XCR0_ZMM_HI256 (1ULL << 6) /* ZMM upper 256-bit state */
+#define XCR0_HI16_ZMM (1ULL << 7) /* ZMM16..ZMM31 512-bit state */
+#endif /* not RC_HIDE_XNU_J137 */
+#define XFEM_X87 XCR0_X87
+#define XFEM_SSE XCR0_SSE
+#define XFEM_YMM XCR0_YMM
+#define XFEM_BNDREGS XCR0_BNDREGS
+#define XFEM_BNDCSR XCR0_BNDCSR
+#if !defined(XNU_HODE_J137)
+#define XFEM_OPMASK XCR0_OPMASK
+#define XFEM_ZMM_HI256 XCR0_ZMM_HI256
+#define XFEM_HI16_ZMM XCR0_HI16_ZMM
+#define XFEM_ZMM (XFEM_ZMM_HI256 | XFEM_HI16_ZMM | XFEM_OPMASK)
+#endif /* not XNU_HODE_J137 */
#define XCR0 (0)
#define PMAP_PCID_PRESERVE (1ULL << 63)
#define PMAP_PCID_MASK (0xFFF)
-#define RDRAND_RAX .byte 0x48, 0x0f, 0xc7, 0xf0
+/*
+ * If thread groups are needed for x86, set this to 1
+ */
+#define CONFIG_THREAD_GROUPS 0
#ifndef ASSEMBLER
static inline uintptr_t get_cr3_raw(void)
{
- register uintptr_t cr3;
+ uintptr_t cr3;
__asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
return(cr3);
}
static inline uintptr_t get_cr3_base(void)
{
- register uintptr_t cr3;
+ uintptr_t cr3;
__asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
return(cr3 & ~(0xFFFULL));
}
-static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint32_t preserve)
+static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint64_t preserve)
{
- __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( ( (uint64_t)preserve) << 63) ) );
+ __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( (preserve) << 63) ) );
}
static inline uintptr_t get_cr4(void)
__asm__ volatile("swapgs");
}
+static inline void hlt(void)
+{
+ __asm__ volatile("hlt");
+}
+
#ifdef MACH_KERNEL_PRIVATE
static inline void flush_tlb_raw(void)
{
- set_cr3_raw(get_cr3_raw());
+ uintptr_t cr4 = get_cr4();
+ if (cr4 & CR4_PGE) {
+ set_cr4(cr4 & ~CR4_PGE);
+ set_cr4(cr4 | CR4_PGE);
+ } else {
+ set_cr3_raw(get_cr3_raw());
+ }
}
extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
__asm__ volatile("invlpg (%0)" :: "r" (addr) : "memory");
}
+static inline void clac(void)
+{
+ __asm__ volatile("clac");
+}
+
+static inline void stac(void)
+{
+ __asm__ volatile("stac");
+}
+
/*
* Access to machine-specific registers (available on 586 and better only)
* Note: the rd* operations modify the parameters directly (without using
#define rdtsc(lo,hi) \
__asm__ volatile("lfence; rdtsc; lfence" : "=a" (lo), "=d" (hi))
+#define rdtsc_nofence(lo,hi) \
+ __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi))
+
#define write_tsc(lo,hi) wrmsr(0x10, lo, hi)
#define rdpmc(counter,lo,hi) \
#define mfence() do_mfence()
#endif
+#ifdef __LP64__
static inline uint64_t rdpmc64(uint32_t pmc)
{
uint32_t lo=0, hi=0;
: "ecx");
return ((hi) << 32) | (lo);
}
-
+#endif /* __LP64__ */
/*
* rdmsr_carefully() returns 0 when the MSR has been read successfully,
#define MSR_IA32_PERFCTR0 0xc1
#define MSR_IA32_PERFCTR1 0xc2
+#define MSR_IA32_PERFCTR3 0xc3
+#define MSR_IA32_PERFCTR4 0xc4
#define MSR_PLATFORM_INFO 0xce
#define MSR_IA32_EVNTSEL0 0x186
#define MSR_IA32_EVNTSEL1 0x187
+#define MSR_IA32_EVNTSEL2 0x188
+#define MSR_IA32_EVNTSEL3 0x189
#define MSR_FLEX_RATIO 0x194
#define MSR_IA32_PERF_STS 0x198
#define MSR_IA32_MC0_ADDR 0x402
#define MSR_IA32_MC0_MISC 0x403
-#define MSR_IA32_VMX_BASE 0x480
-#define MSR_IA32_VMX_BASIC MSR_IA32_VMX_BASE
-#define MSR_IA32_VMXPINBASED_CTLS MSR_IA32_VMX_BASE+1
-#define MSR_IA32_PROCBASED_CTLS MSR_IA32_VMX_BASE+2
-#define MSR_IA32_VMX_EXIT_CTLS MSR_IA32_VMX_BASE+3
-#define MSR_IA32_VMX_ENTRY_CTLS MSR_IA32_VMX_BASE+4
-#define MSR_IA32_VMX_MISC MSR_IA32_VMX_BASE+5
-#define MSR_IA32_VMX_CR0_FIXED0 MSR_IA32_VMX_BASE+6
-#define MSR_IA32_VMX_CR0_FIXED1 MSR_IA32_VMX_BASE+7
-#define MSR_IA32_VMX_CR4_FIXED0 MSR_IA32_VMX_BASE+8
-#define MSR_IA32_VMX_CR4_FIXED1 MSR_IA32_VMX_BASE+9
+#define MSR_IA32_VMX_BASE 0x480
+#define MSR_IA32_VMX_BASIC MSR_IA32_VMX_BASE
+#define MSR_IA32_VMX_PINBASED_CTLS MSR_IA32_VMX_BASE+1
+#define MSR_IA32_VMX_PROCBASED_CTLS MSR_IA32_VMX_BASE+2
+#define MSR_IA32_VMX_EXIT_CTLS MSR_IA32_VMX_BASE+3
+#define MSR_IA32_VMX_ENTRY_CTLS MSR_IA32_VMX_BASE+4
+#define MSR_IA32_VMX_MISC MSR_IA32_VMX_BASE+5
+#define MSR_IA32_VMX_CR0_FIXED0 MSR_IA32_VMX_BASE+6
+#define MSR_IA32_VMX_CR0_FIXED1 MSR_IA32_VMX_BASE+7
+#define MSR_IA32_VMX_CR4_FIXED0 MSR_IA32_VMX_BASE+8
+#define MSR_IA32_VMX_CR4_FIXED1 MSR_IA32_VMX_BASE+9
+#define MSR_IA32_VMX_VMCS_ENUM MSR_IA32_VMX_BASE+10
+#define MSR_IA32_VMX_PROCBASED_CTLS2 MSR_IA32_VMX_BASE+11
+#define MSR_IA32_VMX_EPT_VPID_CAP MSR_IA32_VMX_BASE+12
+#define MSR_IA32_VMX_EPT_VPID_CAP_AD_SHIFT 21
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS MSR_IA32_VMX_BASE+13
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS MSR_IA32_VMX_BASE+14
+#define MSR_IA32_VMX_TRUE_VMEXIT_CTLS MSR_IA32_VMX_BASE+15
+#define MSR_IA32_VMX_TRUE_VMENTRY_CTLS MSR_IA32_VMX_BASE+16
+#define MSR_IA32_VMX_VMFUNC MSR_IA32_VMX_BASE+17
#define MSR_IA32_DS_AREA 0x600
#define MSR_IA32_PP0_ENERGY_STATUS 0x639
#define MSR_IA32_PP1_ENERGY_STATUS 0x641
+#define MSR_IA32_IA_PERF_LIMIT_REASONS_SKL 0x64F
+
#define MSR_IA32_IA_PERF_LIMIT_REASONS 0x690
#define MSR_IA32_GT_PERF_LIMIT_REASONS 0x6B0
#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
#define MSR_IA32_TSC_AUX 0xC0000103
+#define HV_VMX_EPTP_MEMORY_TYPE_UC 0x0
+#define HV_VMX_EPTP_MEMORY_TYPE_WB 0x6
+#define HV_VMX_EPTP_WALK_LENGTH(wl) (0ULL | ((((wl) - 1) & 0x7) << 3))
+#define HV_VMX_EPTP_ENABLE_AD_FLAGS (1ULL << 6)
+
#endif /* _I386_PROC_REG_H_ */
projects / apple / xnu.git / blobdiff