xnu-4570.1.46.tar.gz

[apple/xnu.git] / osfmk / i386 / cpuid.c

diff --git a/osfmk/i386/cpuid.c b/osfmk/i386/cpuid.c
index 090da7d76f1ad66c01623598d501afeef1314dbb..0ebd786b5ff3f10f4276e1ac44cf89a366145968 100644 (file)
--- a/osfmk/i386/cpuid.c
+++ b/osfmk/i386/cpuid.c
@@ -28,7 +28,6 @@
 /*
  * @OSF_COPYRIGHT@
  */
 /*
  * @OSF_COPYRIGHT@
  */

-#include <platforms.h>

 #include <vm/vm_page.h>
 #include <pexpert/pexpert.h>
 
 #include <vm/vm_page.h>
 #include <pexpert/pexpert.h>
 


@@ -362,6 +361,12 @@ cpuid_set_cache_info( i386_cpu_info_t * info_p )
                         */
                        if (type == L2U)
                                info_p->cpuid_cache_L2_associativity = cache_associativity;
                         */
                        if (type == L2U)
                                info_p->cpuid_cache_L2_associativity = cache_associativity;

+            /*
+             * Adjust #sets to account for the N CBos
+             * This is because addresses are hashed across CBos
+             */
+            if (type == L3U && info_p->core_count)
+                cache_sets = cache_sets / info_p->core_count;

 
                        /* Compute the number of page colors for this cache,
                         * which is:
 
                        /* Compute the number of page colors for this cache,
                         * which is:


@@ -695,18 +700,31 @@ cpuid_set_generic_info(i386_cpu_info_t *info_p)
        }
 
        if (info_p->cpuid_max_basic >= 0xd) {
        }
 
        if (info_p->cpuid_max_basic >= 0xd) {

-               cpuid_xsave_leaf_t      *xsp = &info_p->cpuid_xsave_leaf;
+               cpuid_xsave_leaf_t      *xsp;

                /*
                 * XSAVE Features:
                 */
                /*
                 * XSAVE Features:
                 */

-               cpuid_fn(0xd, info_p->cpuid_xsave_leaf.extended_state);
+               xsp = &info_p->cpuid_xsave_leaf[0];

                info_p->cpuid_xsave_leafp = xsp;
                info_p->cpuid_xsave_leafp = xsp;

+               xsp->extended_state[eax] = 0xd;
+               xsp->extended_state[ecx] = 0;
+               cpuid(xsp->extended_state);
+               DBG(" XSAVE Main leaf:\n");
+               DBG("  EAX           : 0x%x\n", xsp->extended_state[eax]);
+               DBG("  EBX           : 0x%x\n", xsp->extended_state[ebx]);
+               DBG("  ECX           : 0x%x\n", xsp->extended_state[ecx]);
+               DBG("  EDX           : 0x%x\n", xsp->extended_state[edx]);

 
 

-               DBG(" XSAVE Leaf:\n");
+               xsp = &info_p->cpuid_xsave_leaf[1];
+               xsp->extended_state[eax] = 0xd;
+               xsp->extended_state[ecx] = 1;
+               cpuid(xsp->extended_state);
+               DBG(" XSAVE Sub-leaf1:\n");

                DBG("  EAX           : 0x%x\n", xsp->extended_state[eax]);
                DBG("  EBX           : 0x%x\n", xsp->extended_state[ebx]);
                DBG("  ECX           : 0x%x\n", xsp->extended_state[ecx]);
                DBG("  EDX           : 0x%x\n", xsp->extended_state[edx]);
                DBG("  EAX           : 0x%x\n", xsp->extended_state[eax]);
                DBG("  EBX           : 0x%x\n", xsp->extended_state[ebx]);
                DBG("  ECX           : 0x%x\n", xsp->extended_state[ecx]);
                DBG("  EDX           : 0x%x\n", xsp->extended_state[edx]);

+

        }
 
        if (info_p->cpuid_model >= CPUID_MODEL_IVYBRIDGE) {
        }
 
        if (info_p->cpuid_model >= CPUID_MODEL_IVYBRIDGE) {


@@ -714,10 +732,24 @@ cpuid_set_generic_info(i386_cpu_info_t *info_p)
                 * Leaf7 Features:
                 */
                cpuid_fn(0x7, reg);
                 * Leaf7 Features:
                 */
                cpuid_fn(0x7, reg);

-               info_p->cpuid_leaf7_features = reg[ebx];
+               info_p->cpuid_leaf7_features = quad(reg[ecx], reg[ebx]);

 
                DBG(" Feature Leaf7:\n");
                DBG("  EBX           : 0x%x\n", reg[ebx]);
 
                DBG(" Feature Leaf7:\n");
                DBG("  EBX           : 0x%x\n", reg[ebx]);

+               DBG("  ECX           : 0x%x\n", reg[ecx]);
+       }
+
+       if (info_p->cpuid_max_basic >= 0x15) {
+               /*
+                * TCS/CCC frequency leaf:
+                */
+               cpuid_fn(0x15, reg);
+               info_p->cpuid_tsc_leaf.denominator = reg[eax];
+               info_p->cpuid_tsc_leaf.numerator   = reg[ebx];
+
+               DBG(" TSC/CCC Information Leaf:\n");
+               DBG("  numerator     : 0x%x\n", reg[ebx]);
+               DBG("  denominator   : 0x%x\n", reg[eax]);

        }
 
        return;
        }
 
        return;


@@ -731,9 +763,6 @@ cpuid_set_cpufamily(i386_cpu_info_t *info_p)
        switch (info_p->cpuid_family) {
        case 6:
                switch (info_p->cpuid_model) {
        switch (info_p->cpuid_family) {
        case 6:
                switch (info_p->cpuid_model) {

-               case 15:
-                       cpufamily = CPUFAMILY_INTEL_MEROM;
-                       break;

                case 23:
                        cpufamily = CPUFAMILY_INTEL_PENRYN;
                        break;
                case 23:
                        cpufamily = CPUFAMILY_INTEL_PENRYN;
                        break;


@@ -753,13 +782,30 @@ cpuid_set_cpufamily(i386_cpu_info_t *info_p)
                        cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE;
                        break;
                case CPUID_MODEL_IVYBRIDGE:
                        cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE;
                        break;
                case CPUID_MODEL_IVYBRIDGE:

+               case CPUID_MODEL_IVYBRIDGE_EP:

                        cpufamily = CPUFAMILY_INTEL_IVYBRIDGE;
                        break;
                case CPUID_MODEL_HASWELL:
                        cpufamily = CPUFAMILY_INTEL_IVYBRIDGE;
                        break;
                case CPUID_MODEL_HASWELL:

+               case CPUID_MODEL_HASWELL_EP:

                case CPUID_MODEL_HASWELL_ULT:
                case CPUID_MODEL_CRYSTALWELL:
                        cpufamily = CPUFAMILY_INTEL_HASWELL;
                        break;
                case CPUID_MODEL_HASWELL_ULT:
                case CPUID_MODEL_CRYSTALWELL:
                        cpufamily = CPUFAMILY_INTEL_HASWELL;
                        break;

+               case CPUID_MODEL_BROADWELL:
+               case CPUID_MODEL_BRYSTALWELL:
+                       cpufamily = CPUFAMILY_INTEL_BROADWELL;
+                       break;
+               case CPUID_MODEL_SKYLAKE:
+               case CPUID_MODEL_SKYLAKE_DT:
+#if !defined(RC_HIDE_XNU_J137)
+               case CPUID_MODEL_SKYLAKE_W:
+#endif
+                       cpufamily = CPUFAMILY_INTEL_SKYLAKE;
+                       break;
+               case CPUID_MODEL_KABYLAKE:
+               case CPUID_MODEL_KABYLAKE_DT:
+                       cpufamily = CPUFAMILY_INTEL_KABYLAKE;
+                       break;

                }
                break;
        }
                }
                break;
        }


@@ -776,6 +822,7 @@ void
 cpuid_set_info(void)
 {
        i386_cpu_info_t         *info_p = &cpuid_cpu_info;
 cpuid_set_info(void)
 {
        i386_cpu_info_t         *info_p = &cpuid_cpu_info;

+       boolean_t               enable_x86_64h = TRUE;

 
        cpuid_set_generic_info(info_p);
 
 
        cpuid_set_generic_info(info_p);
 


@@ -787,26 +834,48 @@ cpuid_set_info(void)
                panic("Unsupported CPU");
 
        info_p->cpuid_cpu_type = CPU_TYPE_X86;
                panic("Unsupported CPU");
 
        info_p->cpuid_cpu_type = CPU_TYPE_X86;

-       info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
-       /* Must be invoked after set_generic_info */
-       cpuid_set_cache_info(info_p);
+
+       if (!PE_parse_boot_argn("-enable_x86_64h", &enable_x86_64h, sizeof(enable_x86_64h))) {
+               boolean_t               disable_x86_64h = FALSE;
+
+               if (PE_parse_boot_argn("-disable_x86_64h", &disable_x86_64h, sizeof(disable_x86_64h))) {
+                       enable_x86_64h = FALSE;
+               }
+       }
+
+       if (enable_x86_64h &&
+           ((info_p->cpuid_features & CPUID_X86_64_H_FEATURE_SUBSET) == CPUID_X86_64_H_FEATURE_SUBSET) &&
+           ((info_p->cpuid_extfeatures & CPUID_X86_64_H_EXTFEATURE_SUBSET) == CPUID_X86_64_H_EXTFEATURE_SUBSET) &&
+           ((info_p->cpuid_leaf7_features & CPUID_X86_64_H_LEAF7_FEATURE_SUBSET) == CPUID_X86_64_H_LEAF7_FEATURE_SUBSET)) {
+               info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_64_H;
+       } else {
+               info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
+       }
+       /* cpuid_set_cache_info must be invoked after set_generic_info */
+
+       if (info_p->cpuid_cpufamily == CPUFAMILY_INTEL_PENRYN)
+               cpuid_set_cache_info(info_p);

 
        /*
         * Find the number of enabled cores and threads
         * (which determines whether SMT/Hyperthreading is active).
         */
        switch (info_p->cpuid_cpufamily) {
 
        /*
         * Find the number of enabled cores and threads
         * (which determines whether SMT/Hyperthreading is active).
         */
        switch (info_p->cpuid_cpufamily) {

+       case CPUFAMILY_INTEL_PENRYN:
+               info_p->core_count   = info_p->cpuid_cores_per_package;
+               info_p->thread_count = info_p->cpuid_logical_per_package;
+               break;

        case CPUFAMILY_INTEL_WESTMERE: {
                uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
                info_p->core_count   = bitfield32((uint32_t)msr, 19, 16);
                info_p->thread_count = bitfield32((uint32_t)msr, 15,  0);
                break;
                }
        case CPUFAMILY_INTEL_WESTMERE: {
                uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
                info_p->core_count   = bitfield32((uint32_t)msr, 19, 16);
                info_p->thread_count = bitfield32((uint32_t)msr, 15,  0);
                break;
                }

-       case CPUFAMILY_INTEL_HASWELL:
-       case CPUFAMILY_INTEL_IVYBRIDGE:
-       case CPUFAMILY_INTEL_SANDYBRIDGE:
-       case CPUFAMILY_INTEL_NEHALEM: {
+       default: {

                uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
                uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);

+               if (msr == 0)
+                       /* Provide a non-zero default for some VMMs */
+                       msr = (1 << 16) + 1;

                info_p->core_count   = bitfield32((uint32_t)msr, 31, 16);
                info_p->thread_count = bitfield32((uint32_t)msr, 15,  0);
                break;
                info_p->core_count   = bitfield32((uint32_t)msr, 31, 16);
                info_p->thread_count = bitfield32((uint32_t)msr, 15,  0);
                break;


@@ -816,9 +885,15 @@ cpuid_set_info(void)
                info_p->core_count   = info_p->cpuid_cores_per_package;
                info_p->thread_count = info_p->cpuid_logical_per_package;
        }
                info_p->core_count   = info_p->cpuid_cores_per_package;
                info_p->thread_count = info_p->cpuid_logical_per_package;
        }

+
+       if (info_p->cpuid_cpufamily != CPUFAMILY_INTEL_PENRYN)
+               cpuid_set_cache_info(info_p);
+

        DBG("cpuid_set_info():\n");
        DBG("  core_count   : %d\n", info_p->core_count);
        DBG("  thread_count : %d\n", info_p->thread_count);
        DBG("cpuid_set_info():\n");
        DBG("  core_count   : %d\n", info_p->core_count);
        DBG("  thread_count : %d\n", info_p->thread_count);

+       DBG("       cpu_type: 0x%08x\n", info_p->cpuid_cpu_type);
+       DBG("    cpu_subtype: 0x%08x\n", info_p->cpuid_cpu_subtype);

 
        info_p->cpuid_model_string = ""; /* deprecated */
 }
 
        info_p->cpuid_model_string = ""; /* deprecated */
 }


@@ -894,6 +969,8 @@ extfeature_map[] = {
        {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"},
        {CPUID_EXTFEATURE_EM64T,   "EM64T"},
        {CPUID_EXTFEATURE_LAHF,    "LAHF"},
        {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"},
        {CPUID_EXTFEATURE_EM64T,   "EM64T"},
        {CPUID_EXTFEATURE_LAHF,    "LAHF"},

+       {CPUID_EXTFEATURE_LZCNT,   "LZCNT"},
+       {CPUID_EXTFEATURE_PREFETCHW, "PREFETCHW"},

        {CPUID_EXTFEATURE_RDTSCP,  "RDTSCP"},
        {CPUID_EXTFEATURE_TSCI,    "TSCI"},
        {0, 0}
        {CPUID_EXTFEATURE_RDTSCP,  "RDTSCP"},
        {CPUID_EXTFEATURE_TSCI,    "TSCI"},
        {0, 0}


@@ -901,7 +978,7 @@ extfeature_map[] = {
 },
 leaf7_feature_map[] = {
        {CPUID_LEAF7_FEATURE_SMEP,     "SMEP"},
 },
 leaf7_feature_map[] = {
        {CPUID_LEAF7_FEATURE_SMEP,     "SMEP"},

-       {CPUID_LEAF7_FEATURE_ENFSTRG,  "ENFSTRG"},
+       {CPUID_LEAF7_FEATURE_ERMS,     "ERMS"},

        {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"},
        {CPUID_LEAF7_FEATURE_TSCOFF,   "TSC_THREAD_OFFSET"},
        {CPUID_LEAF7_FEATURE_BMI1,     "BMI1"},
        {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"},
        {CPUID_LEAF7_FEATURE_TSCOFF,   "TSC_THREAD_OFFSET"},
        {CPUID_LEAF7_FEATURE_BMI1,     "BMI1"},


@@ -910,6 +987,26 @@ leaf7_feature_map[] = {
        {CPUID_LEAF7_FEATURE_BMI2,     "BMI2"},
        {CPUID_LEAF7_FEATURE_INVPCID,  "INVPCID"},
        {CPUID_LEAF7_FEATURE_RTM,      "RTM"},
        {CPUID_LEAF7_FEATURE_BMI2,     "BMI2"},
        {CPUID_LEAF7_FEATURE_INVPCID,  "INVPCID"},
        {CPUID_LEAF7_FEATURE_RTM,      "RTM"},

+       {CPUID_LEAF7_FEATURE_SMAP,     "SMAP"},
+       {CPUID_LEAF7_FEATURE_RDSEED,   "RDSEED"},
+       {CPUID_LEAF7_FEATURE_ADX,      "ADX"},
+       {CPUID_LEAF7_FEATURE_IPT,      "IPT"},
+#if !defined(RC_HIDE_XNU_J137)
+       {CPUID_LEAF7_FEATURE_AVX512F,  "AVX512F"},
+       {CPUID_LEAF7_FEATURE_AVX512CD, "AVX512CD"},     
+       {CPUID_LEAF7_FEATURE_AVX512DQ, "AVX512DQ"},
+       {CPUID_LEAF7_FEATURE_AVX512BW, "AVX512BW"},
+       {CPUID_LEAF7_FEATURE_AVX512VL, "AVX512VL"},
+       {CPUID_LEAF7_FEATURE_AVX512IFMA, "AVX512IFMA"},
+       {CPUID_LEAF7_FEATURE_AVX512VBMI, "AVX512VBMI"},
+#endif /* not RC_HIDE_XNU_J137 */
+       {CPUID_LEAF7_FEATURE_SGX,      "SGX"},
+       {CPUID_LEAF7_FEATURE_PQM,      "PQM"},
+       {CPUID_LEAF7_FEATURE_FPU_CSDS, "FPU_CSDS"},
+       {CPUID_LEAF7_FEATURE_MPX,      "MPX"},
+       {CPUID_LEAF7_FEATURE_PQE,      "PQE"},
+       {CPUID_LEAF7_FEATURE_CLFSOPT,  "CLFSOPT"},
+       {CPUID_LEAF7_FEATURE_SHA,      "SHA"},

        {0, 0}
 };
 
        {0, 0}
 };
 


@@ -969,7 +1066,7 @@ void
 cpuid_feature_display(
        const char      *header)
 {
 cpuid_feature_display(
        const char      *header)
 {

-       char    buf[256];
+       char    buf[320];

 
        kprintf("%s: %s", header,
                 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));
 
        kprintf("%s: %s", header,
                 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));


@@ -1095,6 +1192,9 @@ cpuid_init_vmm_info(i386_vmm_info_t *info_p)
        if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_VMWARE)) {
                /* VMware identification string: kb.vmware.com/kb/1009458 */
                info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_VMWARE;
        if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_VMWARE)) {
                /* VMware identification string: kb.vmware.com/kb/1009458 */
                info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_VMWARE;

+       } else if (0 == strcmp(info_p->cpuid_vmm_vendor, CPUID_VMM_ID_PARALLELS)) {
+               /* Parallels identification string */
+               info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_PARALLELS;

        } else {
                info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_UNKNOWN;
        }
        } else {
                info_p->cpuid_vmm_family = CPUID_VMM_FAMILY_UNKNOWN;
        }