-#define INTEL_PTE_VALID 0x00000001ULL
-#define INTEL_PTE_WRITE 0x00000002ULL
-#define INTEL_PTE_RW 0x00000002ULL
-#define INTEL_PTE_USER 0x00000004ULL
-#define INTEL_PTE_WTHRU 0x00000008ULL
-#define INTEL_PTE_NCACHE 0x00000010ULL
-#define INTEL_PTE_REF 0x00000020ULL
-#define INTEL_PTE_MOD 0x00000040ULL
-#define INTEL_PTE_PS 0x00000080ULL
-#define INTEL_PTE_PTA 0x00000080ULL
-#define INTEL_PTE_GLOBAL 0x00000100ULL
-#define INTEL_PTE_WIRED 0x00000400ULL
-#define INTEL_PDPTE_NESTED 0x00000800ULL
-#define INTEL_PTE_PFN PG_FRAME
-
-#define INTEL_PTE_NX (1ULL << 63)
+#define INTEL_PTE_VALID 0x00000001ULL
+
+#define INTEL_PTE_WRITE 0x00000002ULL
+#define INTEL_PTE_RW 0x00000002ULL
+
+#define INTEL_PTE_USER 0x00000004ULL
+
+#define INTEL_PTE_WTHRU 0x00000008ULL
+#define INTEL_PTE_NCACHE 0x00000010ULL
+
+#define INTEL_PTE_REF 0x00000020ULL
+#define INTEL_PTE_MOD 0x00000040ULL
+
+#define INTEL_PTE_PS 0x00000080ULL
+#define INTEL_PTE_PAT 0x00000080ULL
+
+#define INTEL_PTE_GLOBAL 0x00000100ULL
+
+/* These markers use software available bits ignored by the
+ * processor's 4-level and EPT pagetable walkers.
+ * N.B.: WIRED was originally bit 10, but that conflicts with
+ * execute permissions for EPT entries iff mode-based execute controls
+ * are enabled.
+ */
+#define INTEL_PTE_SWLOCK (0x1ULL << 52)
+#define INTEL_PDPTE_NESTED (0x1ULL << 53)
+#define INTEL_PTE_WIRED (0x1ULL << 54)
+/* TODO: Compressed markers, potential conflict with protection keys? */
+#define INTEL_PTE_COMPRESSED_ALT (1ULL << 61) /* compressed but with "alternate accounting" */
+#define INTEL_PTE_COMPRESSED (1ULL << 62) /* marker, for invalid PTE only -- ignored by hardware for both regular/EPT entries*/
+
+#define INTEL_PTE_PFN PG_FRAME
+/* TODO: these should be internal definitions */
+#define INTEL_PTE_NX (1ULL << 63)