xnu-4570.71.2.tar.gz

[apple/xnu.git] / osfmk / i386 / proc_reg.h

diff --git a/osfmk/i386/proc_reg.h b/osfmk/i386/proc_reg.h
index b9fcb252beadec778f57d5be745dec3e8e37f3b9..530f9e61c7fac099d5384eda721e13fcaaeec50d 100644 (file)
--- a/osfmk/i386/proc_reg.h
+++ b/osfmk/i386/proc_reg.h
@@ -173,16 +173,32 @@
 #define        XCR0_YMM        (1ULL << 2)     /* YMM state available */
 #define        XCR0_BNDREGS    (1ULL << 3)     /* MPX Bounds register state */
 #define        XCR0_BNDCSR     (1ULL << 4)     /* MPX Bounds configuration/state  */
+#if !defined(RC_HIDE_XNU_J137)
+#define        XCR0_OPMASK     (1ULL << 5)     /* Opmask register state */
+#define        XCR0_ZMM_HI256  (1ULL << 6)     /* ZMM upper 256-bit state */
+#define        XCR0_HI16_ZMM   (1ULL << 7)     /* ZMM16..ZMM31 512-bit state */
+#endif /* not RC_HIDE_XNU_J137 */
 #define XFEM_X87       XCR0_X87
 #define XFEM_SSE       XCR0_SSE
 #define        XFEM_YMM        XCR0_YMM
 #define        XFEM_BNDREGS    XCR0_BNDREGS
 #define        XFEM_BNDCSR     XCR0_BNDCSR
+#if !defined(XNU_HODE_J137)
+#define        XFEM_OPMASK     XCR0_OPMASK
+#define        XFEM_ZMM_HI256  XCR0_ZMM_HI256
+#define        XFEM_HI16_ZMM   XCR0_HI16_ZMM
+#define        XFEM_ZMM        (XFEM_ZMM_HI256 | XFEM_HI16_ZMM | XFEM_OPMASK)
+#endif /* not XNU_HODE_J137 */
 #define XCR0 (0)
 
 #define        PMAP_PCID_PRESERVE (1ULL << 63)
 #define        PMAP_PCID_MASK (0xFFF)
 
+/*
+ * If thread groups are needed for x86, set this to 1
+ */
+#define CONFIG_THREAD_GROUPS 0
+
 #ifndef        ASSEMBLER
 
 #include <sys/cdefs.h>
@@ -290,9 +306,9 @@ static inline uintptr_t get_cr3_base(void)
        return(cr3 & ~(0xFFFULL));
 }
 
-static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint32_t preserve)
+static inline void set_cr3_composed(uintptr_t base, uint16_t pcid, uint64_t preserve)
 {
-       __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( ( (uint64_t)preserve) << 63) ) );
+       __asm__ volatile("mov %0, %%cr3" : : "r" (base | pcid | ( (preserve) << 63) ) );
 }
 
 static inline uintptr_t get_cr4(void)
@@ -358,11 +374,22 @@ static inline void swapgs(void)
        __asm__ volatile("swapgs");
 }
 
+static inline void hlt(void)
+{
+       __asm__ volatile("hlt");
+}
+
 #ifdef MACH_KERNEL_PRIVATE
 
 static inline void flush_tlb_raw(void)
 {
-       set_cr3_raw(get_cr3_raw());
+       uintptr_t cr4 = get_cr4();
+       if (cr4 & CR4_PGE) {
+               set_cr4(cr4 & ~CR4_PGE);
+               set_cr4(cr4 | CR4_PGE);
+       } else {
+               set_cr3_raw(get_cr3_raw());
+       }
 }
 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
@@ -416,6 +443,7 @@ extern void do_mfence(void);
 #define mfence() do_mfence()
 #endif
 
+#ifdef __LP64__
 static inline uint64_t rdpmc64(uint32_t pmc)
 {
        uint32_t lo=0, hi=0;
@@ -451,7 +479,7 @@ static inline uint64_t rdtscp64(uint32_t *aux)
                                         : "ecx");
        return ((hi) << 32) | (lo);
 }
-
+#endif /* __LP64__ */
 
 /*
  * rdmsr_carefully() returns 0 when the MSR has been read successfully,
@@ -603,9 +631,7 @@ __END_DECLS
 
 #define MSR_IA32_PP0_ENERGY_STATUS             0x639
 #define MSR_IA32_PP1_ENERGY_STATUS             0x641
-#if !defined(XNU_HIDE_SKYLAKE)
 #define MSR_IA32_IA_PERF_LIMIT_REASONS_SKL     0x64F
-#endif
 
 #define MSR_IA32_IA_PERF_LIMIT_REASONS         0x690
 #define MSR_IA32_GT_PERF_LIMIT_REASONS         0x6B0
@@ -628,4 +654,9 @@ __END_DECLS
 #define MSR_IA32_KERNEL_GS_BASE                        0xC0000102
 #define MSR_IA32_TSC_AUX                       0xC0000103
 
+#define HV_VMX_EPTP_MEMORY_TYPE_UC             0x0
+#define HV_VMX_EPTP_MEMORY_TYPE_WB             0x6
+#define HV_VMX_EPTP_WALK_LENGTH(wl)                    (0ULL | ((((wl) - 1) & 0x7) << 3))
+#define HV_VMX_EPTP_ENABLE_AD_FLAGS                    (1ULL << 6)
+
 #endif /* _I386_PROC_REG_H_ */