+ div = LEGACY_UART_CLOCK / 16 / baud_rate;
+ IO_WRITE( LCR, lcr | UART_LCR_DLAB );
+ IO_WRITE( DLM, (unsigned char)(div >> 8) );
+ IO_WRITE( DLL, (unsigned char) div );
+ IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
+}
+
+static int
+legacy_uart_tr0( void )
+{
+ return (IO_READ(LSR) & UART_LSR_THRE);
+}
+
+static void
+legacy_uart_td0( int c )
+{
+ IO_WRITE( THR, c );
+}
+
+static void
+legacy_uart_init( void )
+{
+ /* Disable hardware interrupts */
+
+ IO_WRITE( MCR, 0 );
+ IO_WRITE( IER, 0 );
+
+ /* Disable FIFO's for 16550 devices */
+
+ IO_WRITE( FCR, 0 );
+
+ /* Set for 8-bit, no parity, DLAB bit cleared */
+
+ IO_WRITE( LCR, UART_LCR_8BITS );
+
+ /* Set baud rate */
+
+ gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
+
+ /* Assert DTR# and RTS# lines (OUT2?) */
+
+ IO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
+
+ /* Clear any garbage in the input buffer */
+
+ IO_READ( RBR );
+
+ uart_initted = 1;
+}
+
+static int
+legacy_uart_rr0( void )
+{
+ unsigned char lsr;
+
+ lsr = IO_READ( LSR );
+
+ if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
+ {
+ IO_READ( RBR ); /* discard */
+ return 0;
+ }
+
+ return (lsr & UART_LSR_DR);
+}
+
+static int
+legacy_uart_rd0( void )
+{
+ return IO_READ( RBR );
+}
+
+static struct pe_serial_functions legacy_uart_serial_functions = {
+ .uart_init = legacy_uart_init,
+ .uart_set_baud_rate = legacy_uart_set_baud_rate,
+ .tr0 = legacy_uart_tr0,
+ .td0 = legacy_uart_td0,
+ .rr0 = legacy_uart_rr0,
+ .rd0 = legacy_uart_rd0
+};
+
+// =============================================================================
+// MMIO UART (using PCH LPSS UART2)
+// =============================================================================
+
+#define MMIO_UART2_BASE_LEGACY 0xFE034000 /* Legacy MMIO Config space */
+#define MMIO_UART2_BASE 0xFE036000 /* MMIO Config space */
+#define PCI_UART2 0xFE037000 /* PCI Config Space */
+
+#define MMIO_WRITE(r, v) ml_phys_write_word(mmio_uart_base + MMIO_UART_##r, v)
+#define MMIO_READ(r) ml_phys_read_word(mmio_uart_base + MMIO_UART_##r)
+
+enum {
+ MMIO_UART_RBR = 0x0, /* receive buffer Register (R) */
+ MMIO_UART_THR = 0x0, /* transmit holding register (W) */
+ MMIO_UART_DLL = 0x0, /* DLAB = 1, divisor latch (LSB) */
+ MMIO_UART_IER = 0x4, /* interrupt enable register */
+ MMIO_UART_DLM = 0x4, /* DLAB = 1, divisor latch (MSB) */
+ MMIO_UART_FCR = 0x8, /* fifo control register (W) */
+ MMIO_UART_LCR = 0xc, /* line control register */
+ MMIO_UART_MCR = 0x10, /* modem control register */
+ MMIO_UART_LSR = 0x14, /* line status register */
+ MMIO_UART_SCR = 0x1c, /* scratch register */
+ MMIO_UART_CLK = 0x200, /* clocks register */
+ MMIO_UART_RST = 0x204 /* Reset register */
+};
+
+static vm_offset_t mmio_uart_base = 0;
+
+static int
+mmio_uart_present( void )
+{
+ MMIO_WRITE( SCR, 0x5a );
+ if (MMIO_READ(SCR) != 0x5a) return 0;
+ MMIO_WRITE( SCR, 0xa5 );
+ if (MMIO_READ(SCR) != 0xa5) return 0;
+ return 1;
+}
+
+static int
+mmio_uart_probe( void )
+{
+ unsigned new_mmio_uart_base = 0;
+
+ // if specified, mmio_uart overrides all probing
+ if (PE_parse_boot_argn("mmio_uart", &new_mmio_uart_base, sizeof (new_mmio_uart_base)))
+ {
+ // mmio_uart=0 will disable mmio_uart support
+ if (new_mmio_uart_base == 0) {
+ return 0;
+ }
+
+ mmio_uart_base = new_mmio_uart_base;
+ return 1;
+ }
+
+ // probe the two possible MMIO_UART2 addresses
+ mmio_uart_base = MMIO_UART2_BASE;
+ if (mmio_uart_present()) {
+ return 1;
+ }
+
+ mmio_uart_base = MMIO_UART2_BASE_LEGACY;
+ if (mmio_uart_present()) {
+ return 1;
+ }
+
+ // no mmio uart found
+ return 0;
projects / apple / xnu.git / blobdiff