xnu-1504.15.3.tar.gz

[apple/xnu.git] / osfmk / i386 / commpage / cacheflush.s

diff --git a/osfmk/i386/commpage/cacheflush.s b/osfmk/i386/commpage/cacheflush.s
index 2e12d074626527a5ee730c30b909681b6c0404fb..4d9e98b0b3a605e88f58918083a010ade005cc0b 100644 (file)
--- a/osfmk/i386/commpage/cacheflush.s
+++ b/osfmk/i386/commpage/cacheflush.s
@@ -1,5 +1,5 @@
 /*
 /*

- * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2003-2006 Apple Computer, Inc. All rights reserved.

  *
  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
  * 
  *
  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
  * 


@@ -26,19 +26,54 @@
  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  */
 
  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  */
 

-#include <sys/appleapiopts.h>

 #include <machine/cpu_capabilities.h>
 #include <machine/commpage.h>
 
 #include <machine/cpu_capabilities.h>
 #include <machine/commpage.h>
 

-        .text
-        .align  2, 0x90
+// void sysFlushDcache( void *p, size_t len );
+// 32-bit version

 
 

-Lsys_flush_dcache:
+COMMPAGE_FUNCTION_START(sys_flush_dcache, 32, 4)
+       movl    8(%esp),%ecx            // get length
+       movl    4(%esp),%edx            // get ptr
+       testl   %ecx,%ecx               // length 0?
+       jz      2f                      // yes
+       mfence                          // ensure previous stores make it to memory
+       clflush -1(%edx,%ecx)           // make sure last line is flushed
+1:
+       clflush (%edx)                  // flush a line
+       addl    $64,%edx
+       subl    $64,%ecx
+       ja      1b
+       mfence                          // make sure memory is updated before we return
+2:

        ret
        ret

+COMMPAGE_DESCRIPTOR(sys_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,kCache64,0)

 
 

-       COMMPAGE_DESCRIPTOR(sys_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0)

 
 

-Lsys_icache_invalidate:
+// void sysFlushDcache( void *p, size_t len );
+// 64-bit version
+// %rdi = ptr,  %rsi = length
+COMMPAGE_FUNCTION_START(sys_flush_dcache_64, 64, 4)
+       testq   %rsi,%rsi               // length 0?
+       jz      2f                      // yes
+       mfence                          // ensure previous stores make it to memory
+       clflush -1(%rdi,%rsi)           // make sure last line is flushed
+1:
+       clflush (%rdi)                  // flush a line
+       addq    $64,%rdi
+       subq    $64,%rsi
+       ja      1b
+       mfence                          // make sure memory is updated before we return
+2:

        ret
        ret

+COMMPAGE_DESCRIPTOR(sys_flush_dcache_64,_COMM_PAGE_FLUSH_DCACHE,kCache64,0)

 
 

-       COMMPAGE_DESCRIPTOR(sys_icache_invalidate,_COMM_PAGE_FLUSH_ICACHE,0,0)
+// void sysIcacheInvalidate( void *p, size_t len );
+
+COMMPAGE_FUNCTION_START(sys_icache_invalidate, 32, 4)
+       // This is a NOP on intel processors, since the intent of the API
+       // is to make data executable, and Intel L1Is are coherent with L1D.
+       // We can use same routine both in 32 and 64-bit mode, since it is
+       // just a RET instruction.
+       ret
+COMMPAGE_DESCRIPTOR(sys_icache_invalidate,_COMM_PAGE_FLUSH_ICACHE,0,0)