#include <cpus.h>
#include <ppc/asm.h>
#include <ppc/proc_reg.h>
+#include <ppc/spec_reg.h>
#include <ppc/POWERMAC/mp/MPPlugIn.h>
#include <ppc/exception.h>
#include <mach/machine/vm_param.h>
lwz r6,4(r3) /* Get word 1 */
lwz r7,8(r3) /* Get word 2 */
lwz r8,12(r3) /* Get word 3 */
+ rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
lwz r9,16(r3) /* Get word 4 */
lwz r10,20(r3) /* Get word 5 */
+ rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
lwz r11,24(r3) /* Get word 6 */
lwz r12,28(r3) /* Get word 7 */
lwz r10,24(r3) /* Get DBAT 3 high */
lwz r11,28(r3) /* Get DBAT 3 low */
- sync /* Common decency and the state law require you to wash your hands */
+ sync /* Common decency and the state law require that you wash your hands */
mtdbatu 0,r4 /* Load DBAT 0 high */
mtdbatl 0,r5 /* Load DBAT 0 low */
mtdbatu 1,r6 /* Load DBAT 1 high */
ENTRY(LoadIBATs, TAG_NO_FRAME_USED)
- lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of CreateFakeIO firmware call number */
+ lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of LoadIBATsCall firmware call number */
ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
sc /* Do it to it */
blr /* Bye bye, Birdie... */
lwz r10,24(r3) /* Get IBAT 3 high */
lwz r11,28(r3) /* Get IBAT 3 low */
- sync /* Common decency and the state law require you to wash your hands */
+ sync /* Common decency and the state law require that you wash your hands */
mtibatu 0,r4 /* Load IBAT 0 high */
mtibatl 0,r5 /* Load IBAT 0 low */
mtibatu 1,r6 /* Load IBAT 1 high */
ENTRY(CreateFakeDEC, TAG_NO_FRAME_USED)
+#if 0
+ mflr r4 ; (TEST/DEBUG)
+ bl EXT(ml_sense_nmi) ; (TEST/DEBUG)
+ mtlr r4 ; (TEST/DEBUG)
+#endif
lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
sc /* Do it to it */
sc /* Do it to it */
blr /* Bye bye, Birdie... */
+/*
+ * This is the glue to choke system
+ */
+
+ENTRY(ChokeSys, TAG_NO_FRAME_USED)
+
+ lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */
+ ori r0,r0,LOW_ADDR(Choke) /* Bottom half */
+ sc /* Do it to it */
+ blr /* Bye bye, Birdie... */
+
/*
* Used to initialize the SCC for debugging output
*/
blr /* Return to interrupt handler */
/*
- * Choke the system. This is just a dummy for now,
- * but we'll eventually do something.
+ * Choke the system.
*/
ENTRY(DoChokeLL, TAG_NO_FRAME_USED)
- BREAKPOINT_TRAP /* Dummy for now */
-
+ mfsprg r11,0 ; Get the per_proc address
+ lwz r11,PP_TEMPWORK1(r11) ; Restore the return address
+ li r3,T_CHOKE ; Set external interrupt value
+ mtlr r11 ; Restore the LR
+ stw r3,saveexception(r13) ; Modify the exception type to external
+ blr ; Return to interrupt handler
+
/*
* Set the low level trace flags
*/
ltsNoMSRx:
lis r5,hi16(EXT(trcWork)) ; Get trace area
+ rlwinm r12,r12,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
ori r5,r5,lo16(EXT(trcWork)) ; again
lwz r3,traceMask(r5) /* Get the old trace flags to pass back */
+ rlwinm r12,r12,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
stw r4,traceMask(r5) /* Replace with the new ones */
mtmsr r12 /* Restore the MSR */
ori r7,r7,0x0020 /* Find it */
dcbi 0,r7 /* Toss it */
sync /* Sync it */
+ rlwinm r9,r9,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
eieio /* Get it */
lwz r6,0x000C(r7) /* Check it */
eieio /* Fence it */
dcbi 0,r7 /* Toss it */
+ rlwinm r9,r9,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
rlwinm. r4,r6,0,19,19 /* Check it */
rlwinm r6,r6,0,20,18 /* Clear it */
sync /* Sync it */
LEXT(stFloat)
mfmsr r0 ; Save the MSR
+ rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
+ rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
mtmsr r4
LEXT(stVectors)
- mfpvr r6 ; Get machine type
+
+ mfsprg r6,2 ; Get features
mr r5,r3 ; Save area address
- rlwinm r6,r6,16,17,31 ; Rotate on it
+ rlwinm. r6,r6,0,pfAltivecb,pfAltivecb ; Do we have Altivec?
li r3,0 ; Assume failure
- cmplwi r6,PROCESSOR_VERSION_7400 ; Do we have Altivec?
- bltlr+ ; No...
+ beqlr- ; No...
mfmsr r0 ; Save the MSR
+ rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
+ rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
mtmsr r4
lvxl v31,0,r5
mtmsr r0
isync
+
blr
LEXT(stSpecrs)
mfmsr r0 ; Save the MSR
+ rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
+ rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
mtmsr r4
isync
mtmsr r0
isync
+
blr
projects / apple / xnu.git / blobdiff