#define hid1 1009 /* Clock configuration */
#define iabr 1010 /* Instruction address breakpoint register */
#define ictrl 1011 /* Instruction Cache Control */
+#define ldstdb 1012 /* Load/Store Debug */
#define dabr 1013 /* Data address breakpoint register */
#define msscr0 1014 /* Memory subsystem control */
#define msscr1 1015 /* Memory subsystem debug */
#define risegm 0x00080000
#define eiec 13
#define eiecm 0x00040000
+#define mum 14
+#define mumm 0x00020000
#define nhr 15
#define nhrm 0x00010000
#define ice 16
#define nopti 31
#define noptim 0x00000001
+; hid1 bits
+#define hid1pcem 0xF8000000
+#define hid1prem 0x06000000
+#define hid1pi0 14
+#define hid1pi0m 0x00020000
+#define hid1ps 15
+#define hid1psm 0x00010000
+#define hid1pc0 0x0000F800
+#define hid1pr0 0x00000600
+#define hid1pc1 0x000000F8
+#define hid1pc0 0x0000F800
+#define hid1pr1 0x00000006
+
; msscr0 bits
#define shden 0
#define shdenm 0x80000000
#define tfsts 24
#define tfste 25
#define tfstm 0x000000C0
+#define l2pfes 30
+#define l2pfee 31
+#define l2pfem 0x00000003
; msscr1 bits
#define cqd 15