#define bootCPU 10
#define firstInit 9
#define firstBoot 8
-
+
+/* Defines for PVRs */
+#define PROCESSOR_VERSION_601 1
+#define PROCESSOR_VERSION_603 3
+#define PROCESSOR_VERSION_604 4
+#define PROCESSOR_VERSION_603e 6
+#define PROCESSOR_VERSION_750 8
+#define PROCESSOR_VERSION_604e 9
+#define PROCESSOR_VERSION_604ev 10 /* ? */
+#define PROCESSOR_VERSION_7400 12 /* ? */
+#define PROCESSOR_VERSION_7410 0x800C /* ? */
+#define PROCESSOR_VERSION_7450 0x8000 /* ? */
+
/*
* Interrupt and bootup stack for initial processor
*/
.align ALIGN
.globl EXT(intstack_top_ss)
EXT(intstack_top_ss):
- .long EXT(intstack)+INTSTACK_SIZE-SS_SIZE /* intstack_top_ss points to the top of interrupt stack */
+ .long EXT(intstack)+INTSTACK_SIZE-FM_SIZE /* intstack_top_ss points to the top of interrupt stack */
.align ALIGN
.globl EXT(debstack_top_ss)
EXT(debstack_top_ss):
- .long EXT(debstack)+KERNEL_STACK_SIZE-SS_SIZE /* debstack_top_ss points to the top of debug stack */
+ .long EXT(debstack)+KERNEL_STACK_SIZE-FM_SIZE /* debstack_top_ss points to the top of debug stack */
.globl EXT(debstackptr)
EXT(debstackptr):
- .long EXT(debstack)+KERNEL_STACK_SIZE-SS_SIZE
+ .long EXT(debstack)+KERNEL_STACK_SIZE-FM_SIZE
#endif /* MACH_KDP || MACH_KDB */
; 750CX
-init750CX: bflr firstBoot ; No init for wakeup....
+init750CX:
+ bf firstBoot, init750 ; No init for wakeup....
mfspr r13,hid1 ; Get HID1
li r14,lo16(0xFD5F) ; Get valid
rlwinm r13,r13,4,28,31 ; Isolate
slw r14,r14,r13 ; Position
rlwimi r17,r14,15-pfCanNapb,pfCanNapb,pfCanNapb ; Set it
- b init750com ; Join common...
+ b init750 ; Join common...
; 750
-init750: bflr firstBoot ; No init for wakeup....
+init750:
+ bf firstBoot, init750nb ; No init for wakeup....
-init750com: mfspr r13,l2cr ; Get the L2CR
+ mfspr r13,l2cr ; Get the L2CR
rlwinm. r0,r13,0,l2e,l2e ; Any L2?
bne+ i750hl2 ; Yes...
rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No L2, turn off feature
-i750hl2: lis r14,hi16(256*1024) ; Base L2 size
- addis r15,r13,0x3000 ; Hah... Figure this one out...
- rlwinm r15,r15,4,30,31 ; Isolate
- rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
- slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
- beq- init750none ; Not a valid setting...
+i750hl2:
+ lis r14,hi16(256*1024) ; Base L2 size
+ addis r15,r13,0x3000 ; Hah... Figure this one out...
+ rlwinm r15,r15,4,30,31 ; Isolate
+ rlwinm. r8,r13,0,l2siz,l2sizf ; Was size valid?
+ slw r14,r14,r15 ; Set 256KB, 512KB, or 1MB
+ beq- init750l2none ; Not a valid setting...
- stw r13,pfl2cr(r30) ; Shadow the L2CR
- stw r14,pfl2Size(r30) ; Set the L2 size
- blr ; Return....
+ stw r13,pfl2cr(r30) ; Shadow the L2CR
+ stw r14,pfl2Size(r30) ; Set the L2 size
+ b init750l2done ; Done with L2
-init750none:
- rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
- blr ; Return...
-
+init750l2none:
+ rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache
+
+init750l2done:
+ mfspr r11,hid0 ; Get the current HID0
+ stw r11,pfHID0(r30) ; Save the HID0 value
+ blr ; Return...
+
+init750nb:
+ lwz r11,pfHID0(r30) ; Get HID0
+ sync
+ mtspr hid0,r11 ; Set the HID
+ isync
+ sync
+ blr
init7400: bf firstBoot,i7400nb ; Do different if not initial boot...
mfspr r13,l2cr ; Get the L2CR
stw r11,pfMSSCR1(r30) ; Save the MSSCR1 value
blr ; Return...
-i7400nb: lwz r11,pfHID0(r30) ; Get HID0
+i7400nb:
+ lwz r11,pfHID0(r30) ; Get HID0
sync
mtspr hid0,r11 ; Set the HID
+ isync
+ sync
lwz r11,pfMSSCR0(r30) ; Get MSSCR0
isync
sync
b init7450fin ; Return....
init7450none:
- rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
+ rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist
+ rlwinm r11,r17,pfWillNapb-pfCanNapb,pfCanNapb,pfCanNapb ; Set pfCanNap if pfWillNap is set
+ or r17,r17,r11
-init7450fin: mfspr r11,hid0 ; Get the current HID0
+init7450fin:
+ rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 ; Make sure pfWillNap is not set
+
+ mfspr r11,hid0 ; Get the current HID0
stw r11,pfHID0(r30) ; Save the HID0 value
mfspr r11,hid1 ; Get the current HID1
stw r11,pfHID1(r30) ; Save the HID1 value
stw r11,pfICTRL(r30) ; Save the ICTRL value
mfspr r11,ldstcr ; Get the ldstcr register
stw r11,pfLDSTCR(r30) ; Save the LDSTCR value
+ mfspr r11,ldstdb ; Get the ldstdb register
+ stw r11,pfLDSTDB(r30) ; Save the LDSTDB value
blr ; Return....
mtspr ldstcr,r11 ; Set the LDSTCR
isync
sync
+ lwz r11,pfLDSTDB(r30) ; Get LDSTDB
+ sync
+ mtspr ldstdb,r11 ; Set the LDSTDB
+ isync
+ sync
blr
.long 32*1024
.long 32*1024
+
; 7400 (generic)
.align 2
.long 0xFFFFFF00 ; Just revisions 1.xx
.short PROCESSOR_VERSION_7450
.short 0x0100
- .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfL23lck | pfL1nnc | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfLClck | pfL1nnc | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long init7450
+ .long CPU_SUBTYPE_POWERPC_7450
+ .long 105
+ .long 90
+ .long 32
+ .long 32*1024
+ .long 32*1024
+
+; 7450 (2.0)
+
+ .align 2
+ .long 0xFFFFFFFF ; Just revision 2.0
+ .short PROCESSOR_VERSION_7450
+ .short 0x0200
+ .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 32*1024
.long 32*1024
-; 7450 (>=2)
+; 7450 (2.1)
.align 2
.long 0xFFFF0000 ; All other revisions
.short PROCESSOR_VERSION_7450
.short 0
- .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfL23lck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
+ .long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfWillNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 32*1024
.long 32*1024
+
; Default dumb loser machine
.align 2
projects / apple / xnu.git / blobdiff