*
* @APPLE_LICENSE_HEADER_START@
*
- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License"). You may not use this file except in compliance with the
- * License. Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
*
- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this
+ * file.
+ *
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
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- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
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*
* @APPLE_LICENSE_HEADER_END@
*/
#include <debug.h>
#include <mach/ppc/vm_param.h>
#include <ppc/exception.h>
+#include <ppc/savearea.h>
#define FPVECDBG 0
#define GDDBG 0
.text
/*
- * void load_context(thread_t thread)
- *
- * Load the context for the first kernel thread, and go.
+ * void machine_load_context(thread_t thread)
*
- * NOTE - if DEBUG is set, the former routine is a piece
- * of C capable of printing out debug info before calling the latter,
- * otherwise both entry points are identical.
+ * Load the context for the first thread to run on a
+ * cpu, and go.
*/
-ENTRY2(load_context, Load_context, TAG_NO_FRAME_USED)
-
-/*
- * Since this is the first thread, we came in on the interrupt
- * stack. The first thread never returns, so there is no need to
- * worry about saving its frame, hence we can reset the istackptr
- * back to the saved_state structure at it's top
- */
-
+ .align 5
+ .globl EXT(machine_load_context)
-/*
- * get new thread pointer and set it into the active_threads pointer
- *
- */
-
+LEXT(machine_load_context)
mfsprg r6,0
lwz r0,PP_INTSTACK_TOP_SS(r6)
- lwz r11,PP_CPU_DATA(r6)
stw r0,PP_ISTACKPTR(r6)
- stw r3,CPU_ACTIVE_THREAD(r11)
-
-/* Find the new stack and store it in active_stacks */
-
- lwz r12,PP_ACTIVE_STACKS(r6)
- lwz r1,THREAD_KERNEL_STACK(r3)
- lwz r9,THREAD_TOP_ACT(r3) /* Point to the active activation */
- stw r1,0(r12)
+ lwz r9,THREAD_TOP_ACT(r3) /* Set up the current thread */
+ mtsprg 1,r9
li r0,0 /* Clear a register */
- lwz r8,ACT_MACT_PCB(r9) /* Get the savearea used */
- lwz r10,SAVflags(r8) /* Get the savearea flags */
- rlwinm r7,r8,0,0,19 /* Switch to savearea base */
- lwz r11,SAVprev(r8) /* Get the previous savearea */
+ lwz r3,ACT_MACT_PCB(r9) /* Get the savearea used */
mfmsr r5 /* Since we are passing control, get our MSR values */
- lwz r1,saver1(r8) /* Load new stack pointer */
- rlwinm r10,r10,0,1,31 /* Remove the attached flag */
- stw r0,saver3(r8) /* Make sure we pass in a 0 for the continuation */
- lwz r7,SACvrswap(r7) /* Get the translation from virtual to real */
+ lwz r11,SAVprev+4(r3) /* Get the previous savearea */
+ lwz r1,saver1+4(r3) /* Load new stack pointer */
+ stw r0,saver3+4(r3) /* Make sure we pass in a 0 for the continuation */
stw r0,FM_BACKPTR(r1) /* zero backptr */
- stw r5,savesrr1(r8) /* Pass our MSR to the new guy */
- stw r10,SAVflags(r8) /* Pass back the flags */
- xor r3,r7,r8 /* Get the physical address of the new context save area */
+ stw r5,savesrr1+4(r3) /* Pass our MSR to the new guy */
stw r11,ACT_MACT_PCB(r9) /* Unstack our savearea */
- b EXT(exception_exit) /* Go end it all... */
+ stw r0,ACT_PREEMPT_CNT(r9) /* Enable preemption */
+ b EXT(exception_exit) /* Go for it */
-/* struct thread_shuttle *Switch_context(struct thread_shuttle *old,
- * void (*cont)(void),
- * struct thread_shuttle *new)
+/* thread_t Switch_context(thread_t old,
+ * void (*cont)(void),
+ * thread_t new)
*
* Switch from one thread to another. If a continuation is supplied, then
* we do not need to save callee save registers.
/* void Call_continuation( void (*continuation)(void), vm_offset_t stack_ptr)
*/
-ENTRY(Call_continuation, TAG_NO_FRAME_USED)
- mtlr r3
- mr r1, r4 /* Load new stack pointer */
- blr /* Jump to the continuation */
+ .align 5
+ .globl EXT(Call_continuation)
+
+LEXT(Call_continuation)
+
+ mtlr r3
+ mr r1, r4 /* Load new stack pointer */
+ blr /* Jump to the continuation */
/*
* Get the old kernel stack, and store into the thread structure.
* See if a continuation is supplied, and skip state save if so.
- * NB. Continuations are no longer used, so this test is omitted,
- * as should the second argument, but it is in generic code.
- * We always save state. This does not hurt even if continuations
- * are put back in.
+ *
+ * Note that interrupts must be disabled before we get here (i.e., splsched)
*/
/* Context switches are double jumps. We pass the following to the
* context switch firmware call:
*
- * R3 = switchee's savearea
+ * R3 = switchee's savearea, virtual if continuation, low order physical for full switch
* R4 = old thread
* R5 = new SRR0
* R6 = new SRR1
+ * R7 = high order physical address of savearea for full switch
*
* savesrr0 is set to go to switch_in
* savesrr1 is set to uninterruptible with translation on
*/
-ENTRY(Switch_context, TAG_NO_FRAME_USED)
+ .align 5
+ .globl EXT(Switch_context)
+
+LEXT(Switch_context)
- mfsprg r6,0 /* Get the per_proc block */
- lwz r12,PP_ACTIVE_STACKS(r6)
+ mfsprg r12,0 ; Get the per_proc block
#if DEBUG
- lwz r11,PP_ISTACKPTR(r6) ; (DEBUG/TRACE) make sure we are not
- mr. r11,r11 ; (DEBUG/TRACE) on the interrupt
- bne+ notonintstack ; (DEBUG/TRACE) stack
+ lwz r0,PP_ISTACKPTR(r12) ; (DEBUG/TRACE) make sure we are not
+ mr. r0,r0 ; (DEBUG/TRACE) on the interrupt
+ bne++ notonintstack ; (DEBUG/TRACE) stack
BREAKPOINT_TRAP
notonintstack:
#endif
- stw r4,THREAD_CONTINUATION(r3)
- cmpwi cr1,r4,0 /* used waaaay down below */
- lwz r11,0(r12)
- stw r11,THREAD_KERNEL_STACK(r3)
-/*
- * Make the new thread the current thread.
- */
-
- lwz r11,PP_CPU_DATA(r6)
- stw r5, CPU_ACTIVE_THREAD(r11)
-
- lwz r11,THREAD_KERNEL_STACK(r5)
-
- lwz r5,THREAD_TOP_ACT(r5)
- lwz r10,PP_ACTIVE_STACKS(r6)
+ lwz r5,THREAD_TOP_ACT(r5) ; Get the new activation
+ lwz r8,ACT_MACT_PCB(r5) ; Get the PCB for the new guy
+ lwz r9,cioSpace(r5) ; Get copyin/out address space
+ cmpwi cr1,r4,0 ; Remeber if there is a continuation - used waaaay down below
lwz r7,CTHREAD_SELF(r5) ; Pick up the user assist word
- lwz r8,ACT_MACT_PCB(r5) /* Get the PCB for the new guy */
-
- stw r11,0(r10) ; Save the kernel stack address
- stw r7,UAW(r6) ; Save the assist word for the "ultra fast path"
-
+ lwz r11,ACT_MACT_BTE(r5) ; Get BlueBox Task Environment
+ lwz r6,cioRelo(r5) ; Get copyin/out relocation top
+ mtsprg 1,r5
+ lwz r2,cioRelo+4(r5) ; Get copyin/out relocation bottom
+
+ stw r7,UAW(r12) ; Save the assist word for the "ultra fast path"
+
lwz r7,ACT_MACT_SPF(r5) ; Get the special flags
- lwz r10,ACT_KLOADED(r5)
- li r0,0
- cmpwi cr0,r10,0
- lwz r10,PP_ACTIVE_KLOADED(r6)
- stw r7,spcFlags(r6) ; Set per_proc copy of the special flags
- beq cr0,.L_sw_ctx_not_kld
-
- stw r5,0(r10)
- b .L_sw_ctx_cont
-
-.L_sw_ctx_not_kld:
- stw r0,0(r10) /* act_kloaded = 0 */
-
-.L_sw_ctx_cont:
- lis r10,hi16(EXT(trcWork)) ; Get top of trace mask
- rlwinm r7,r8,0,0,19 /* Switch to savearea base */
- ori r10,r10,lo16(EXT(trcWork)) ; Get bottom of mask
- lwz r11,SAVprev(r8) /* Get the previous of the switchee's savearea */
- lwz r10,traceMask(r10) ; Get the enabled traces
+ sth r9,ppCIOmp+mpSpace(r12) ; Save the space
+ stw r6,ppCIOmp+mpNestReloc(r12) ; Save top part of physical address
+ stw r2,ppCIOmp+mpNestReloc+4(r12) ; Save bottom part of physical address
+ stw r11,ppbbTaskEnv(r12) ; Save the bb task env
+ lwz r2,traceMask(0) ; Get the enabled traces
+ stw r7,spcFlags(r12) ; Set per_proc copy of the special flags
lis r0,hi16(CutTrace) ; Trace FW call
- mr. r10,r10 ; Any tracing going on?
+ mr. r2,r2 ; Any tracing going on?
+ lwz r11,SAVprev+4(r8) ; Get the previous of the switchee savearea
ori r0,r0,lo16(CutTrace) ; Trace FW call
- beq+ cswNoTrc ; No trace today, dude...
+ beq++ cswNoTrc ; No trace today, dude...
mr r10,r3 ; Save across trace
lwz r2,THREAD_TOP_ACT(r3) ; Trace old activation
mr r3,r11 ; Trace prev savearea
sc ; Cut trace entry of context switch
mr r3,r10 ; Restore
-cswNoTrc: mfmsr r6 /* Get the MSR because the switched to thread should inherit it */
- lwz r7,SACvrswap(r7) /* Get the translation from virtual to real */
+cswNoTrc: lwz r2,curctx(r5) ; Grab our current context pointer
+ lwz r10,FPUowner(r12) ; Grab the owner of the FPU
+ lwz r9,VMXowner(r12) ; Grab the owner of the vector
+ lhz r0,PP_CPU_NUMBER(r12) ; Get our CPU number
+ mfmsr r6 ; Get the MSR because the switched to thread should inherit it
+ stw r11,ACT_MACT_PCB(r5) ; Dequeue the savearea we are switching to
+ li r0,1 ; Get set to hold off quickfret
+
+ rlwinm r6,r6,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Turn off the FP
+ cmplw r10,r2 ; Do we have the live float context?
+ lwz r10,FPUlevel(r2) ; Get the live level
+ mr r4,r3 ; Save our old thread to pass back
+ cmplw cr5,r9,r2 ; Do we have the live vector context?
+ rlwinm r6,r6,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Turn off the vector
+ stw r0,holdQFret(r12) ; Make sure we hold off releasing quickfret
+ bne++ cswnofloat ; Float is not ours...
+
+ cmplw r10,r11 ; Is the level the same?
+ lwz r5,FPUcpu(r2) ; Get the owning cpu
+ bne++ cswnofloat ; Level not the same, this is not live...
+
+ cmplw r5,r0 ; Still owned by this cpu?
+ lwz r10,FPUsave(r2) ; Get the level
+ bne++ cswnofloat ; CPU claimed by someone else...
+
+ mr. r10,r10 ; Is there a savearea here?
+ ori r6,r6,lo16(MASK(MSR_FP)) ; Enable floating point
+
+ beq-- cswnofloat ; No savearea to check...
+
+ lwz r3,SAVlevel(r10) ; Get the level
+ lwz r5,SAVprev+4(r10) ; Get the previous of this savearea
+ cmplw r3,r11 ; Is it for the current level?
+
+ bne++ cswnofloat ; Nope...
+
+ stw r5,FPUsave(r2) ; Pop off this savearea
+
+ rlwinm r3,r10,0,0,19 ; Move back to start of page
+
+ lwz r5,quickfret(r12) ; Get the first in quickfret list (top)
+ lwz r9,quickfret+4(r12) ; Get the first in quickfret list (bottom)
+ lwz r7,SACvrswap(r3) ; Get the virtual to real conversion (top)
+ lwz r3,SACvrswap+4(r3) ; Get the virtual to real conversion (bottom)
+ stw r5,SAVprev(r10) ; Link the old in (top)
+ stw r9,SAVprev+4(r10) ; Link the old in (bottom)
+ xor r3,r10,r3 ; Convert to physical
+ stw r7,quickfret(r12) ; Set the first in quickfret list (top)
+ stw r3,quickfret+4(r12) ; Set the first in quickfret list (bottom)
+
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ mr r7,r2 ; (TEST/DEBUG)
+ li r2,0x4401 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+ lhz r0,PP_CPU_NUMBER(r12) ; (TEST/DEBUG)
+ mr r2,r7 ; (TEST/DEBUG)
+#endif
+
+cswnofloat: bne++ cr5,cswnovect ; Vector is not ours...
+
+ lwz r10,VMXlevel(r2) ; Get the live level
+
+ cmplw r10,r11 ; Is the level the same?
+ lwz r5,VMXcpu(r2) ; Get the owning cpu
+ bne++ cswnovect ; Level not the same, this is not live...
+
+ cmplw r5,r0 ; Still owned by this cpu?
+ lwz r10,VMXsave(r2) ; Get the level
+ bne++ cswnovect ; CPU claimed by someone else...
+
+ mr. r10,r10 ; Is there a savearea here?
+ oris r6,r6,hi16(MASK(MSR_VEC)) ; Enable vector
+
+ beq-- cswnovect ; No savearea to check...
+
+ lwz r3,SAVlevel(r10) ; Get the level
+ lwz r5,SAVprev+4(r10) ; Get the previous of this savearea
+ cmplw r3,r11 ; Is it for the current level?
+
+ bne++ cswnovect ; Nope...
+
+ stw r5,VMXsave(r2) ; Pop off this savearea
+ rlwinm r3,r10,0,0,19 ; Move back to start of page
+
+ lwz r5,quickfret(r12) ; Get the first in quickfret list (top)
+ lwz r9,quickfret+4(r12) ; Get the first in quickfret list (bottom)
+ lwz r2,SACvrswap(r3) ; Get the virtual to real conversion (top)
+ lwz r3,SACvrswap+4(r3) ; Get the virtual to real conversion (bottom)
+ stw r5,SAVprev(r10) ; Link the old in (top)
+ stw r9,SAVprev+4(r10) ; Link the old in (bottom)
+ xor r3,r10,r3 ; Convert to physical
+ stw r2,quickfret(r12) ; Set the first in quickfret list (top)
+ stw r3,quickfret+4(r12) ; Set the first in quickfret list (bottom)
+
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x4501 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
+
+cswnovect: li r0,0 ; Get set to release quickfret holdoff
+ rlwinm r11,r8,0,0,19 ; Switch to savearea base
+ lis r9,hi16(EXT(switch_in)) ; Get top of switch in routine
+ lwz r5,savesrr0+4(r8) ; Set up the new SRR0
+ lwz r7,SACvrswap(r11) ; Get the high order V to R translation
+ lwz r11,SACvrswap+4(r11) ; Get the low order V to R translation
+ ori r9,r9,lo16(EXT(switch_in)) ; Bottom half of switch in
+ stw r0,holdQFret(r12) ; Make sure we release quickfret holdoff
+ stw r9,savesrr0+4(r8) ; Make us jump to the switch in routine
+
+ lwz r9,SAVflags(r8) /* Get the flags */
lis r0,hi16(SwitchContextCall) /* Top part of switch context */
- lis r9,hi16(EXT(switch_in)) /* Get top of switch in routine */
- stw r11,ACT_MACT_PCB(r5) /* Dequeue the savearea we're switching to */
-
- rlwinm r6,r6,0,MSR_FP_BIT+1,MSR_FP_BIT-1 /* Turn off the FP */
- ori r9,r9,lo16(EXT(switch_in)) /* Bottom half of switch in */
- lwz r5,savesrr0(r8) /* Set up the new SRR0 */
- rlwinm r6,r6,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 /* Turn off the vector */
- mr r4,r3 /* Save our old thread to pass back */
- stw r9,savesrr0(r8) /* Make us jump to the switch in routine */
li r10,MSR_SUPERVISOR_INT_OFF /* Get the switcher's MSR */
- lwz r9,SAVflags(r8) /* Get the flags */
- stw r10,savesrr1(r8) /* Set up for switch in */
- rlwinm r9,r9,0,15,13 /* Reset the syscall flag */
ori r0,r0,lo16(SwitchContextCall) /* Bottom part of switch context */
- rlwinm r9,r9,0,1,31 /* Clear the attached flag */
- xor r3,r7,r8 /* Get the physical address of the new context save area */
+ stw r10,savesrr1+4(r8) /* Set up for switch in */
+ rlwinm r9,r9,0,15,13 /* Reset the syscall flag */
+ xor r3,r11,r8 /* Get the physical address of the new context save area */
stw r9,SAVflags(r8) /* Set the flags */
-/* if blocking on continuation avoid saving state */
- bne cr1,1f
+
+ bne cr1,swtchtocont ; Switch to the continuation
sc /* Switch to the new context */
/* We come back here in the new thread context
* R3 where it belongs.
*/
blr /* Jump into the new thread */
+
+;
+; This is where we go when a continuation is set. We are actually
+; killing off the old context of the new guy so we need to pop off
+; any float or vector states for the ditched level.
+;
+; Note that we do the same kind of thing a chkfac in hw_exceptions.s
+;
+
-1: stw r5,savesrr0(r8) /* go to real pc */
- stw r4,saver3(r8) /* must pass back old thread */
- b EXT(exception_exit) /* blocking on continuation, avoid state save */
+swtchtocont:
+
+ stw r5,savesrr0+4(r8) ; Set the pc
+ stw r6,savesrr1+4(r8) ; Set the next MSR to use
+ stw r4,saver3+4(r8) ; Make sure we pass back the old thread
+ mr r3,r8 ; Pass in the virtual address of savearea
+
+ b EXT(exception_exit) ; Blocking on continuation, toss old context...
* with translation on. If we could, this should be done in lowmem_vectors
* before translation is turned on. But we can't, dang it!
*
- * R3 = switcher's savearea
+ * R3 = switcher's savearea (32-bit virtual)
* saver4 = old thread in switcher's save
* saver5 = new SRR0 in switcher's save
* saver6 = new SRR1 in switcher's save
*/
-ENTRY(switch_in, TAG_NO_FRAME_USED)
-
- lwz r4,saver4(r3) /* Get the old thread */
- li r8,MSR_VM_OFF /* Set to everything off */
- lwz r9,THREAD_TOP_ACT(r4) /* Get the switched from ACT */
- lwz r5,saver5(r3) /* Get the srr0 value */
- lwz r10,ACT_MACT_PCB(r9) /* Get the top PCB on the old thread */
- lwz r6,saver6(r3) /* Get the srr1 value */
- stw r3,ACT_MACT_PCB(r9) /* Put the new one on top */
- stw r10,SAVprev(r3) /* Chain on the old one */
+ .align 5
+ .globl EXT(switch_in)
+
+LEXT(switch_in)
- mr r3,r4 /* Pass back the old thread */
+ lwz r4,saver4+4(r3) ; Get the old thread
+ lwz r5,saver5+4(r3) ; Get the srr0 value
+
+ mfsprg r0,2 ; Get feature flags
+ lwz r9,THREAD_TOP_ACT(r4) ; Get the switched from ACT
+ lwz r6,saver6+4(r3) ; Get the srr1 value
+ rlwinm. r0,r0,0,pf64Bitb,pf64Bitb ; Check for 64-bit
+ lwz r10,ACT_MACT_PCB(r9) ; Get the top PCB on the old thread
+
+ stw r3,ACT_MACT_PCB(r9) ; Put the new one on top
+ stw r10,SAVprev+4(r3) ; Chain on the old one
- mtsrr0 r5 /* Set return point */
- mtsrr1 r6 /* Set return MSR */
- rfi /* Jam... */
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
+ mr r3,r4 ; Pass back the old thread
+ mtsrr0 r5 ; Set return point
+ mtsrr1 r6 ; Set return MSR
+
+ bne++ siSixtyFour ; Go do 64-bit...
+ rfi ; Jam...
+
+siSixtyFour:
+ rfid ; Jam...
/*
- * void fpu_save(void)
- *
- * To do the floating point and VMX, we keep three thread pointers: one
- * to the current thread, one to the thread that has the floating point context
- * loaded into the FPU registers, and one for the VMX owner.
- *
- * Each of these threads has three PCB pointers. The normal PCB, the FPU pcb,
- * and the VMX pcb. There is also a bit for each in the savearea flags.
- * When we take an exception, or need to use the FPU/VMX in the kernel, we call
- * this routine. It checks to see if there is an owner thread for the facility.
- * If so, it saves the facility's state information in the normal PCB. Then, it
- * turns on the appropriate flag in the savearea to indicate that the state is
- * in that particular savearea. Also, the thread pointer for the owner in
- * the per_processor block is cleared. Note that we don't have to worry about the
- * PCB pointers in the thread because whenever the state is loaded, the associated
- * savearea is released and the pointer cleared. This is done so that the facility
- * context always migrates to the normal savearea/PCB. This always insures that
- * no more than 2 saveareas are used for a thread.
- *
- * When the context is loaded into the facility, the associated PCB is released if
- * its usage flags indicate that it is empty. (Note that return from exception and
- * context switch honor these flags and won't release a savearea if there is unrestored
- * facility context.) The per_processor is set to point to the facility owner's
- * thread and the associated PCB pointer within the thread is cleared because
- * the PCB has been released.
- *
- * Part of loading a context is to release the savearea. If the savearea contains
- * other context, the savearea cannot be released. So, what we're left with is
- * that there will be no normal context savearea, but one for the as-not-yet
- * restored facility savearea. Again, when that context is reloaded, the PCB
- * is released, and when it is again stored, it goes into the "normal" savearea.
- *
- * So, what do we do when there is no general context, and we have some FPU/VMX
- * state to save? Heck if I know, but it happens when we switch threads when
- * we shortcut system calls. The question is: does the target thread carry the
- * FPU/VMX context with it or not? Actually, it don't matter, not one little bit.
- * If we are asked to save it, we gotta. It's a really lousy way to do it, but
- * short of starting over with FPUs, it's what's what. Therefore, we'll
- * allocate an FPU context save and attach it.
- *
- * Actually, it's not quite that simple: since we aren't in
- * in interrupt handler context (that's only in fpu_switch) we can't use
- * quickfret to merge FPU into general context. So, if there is an FPU
- * savearea, we need to use that. So what we do is: if there is FPU context
- * use that. If there is a general context, then use that. If neither,
- * allocate a savearea and make that the FPU context.
- *
- * The next thing we have to do is to allow the kernel to use both the
- * floating point and Altivec. It is not recommended, but there may be a
- * good reason to do so. So, what we need to do is to treat each of the
- * three types of context the same, by keeping a LIFO chain of states.
- * We do have a problem with that in that there can be multiple levels of
- * kernel context. For example, we are using floating point and we take a
- * page fault, and somehow start using the FPU, and take another page fault,
- * etc.
- *
- * Anyway, we will hope that we only reasonably use floating point and vectors in
- * the kernel. And try to pack the context in as few saveareas as possible.
+ * void fpu_save(facility_context ctx)
*
- * The way we keep these "levels" of floating point or vector context straight is
- * to remember the top of the normal savearea chain when we activate the
- * facility when it is first used. Then, when we save that context, this value
- * is saved in its level field.
- *
- * What the level concept gives us is a way to distinguish between multiple
- * independent contexts under the same thread activation. Any time we take
- * any kind of interruption (trap, system call, I/O interruption), we are,
- * in effect, running with a different context even though we are in the
- * same thread. The top savearea address is used only as a marker. It does not
- * point to any context associated with the float or vector context. For example,
- * the top savearea pointer will always be 0 for the user context, because there
- * it it always last on the list.
- *
- * As normal context is unstacked, the first facility context is checked and
- * if there is a match, the facility savearea is released. This is because we
- * are returning to a level before the facility saved there was used. In effect,
- * this allows us to unwind the facility context saveareas at different rates.
- *
- * In conjunction with the current activation, these markers are also used to
- * determine the state of the facility enablement. Whenever the facility context is
- * "live," i.e., loaded in the hardware registers and belonging to the currently
- * running context, the facility is enabled before dispatch.
- *
- * There is nothing special about using floating point or vector facilities,
- * no preliminary saving, enabling, or disabling. You just use them. The only exception
- * is during context switching on an SMP system. In this case, the context must
- * be saved as there is no guarantee that the thread will resume on the same
- * processor. This is not a good thing, not at all.
- *
- * Whenever we switch out a thread with a dirty context, we always need to save it
- * because it can wake up on a different processor. However, once the context has
- * been saved, we don't need to save it again until it gets dirty, nor do we need
- * to reload it unless someone else's context has been loaded. To handle this
- * optimization, we need 3 things. We need to know what processor the saved context
- * was last loaded on, whether the loaded context could be dirty, and if we've already
- * saved it.
- *
- * Whenever the facility is enabled, the processor ID is saved in the activation. This
- * will show which processor has dirty data. When a context switch occurs, the facility
- * contexts are saved, but are still remembered as live. The next time we need to
- * context switch, we first check if the state is live, and if not, do no state
- * saving. Then we check if the state has already been save and if not, save it.
- * The facility is always disabled on a context switch. On a UP, this save function
- * does not occur.
- *
- * Whenever a facility unavailable interruption occurs, the current state is saved
- * if it is live and unsaved. However, if the live state is the same as the new
- * one to be loaded, the processor ID is checked and if it is the current processor
- * the state does not need to be loaded or saved. The facility is simply enabled.
- *
- * Once allocated, facility saveareas are not released until a return is made to a
- * previous level. Once a facility has been enabled, there is no way to tell if
- * it will ever be used again, but it is likely. Therefore, discarding a savearea
- * when its context is made live is extra overhead. So, we don't do it, but we
- * do mark the savearea contents as invalid.
- *
+ * Note that there are some oddities here when we save a context we are using.
+ * It is really not too cool to do this, but what the hey... Anyway,
+ * we turn fpus and vecs off before we leave., The oddity is that if you use fpus after this, the
+ * savearea containing the context just saved will go away. So, bottom line is
+ * that don't use fpus until after you are done with the saved context.
*/
+ .align 5
+ .globl EXT(fpu_save)
-/*
-; The following is the actual way it is implemented. It doesn't quite match
-; the above text. I need to go and fix that.
-;
-; Context download (operates on owner's data):
-;
-; 0) enable facility
-; 1) if no owner exit to context restore
-; 2) if context processor != current processor exit to context restore
-; 3) if current activation == owner activation:
-; 1) if curr level == active level:
-; 1) if top facility savearea exists:
-; invalidate savearea by setting level to 1
-; 2) enable facility for user
-; 3) exit
-;
-; 2) else go to 5
-;
-; 4) if curr level == active level:
-; 1) if top facility savearea exists:
-; 1) if top save level == active level exit to context restore
-;
-; 5) allocate savearea
-; 1) if there is a facility save and it is invalid, select it, and break
-; 2) scan normal list for free facility area, select if found, and break
-; 3) scan other facility for free save: select, if found, and break
-; 4) allocate a new save area
-;
-; 6) save context
-; 7) mark facility save with curr level
-; 8) if reusing cached savearea (case #1) exit to context restore
-; 9) set facility save backchain to facility top savearea
-; 10) set facility top to savearea
-; 11) exit to context restore
-;
-;
-; Context restore/upload (operates on current activation's data):
-;
-; 1) set current to activation
-; 2) set active level to current level
-; 3) set context processor to current processor
-; 4) if no facility savearea or top save level != curr level
-; initialize facility registers to empty value
-; 5) else
-; 1) load registers from savearea
-; 2) invalidate save area by setting level to 1
-;
-; 6) enable facility for user
-; 7) exit to interrupt return
-;
-;
-; Context save (operates on current activation's data; only used during context switch):
-; (context switch always disables the facility)
-;
-; 1) if no owner exit
-; 2) if owner != current activation exit
-; 3) if context processor != current processor
-; 1) clear owner
-; 2) exit
-;
-; 4) if facility top savearea level exists and == active level exit
-; 5) if curr level != active level exit
-; 6) allocate savearea
-; 1) if there is a facility save and it is invalid, select it, and break
-; 2) scan normal list for free facility area, select if found, and break
-; 3) scan other facility for free save: select, if found, and break
-; 4) allocate a new save area
-; 7) save context
-; 8) mark facility savearea with curr level
-; 9) if reusing cached savearea (case #1) exit
-; 10) set facility save backchain to facility top savearea
-; 11) set facility top to savearea
-; 12) exit
-;
-;
-; Exception exit (hw_exceptions):
-;
-; 1) disable return facility
-; 2) if returning savearea != active level
-; 1) if owner != current activation exit
-; 2) if context processor != current processor:
-; 1) clear owner
-; 2) exit
-;
-; 3) if new level != active level exit
-; 4) enable return facility
-; 5) exit
-;
-; 3) if no facility savearea exit
-; 4) if top save level == active or top is invalid
-; 1) dequeue top facility savearea
-; 2) set active level to new top savearea's level
-; 3) release savearea
-; 4) if owner == current activation clear owner
-; 5) exit
-;
-;
-;
-;
-; if (owner == activation) && (curr level == active level)
-; && (activation processor == current processor) ::= context live
-*/
-
-ENTRY(fpu_save, TAG_NO_FRAME_USED)
-
- mfmsr r0 ; Get the MSR
- rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Turn off floating point forever
- rlwinm r2,r0,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; But do interrupts only for now
- ori r2,r2,MASK(MSR_FP) ; Enable the floating point feature for now also
- mtmsr r2 ; Set the MSR
+LEXT(fpu_save)
+
+ lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
+ li r12,lo16(MASK(MSR_EE)) ; Get the EE bit
+ ori r2,r2,lo16(MASK(MSR_FP)) ; Get FP
+
+ mfmsr r0 ; Get the MSR
+ andc r0,r0,r2 ; Clear FP, VEC
+ andc r2,r0,r12 ; Clear EE
+ ori r2,r2,MASK(MSR_FP) ; Enable the floating point feature for now also
+ mtmsr r2 ; Set the MSR
isync
-
- mfsprg r6,0 ; Get the per_processor block
- lwz r12,PP_FPU_THREAD(r6) ; Get the thread that owns the FPU
+
+ mfsprg r6,0 ; Get the per_processor block
+ lwz r12,FPUowner(r6) ; Get the context ID for owner
+
#if FPVECDBG
- mr r7,r0 ; (TEST/DEBUG)
- li r4,0 ; (TEST/DEBUG)
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- mr. r3,r12 ; (TEST/DEBUG)
- li r2,0x6F00 ; (TEST/DEBUG)
- li r5,0 ; (TEST/DEBUG)
- beq- noowneryet ; (TEST/DEBUG)
- lwz r4,ACT_MACT_FPUlvl(r12) ; (TEST/DEBUG)
- lwz r5,ACT_MACT_FPU(r12) ; (TEST/DEBUG)
-
-noowneryet: oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
- mr r0,r7 ; (TEST/DEBUG)
+ mr r7,r0 ; (TEST/DEBUG)
+ li r4,0 ; (TEST/DEBUG)
+ mr r10,r3 ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ mr. r3,r12 ; (TEST/DEBUG)
+ li r2,0x6F00 ; (TEST/DEBUG)
+ li r5,0 ; (TEST/DEBUG)
+ beq-- noowneryet ; (TEST/DEBUG)
+ lwz r4,FPUlevel(r12) ; (TEST/DEBUG)
+ lwz r5,FPUsave(r12) ; (TEST/DEBUG)
+
+noowneryet: oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+ mr r0,r7 ; (TEST/DEBUG)
+ mr r3,r10 ; (TEST/DEBUG)
#endif
- mflr r2 ; Save the return address
- lwz r10,PP_CPU_DATA(r6) ; Get the CPU data pointer
- lhz r11,PP_CPU_NUMBER(r6) ; Get our CPU number
+ mflr r2 ; Save the return address
+
+fsretry: mr. r12,r12 ; Anyone own the FPU?
+ lhz r11,PP_CPU_NUMBER(r6) ; Get our CPU number
+ beq-- fsret ; Nobody owns the FPU, no save required...
- mr. r12,r12 ; Anyone own the FPU?
+ cmplw cr1,r3,r12 ; Is the specified context live?
- lwz r10,CPU_ACTIVE_THREAD(r10) ; Get the pointer to the active thread
+ isync ; Force owner check first
- beq- fsret ; Nobody owns the FPU, no save required...
+ lwz r9,FPUcpu(r12) ; Get the cpu that context was last on
+ bne-- cr1,fsret ; No, it is not...
- lwz r10,THREAD_TOP_ACT(r10) ; Now get the activation that is running
- lwz r9,ACT_MACT_FPUcpu(r12) ; Get the last CPU to use this context
+ cmplw cr1,r9,r11 ; Was the context for this processor?
+ beq-- cr1,fsgoodcpu ; Facility last used on this processor...
+
+ b fsret ; Someone else claimed it...
- cmplw r12,r10 ; Do we own the FPU?
- cmplw cr1,r9,r11 ; Was the context for this processor?
- bne+ fsret ; Facility belongs to some other activation...
- li r3,0 ; Assume we need a fix-me-up
- beq- cr1,fsgoodcpu ; Facility last used on this processor...
- stw r3,PP_FPU_THREAD(r6) ; Clear owner because it was really on the other processor
- b fsret ; Bail now with no save...
+ .align 5
-fsgoodcpu: lwz r3,ACT_MACT_FPU(r12) ; Get the current FPU savearea for the thread
- lwz r9,ACT_MACT_FPUlvl(r12) ; Get our current level indicator
+fsgoodcpu: lwz r3,FPUsave(r12) ; Get the current FPU savearea for the thread
+ lwz r9,FPUlevel(r12) ; Get our current level indicator
- cmplwi cr1,r3,0 ; Have we ever saved this facility context?
- beq- cr1,fsneedone ; Never saved it, so we need an area...
+ cmplwi cr1,r3,0 ; Have we ever saved this facility context?
+ beq- cr1,fsneedone ; Never saved it, so go do it...
- lwz r8,SAVlvlfp(r3) ; Get the level this savearea is for
- cmplwi r8,1 ; See if it is a spare
- cmplw cr1,r9,r8 ; Correct level?
- beq+ fsusespare ; We have a spare to use...
- beq- cr1,fsret ; The current level is already saved, bail out...
+ lwz r8,SAVlevel(r3) ; Get the level this savearea is for
+ cmplw cr1,r9,r8 ; Correct level?
+ beq-- cr1,fsret ; The current level is already saved, bail out...
-fsneedone: li r3,0 ; Tell the routine to allocate an area if none found
- bl fpsrchsave ; Find a free savearea
-
- mfsprg r6,0 ; Get back per_processor block
- oris r7,r7,hi16(SAVfpuvalid) ; Set the allocated bit
- lwz r12,PP_FPU_THREAD(r6) ; Get back our thread
- mtlr r2 ; Restore return
- lwz r8,ACT_MACT_FPU(r12) ; Get the current top floating point savearea
- lwz r9,ACT_MACT_FPUlvl(r12) ; Get our current level indicator again
- stw r3,ACT_MACT_FPU(r12) ; Set this as the latest FPU savearea for the thread
- stw r8,SAVprefp(r3) ; And then chain this in front
- stw r7,SAVflags(r3) ; Set the validity flags
- stw r12,SAVact(r3) ; Make sure we point to the right guy
+fsneedone: bl EXT(save_get) ; Get a savearea for the context
-fsusespare: stw r9,SAVlvlfp(r3) ; And set the level this savearea is for
-
-;
-; Save the current FPU state into the PCB of the thread that owns it.
-;
-
- la r11,savefp0(r3) ; Point to the 1st line
- dcbz 0,r11 ; Allocate the first savearea line
-
- la r11,savefp4(r3) /* Point to the 2nd line */
- stfd f0,savefp0(r3)
- dcbz 0,r11 /* allocate it */
- stfd f1,savefp1(r3)
- stfd f2,savefp2(r3)
- la r11,savefp8(r3) /* Point to the 3rd line */
- stfd f3,savefp3(r3)
- dcbz 0,r11 /* allocate it */
- stfd f4,savefp4(r3)
- stfd f5,savefp5(r3)
- stfd f6,savefp6(r3)
- la r11,savefp12(r3) /* Point to the 4th line */
- stfd f7,savefp7(r3)
- dcbz 0,r11 /* allocate it */
- stfd f8,savefp8(r3)
- stfd f9,savefp9(r3)
- stfd f10,savefp10(r3)
- la r11,savefp16(r3) /* Point to the 5th line */
- stfd f11,savefp11(r3)
- dcbz 0,r11 /* allocate it */
- stfd f12,savefp12(r3)
- stfd f13,savefp13(r3)
- stfd f14,savefp14(r3)
- la r11,savefp20(r3) /* Point to the 6th line */
- stfd f15,savefp15(r3)
- stfd f16,savefp16(r3)
- stfd f17,savefp17(r3)
- stfd f18,savefp18(r3)
- la r11,savefp24(r3) /* Point to the 7th line */
- stfd f19,savefp19(r3)
- dcbz 0,r11 /* allocate it */
- stfd f20,savefp20(r3)
- lwz r10,liveFPSCR(r6) ; Get the previously saved FPSCR
- stfd f21,savefp21(r3)
- stfd f22,savefp22(r3)
- li r9,0 ; Just clear this out
- la r11,savefp28(r3) /* Point to the 8th line */
- stfd f23,savefp23(r3)
- dcbz 0,r11 /* allocate it */
- stfd f24,savefp24(r3)
- stfd f25,savefp25(r3)
- stfd f26,savefp26(r3)
- stfd f27,savefp27(r3)
- stfd f28,savefp28(r3)
+ mfsprg r6,0 ; Get back per_processor block
+ li r4,SAVfloat ; Get floating point tag
+ lwz r12,FPUowner(r6) ; Get back our thread
+ stb r4,SAVflags+2(r3) ; Mark this savearea as a float
+ mr. r12,r12 ; See if we were disowned while away. Very, very small chance of it...
+ beq-- fsbackout ; If disowned, just toss savearea...
+ lwz r4,facAct(r12) ; Get the activation associated with live context
+ lwz r8,FPUsave(r12) ; Get the current top floating point savearea
+ stw r4,SAVact(r3) ; Indicate the right activation for this context
+ lwz r9,FPUlevel(r12) ; Get our current level indicator again
+ stw r3,FPUsave(r12) ; Set this as the most current floating point context
+ stw r8,SAVprev+4(r3) ; And then chain this in front
-; Note that we just save the FPSCR here for ease. It is really already saved
-; in the "normal" context area of the savearea.
+ stw r9,SAVlevel(r3) ; Show level in savearea
- stw r9,savefpscrpad(r3) ; Save the FPSCR pad
- stw r10,savefpscr(r3) ; Save the FPSCR
-
- stfd f29,savefp29(r3)
- stfd f30,savefp30(r3)
- stfd f31,savefp31(r3)
- lfd f0,savefp0(r3) ; We need to restore F0 because we used it
- ; to get the FPSCR
-
-#if 0
- la r9,savefp0(r3) ; (TEST/DEBUG)
- la r10,savefp31(r3) ; (TEST/DEBUG)
-
-chkkillmedead:
- lha r8,0(r9) ; (TEST/DEBUG)
- addi r9,r9,8 ; (TEST/DEBUG)
- cmpwi r8,-8 ; (TEST/DEBUG)
- cmplw cr1,r9,r10 ; (TEST/DEBUG)
- bne+ dontkillmedead ; (TEST/DEBUG)
- BREAKPOINT_TRAP ; (TEST/DEBUG)
-
-dontkillmedead: ; (TEST/DEBUG)
- ble+ cr1,chkkillmedead ; (TEST/DEBUG)
-#endif
-
-fsret: mtmsr r0 ; Put interrupts on if they were and floating point off
+ bl fp_store ; save all 32 FPRs in the save area at r3
+ mtlr r2 ; Restore return
+
+fsret: mtmsr r0 ; Put interrupts on if they were and floating point off
isync
blr
+fsbackout: mr r4,r0 ; restore the original MSR
+ b EXT(save_ret_wMSR) ; Toss savearea and return from there...
+
/*
* fpu_switch()
*
*
*/
-ENTRY(fpu_switch, TAG_NO_FRAME_USED)
+ .align 5
+ .globl EXT(fpu_switch)
+
+LEXT(fpu_switch)
+
#if DEBUG
-#if GDDBG
- mr r7,r4 ; Save input parameter
- lis r3,hi16(EXT(fpu_trap_count)) ; Get address of FP trap counter
- ori r3,r3,lo16(EXT(fpu_trap_count)) ; Get address of FP trap counter
- lwz r1,0(r3)
- lis r5,hi16(EXT(GratefulDeb)) ; Point to top of display
- ori r5,r5,lo16(EXT(GratefulDeb)) ; Put in bottom part
- addi r1,r1,1
- mtlr r5 ; Set link register
- stw r1,0(r3)
- mr r4,r1
- li r3,0
- blrl ; Display count
- mr r4,r7 ; Restore the parameter
-#else
lis r3,hi16(EXT(fpu_trap_count)) ; Get address of FP trap counter
ori r3,r3,lo16(EXT(fpu_trap_count)) ; Get address of FP trap counter
lwz r1,0(r3)
addi r1,r1,1
stw r1,0(r3)
-#endif
#endif /* DEBUG */
- mfsprg r6,0 ; Get the per_processor block
- mfmsr r19 ; Get the current MSR
-
- lwz r10,PP_CPU_DATA(r6) ; Get the CPU data pointer
- lwz r12,PP_FPU_THREAD(r6) ; Get the thread that owns the FPU
- lwz r10,CPU_ACTIVE_THREAD(r10) ; Get the pointer to the active thread
- ori r19,r19,lo16(MASK(MSR_FP)) ; Enable the floating point feature
- lwz r17,THREAD_TOP_ACT(r10) ; Now get the activation that is running
-
-; R12 has the "old" activation
-; R17 has the "new" activation
-
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F01 ; (TEST/DEBUG)
- mr r3,r12 ; (TEST/DEBUG)
- mr r5,r17 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#endif
- mr. r12,r12 ; See if there is any live FP status
+ mfsprg r26,0 ; Get the per_processor block
+ mfmsr r19 ; Get the current MSR
+ mfsprg r17,1 ; Get the current thread
- lhz r18,PP_CPU_NUMBER(r6) ; Get the current CPU, we will need it later
+ mr r25,r4 ; Save the entry savearea
+ lwz r22,FPUowner(r26) ; Get the thread that owns the FPU
+ ori r19,r19,lo16(MASK(MSR_FP)) ; Enable the floating point feature
- mtmsr r19 ; Enable floating point instructions
+ mtmsr r19 ; Enable floating point instructions
isync
-
- beq- fsnosave ; No live context, so nothing to save...
- lwz r19,ACT_MACT_FPUcpu(r12) ; Get the "old" active CPU
- lwz r15,ACT_MACT_PCB(r12) ; Get the current level of the "old" one
- cmplw r18,r19 ; Check the CPU that the old context is live on
- lwz r14,ACT_MACT_FPU(r12) ; Point to the top of the old context stack
- bne- fsnosave ; Context is not live if used on a different CPU...
- lwz r13,ACT_MACT_FPUlvl(r12) ; Get the "old" active level
-
-;
-; First, check to see if all we are doing is enabling because the
-; "new" context is live.
-;
+ lwz r27,ACT_MACT_PCB(r17) ; Get the current level
+ lwz r29,curctx(r17) ; Grab the current context anchor of the current thread
+
+; R22 has the "old" context anchor
+; R29 has the "new" context anchor
+
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F02 ; (TEST/DEBUG)
- mr r1,r15 ; (TEST/DEBUG)
- mr r3,r13 ; (TEST/DEBUG)
- mr r5,r14 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F01 ; (TEST/DEBUG)
+ mr r3,r22 ; (TEST/DEBUG)
+ mr r5,r29 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
+
+ lhz r16,PP_CPU_NUMBER(r26) ; Get the current CPU number
+
+fswretry: mr. r22,r22 ; See if there is any live FP status
- cmplw cr1,r12,r17 ; Are the "old" activation and the "new" the same?
- cmplwi cr2,r14,0 ; Is there any saved context on the "old" activation?
- bne+ cr1,fsmstsave ; The activations are different so "old" context must be saved...
+ beq- fsnosave ; No live context, so nothing to save...
+ isync ; Make sure we see this in the right order
+
+ lwz r30,FPUsave(r22) ; Get the top savearea
+ cmplw cr2,r22,r29 ; Are both old and new the same context?
+ lwz r18,FPUcpu(r22) ; Get the last CPU we ran on
+ cmplwi cr1,r30,0 ; Anything saved yet?
+ cmplw r18,r16 ; Make sure we are on the right processor
+ lwz r31,FPUlevel(r22) ; Get the context level
+
+ bne- fsnosave ; No, not on the same processor...
+
;
-; Here we know that both the "old" and "new" activations are the same. We will
-; check the current level and active levels. If they are the same, the context is
-; already live, so all we do is turn on the facility and invalidate the top
-; savearea.
-;
-; If the current level, the active level, and the top savearea level are the
-; same, then the context was saved as part of a thread context switch and neither
-; needs saving or restoration.
-;
-; In all other cases, the context must be saved unless we are just re-enabling
-; floating point.
+; Check to see if the live context has already been saved.
+; Also check to see if all we are here just to re-enable the MSR
+; and handle specially if so.
;
- cmplw r13,r15 ; Are the levels the same?
- cmplwi cr2,r14,0 ; Is there any saved context?
- bne- fsmstsave ; Levels are different, we need to save...
+ cmplw r31,r27 ; See if the current and active levels are the same
+ crand cr0_eq,cr2_eq,cr0_eq ; Remember if both the levels and contexts are the same
+ li r3,0 ; Clear this
- beq- cr2,fsenable ; No saved context at all, enable and go...
+ beq- fsthesame ; New and old are the same, just go enable...
+
+ beq- cr1,fsmstsave ; Not saved yet, go do it...
+
+ lwz r11,SAVlevel(r30) ; Get the level of top saved context
- lwz r20,SAVlvlfp(r14) ; Get the level of the top savearea
+ cmplw r31,r11 ; Are live and saved the same?
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F03 ; (TEST/DEBUG)
- mr r3,r15 ; (TEST/DEBUG)
- mr r5,r20 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F02 ; (TEST/DEBUG)
+ mr r3,r30 ; (TEST/DEBUG)
+ mr r5,r31 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+ li r3,0 ; (TEST/DEBUG)
#endif
- cmplw r15,r20 ; Is the top level the same as the current?
- li r0,1 ; Get the invalid flag
- bne- fsenable ; Not the same, just enable and go...
-
- stw r0,SAVlvlfp(r14) ; Invalidate that top savearea
- b fsenable ; Then enable and go...
+ beq+ fsnosave ; Same level, so already saved...
+
+fsmstsave: stw r3,FPUowner(r26) ; Kill the context now
+ eieio ; Make sure everyone sees it
+ bl EXT(save_get) ; Go get a savearea
+
+ mr. r31,r31 ; Are we saving the user state?
+ la r15,FPUsync(r22) ; Point to the sync word
+ beq++ fswusave ; Yeah, no need for lock...
;
-; We need to save the "old" context here. The LIFO queueing scheme works
-; out for all cases because if both the "new" and "old" activations are the
-; same, there can not be any saved state to load. the "new" level is
-; truely new.
+; Here we make sure that the live context is not tossed while we are
+; trying to push it. This can happen only for kernel context and
+; then only by a race with act_machine_sv_free.
;
-; When we save the context, we either use a new savearea, or the free
-; one that is cached at the head of the list.
-
-fsmstsave: beq- cr2,fsgetsave ; There is no possible cached save area
+; We only need to hold this for a very short time, so no sniffing needed.
+; If we find any change to the level, we just abandon.
+;
+fswsync: lwarx r19,0,r15 ; Get the sync word
+ li r0,1 ; Get the lock
+ cmplwi cr1,r19,0 ; Is it unlocked?
+ stwcx. r0,0,r15 ; Store lock and test reservation
+ cror cr0_eq,cr1_eq,cr0_eq ; Combine lost reservation and previously locked
+ bne-- fswsync ; Try again if lost reservation or locked...
+
+ isync ; Toss speculation
- lwz r5,SAVlvlfp(r14) ; Get the level of first facility savearea
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F04 ; (TEST/DEBUG)
- mr r3,r15 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#endif
- mr r3,r14 ; Assume we are invalid
- cmplwi r5,1 ; Is it invalid?
- cmplw cr1,r5,r13 ; Is the SA level the active one?
- beq+ fsusecache ; Invalid, just use it...
- beq- cr1,fsnosave ; The SA level is active, it is already saved...
+ lwz r0,FPUlevel(r22) ; Pick up the level again
+ li r7,0 ; Get unlock value
+ cmplw r0,r31 ; Same level?
+ beq++ fswusave ; Yeah, we expect it to be...
-fsgetsave: mr r3,r4 ; Use the interrupt save as the context savearea if none cached
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F05 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#endif
+ stw r7,FPUsync(r22) ; Unlock lock. No need to sync here
- bl fpsrchsave ; Find a free savearea
+ bl EXT(save_ret) ; Toss save area because we are abandoning save
+ b fsnosave ; Skip the save...
- stw r3,ACT_MACT_FPU(r12) ; Set this as the latest context savearea for the thread
- mfsprg r6,0 ; Get back per_processor block
- stw r14,SAVprefp(r3) ; And then chain this in front
- oris r7,r7,hi16(SAVfpuvalid) ; Set the allocated bit
- stw r12,SAVact(r3) ; Make sure we point to the right guy
- stw r7,SAVflags(r3) ; Set the allocation flags
+ .align 5
-fsusecache: la r11,savefp0(r3) ; Point to the 1st line in area
- stw r13,SAVlvlfp(r3) ; Set this context level
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F06 ; (TEST/DEBUG)
- mr r5,r13 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#endif
+fswusave: lwz r12,facAct(r22) ; Get the activation associated with the context
+ stw r3,FPUsave(r22) ; Set this as the latest context savearea for the thread
+ mr. r31,r31 ; Check again if we were user level
+ stw r30,SAVprev+4(r3) ; Point us to the old context
+ stw r31,SAVlevel(r3) ; Tag our level
+ li r7,SAVfloat ; Get the floating point ID
+ stw r12,SAVact(r3) ; Make sure we point to the right guy
+ stb r7,SAVflags+2(r3) ; Set that we have a floating point save area
-;
-; Now we will actually save the old context
-;
-
- dcbz 0,r11 ; Allocate the output area
+ li r7,0 ; Get the unlock value
- la r11,savefp4(r3) ; Point to the 2nd line
- stfd f0,savefp0(r3)
- dcbz 0,r11 ; Allocate cache
- stfd f1,savefp1(r3)
- stfd f2,savefp2(r3)
- la r11,savefp8(r3) ; Point to the 3rd line
- stfd f3,savefp3(r3)
- dcbz 0,r11 ; Allocate cache
- stfd f4,savefp4(r3)
- stfd f5,savefp5(r3)
- stfd f6,savefp6(r3)
- la r11,savefp12(r3) ; Point to the 4th line
- stfd f7,savefp7(r3)
- dcbz 0,r11 ; Allocate cache
- stfd f8,savefp8(r3)
- stfd f9,savefp9(r3)
- stfd f10,savefp10(r3)
- la r11,savefp16(r3) ; Point to the 5th line
- stfd f11,savefp11(r3)
- dcbz 0,r11 ; Allocate cache
- stfd f12,savefp12(r3)
- stfd f13,savefp13(r3)
- stfd f14,savefp14(r3)
- la r11,savefp20(r3) ; Point to the 6th line
- stfd f15,savefp15(r3)
- dcbz 0,r11 ; Allocate cache
- stfd f16,savefp16(r3)
- stfd f17,savefp17(r3)
- stfd f18,savefp18(r3)
- la r11,savefp24(r3) ; Point to the 7th line
- stfd f19,savefp19(r3)
- dcbz 0,r11 ; Allocate cache
- stfd f20,savefp20(r3)
-
- li r14,0 ; Clear this for now
- lwz r15,liveFPSCR(r6) ; Get the previously saved FPSCR
-
- stfd f21,savefp21(r3)
- stfd f22,savefp22(r3)
- la r11,savefp28(r3) ; Point to the 8th line
- stfd f23,savefp23(r3)
- dcbz 0,r11 ; allocate it
- stfd f24,savefp24(r3)
- stfd f25,savefp25(r3)
- stfd f26,savefp26(r3)
- la r11,savefpscrpad(r3) ; Point to the 9th line
- stfd f27,savefp27(r3)
- dcbz 0,r11 ; allocate it
- stfd f28,savefp28(r3)
- stfd f29,savefp29(r3)
- stfd f30,savefp30(r3)
- stfd f31,savefp31(r3)
+ beq-- fswnulock ; Skip unlock if user (we did not lock it)...
+ eieio ; Make sure that these updates make it out
+ stw r7,FPUsync(r22) ; Unlock it.
+
+fswnulock:
-; Note that we just save the FPSCR here for ease. It is really already saved
-; in the "normal" context area of the savearea.
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F03 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
- stw r14,savefpscrpad(r3) ; Save the FPSCR pad
- stw r15,savefpscr(r3) ; Save the FPSCR
+ bl fp_store ; store all 32 FPRs
;
; The context is all saved now and the facility is free.
;
-; Now check out the "new" and see if we need to load up his context.
-; If we do (and this should be the normal case), do it and then invalidate the
-; savearea. (This will keep it cached for quick access next time around.)
-;
-; If we do not (remember, we already took care of the case where we just enable
-; the FPU), we need to fill the registers with junk, because this level has
+; If we do not we need to fill the registers with junk, because this level has
; never used them before and some thieving bastard could hack the old values
; of some thread! Just imagine what would happen if they could! Why, nothing
; would be safe! My God! It is terrifying!
;
-
-fsnosave: lwz r15,ACT_MACT_PCB(r17) ; Get the current level of the "new" one
- lwz r14,ACT_MACT_FPU(r17) ; Point to the top of the "new" context stack
- lwz r13,ACT_MACT_FPUlvl(r17) ; Get the "new" active level
+
+fsnosave: lwz r15,ACT_MACT_PCB(r17) ; Get the current level of the "new" one
+ lwz r19,FPUcpu(r29) ; Get the last CPU we ran on
+ lwz r14,FPUsave(r29) ; Point to the top of the "new" context stack
+
+ stw r16,FPUcpu(r29) ; Claim context for us
+ eieio
+
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F07 ; (TEST/DEBUG)
- mr r1,r15 ; (TEST/DEBUG)
- mr r3,r14 ; (TEST/DEBUG)
- mr r5,r13 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lwz r13,FPUlevel(r29) ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F04 ; (TEST/DEBUG)
+ mr r1,r15 ; (TEST/DEBUG)
+ mr r3,r14 ; (TEST/DEBUG)
+ mr r5,r13 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
-
- cmplwi cr1,r14,0 ; Do we possibly have some context to load?
- stw r15,ACT_MACT_FPUlvl(r17) ; Set the "new" active level
- stw r18,ACT_MACT_FPUcpu(r17) ; Set the active CPU
- la r11,savefp0(r14) ; Point to first line to bring in
- stw r17,PP_FPU_THREAD(r6) ; Store current thread address in fpu_thread to claim fpu for thread
- beq+ cr1,MakeSureThatNoTerroristsCanHurtUsByGod ; No "new" context to load...
- lwz r0,SAVlvlfp(r14) ; Get the level of first facility savearea
- cmplw r0,r15 ; Top level correct to load?
- bne- MakeSureThatNoTerroristsCanHurtUsByGod ; No, go initialize...
+ lis r18,hi16(EXT(per_proc_info)) ; Set base per_proc
+ mulli r19,r19,ppSize ; Find offset to the owner per_proc
+ ori r18,r18,lo16(EXT(per_proc_info)) ; Set base per_proc
+ li r16,FPUowner ; Displacement to float owner
+ add r19,r18,r19 ; Point to the owner per_proc
+
+fsinvothr: lwarx r18,r16,r19 ; Get the owner
+ sub r0,r18,r29 ; Subtract one from the other
+ sub r11,r29,r18 ; Subtract the other from the one
+ or r11,r11,r0 ; Combine them
+ srawi r11,r11,31 ; Get a 0 if equal or -1 of not
+ and r18,r18,r11 ; Make 0 if same, unchanged if not
+ stwcx. r18,r16,r19 ; Try to invalidate it
+ bne-- fsinvothr ; Try again if there was a collision...
+
+ cmplwi cr1,r14,0 ; Do we possibly have some context to load?
+ la r11,savefp0(r14) ; Point to first line to bring in
+ stw r15,FPUlevel(r29) ; Set the "new" active level
+ eieio
+ stw r29,FPUowner(r26) ; Mark us as having the live context
+
+ beq++ cr1,MakeSureThatNoTerroristsCanHurtUsByGod ; No "new" context to load...
+
+ dcbt 0,r11 ; Touch line in
+
+ lwz r3,SAVprev+4(r14) ; Get the previous context
+ lwz r0,SAVlevel(r14) ; Get the level of first facility savearea
+ cmplw r0,r15 ; Top level correct to load?
+ bne-- MakeSureThatNoTerroristsCanHurtUsByGod ; No, go initialize...
+
+ stw r3,FPUsave(r29) ; Pop the context (we will toss the savearea later)
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F08 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F05 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
- dcbt 0,r11 ; Touch line in
- li r0,1 ; Get the level invalid indication
-
- la r11,savefp4(r14) ; Point to next line
- dcbt 0,r11 ; Touch line in
+// Note this code is used both by 32- and 128-byte processors. This means six extra DCBTs
+// are executed on a 128-byte machine, but that is better than a mispredicted branch.
+
+ la r11,savefp4(r14) ; Point to next line
+ dcbt 0,r11 ; Touch line in
lfd f0, savefp0(r14)
lfd f1,savefp1(r14)
- stw r0,SAVlvlfp(r14) ; Mark the savearea invalid because we are activating again
lfd f2,savefp2(r14)
- la r11,savefp8(r14) ; Point to next line
+ la r11,savefp8(r14) ; Point to next line
lfd f3,savefp3(r14)
- dcbt 0,r11 ; Touch line in
+ dcbt 0,r11 ; Touch line in
lfd f4,savefp4(r14)
lfd f5,savefp5(r14)
lfd f6,savefp6(r14)
- la r11,savefp12(r14) ; Point to next line
+ la r11,savefp12(r14) ; Point to next line
lfd f7,savefp7(r14)
- dcbt 0,r11 ; Touch line in
+ dcbt 0,r11 ; Touch line in
lfd f8,savefp8(r14)
lfd f9,savefp9(r14)
lfd f10,savefp10(r14)
- la r11,savefp16(r14) ; Point to next line
+ la r11,savefp16(r14) ; Point to next line
lfd f11,savefp11(r14)
- dcbt 0,r11 ; Touch line in
+ dcbt 0,r11 ; Touch line in
lfd f12,savefp12(r14)
lfd f13,savefp13(r14)
lfd f14,savefp14(r14)
- la r11,savefp20(r14) ; Point to next line
+ la r11,savefp20(r14) ; Point to next line
lfd f15,savefp15(r14)
- dcbt 0,r11 ; Touch line in
+ dcbt 0,r11 ; Touch line in
lfd f16,savefp16(r14)
lfd f17,savefp17(r14)
lfd f18,savefp18(r14)
- la r11,savefp24(r14) ; Point to next line
+ la r11,savefp24(r14) ; Point to next line
lfd f19,savefp19(r14)
- dcbt 0,r11 ; Touch line in
+ dcbt 0,r11 ; Touch line in
lfd f20,savefp20(r14)
lfd f21,savefp21(r14)
- la r11,savefp28(r14) ; Point to next line
+ la r11,savefp28(r14) ; Point to next line
lfd f22,savefp22(r14)
lfd f23,savefp23(r14)
- dcbt 0,r11 ; Touch line in
+ dcbt 0,r11 ; Touch line in
lfd f24,savefp24(r14)
lfd f25,savefp25(r14)
lfd f26,savefp26(r14)
lfd f30,savefp30(r14)
lfd f31,savefp31(r14)
-fsenable: lwz r9,SAVflags(r4) /* Get the flags of the current savearea */
- lwz r8,savesrr1(r4) ; Get the msr of the interrupted guy
- rlwinm r5,r4,0,0,19 /* Get the page address of the savearea */
- ori r8,r8,MASK(MSR_FP) ; Enable the floating point feature
- lwz r10,ACT_MACT_SPF(r17) ; Get the special flags
- lis r7,hi16(SAVattach) /* Get the attached flag */
- lwz r5,SACvrswap(r5) /* Get Virtual to Real translation */
+ mr r3,r14 ; Get the old savearea (we popped it before)
+ bl EXT(save_ret) ; Toss it
+
+fsenable: lwz r8,savesrr1+4(r25) ; Get the msr of the interrupted guy
+ ori r8,r8,MASK(MSR_FP) ; Enable the floating point feature
+ lwz r10,ACT_MACT_SPF(r17) ; Get the act special flags
+ lwz r11,spcFlags(r26) ; Get per_proc spec flags cause not in sync with act
oris r10,r10,hi16(floatUsed|floatCng) ; Set that we used floating point
- mr. r15,r15 ; See if we are doing this for user state
- stw r8,savesrr1(r4) ; Set the msr of the interrupted guy
- andc r9,r9,r7 /* Clear the attached bit */
- xor r3,r4,r5 /* Get the real address of the savearea */
- bne- fsnuser ; We are not user state...
- stw r10,ACT_MACT_SPF(r17) ; Set the activation copy
- stw r10,spcFlags(r6) ; Set per_proc copy
+ oris r11,r11,hi16(floatUsed|floatCng) ; Set that we used floating point
+ rlwinm. r0,r8,0,MSR_PR_BIT,MSR_PR_BIT ; See if we are doing this for user state
+ stw r8,savesrr1+4(r25) ; Set the msr of the interrupted guy
+ mr r3,r25 ; Pass the virtual addres of savearea
+ beq- fsnuser ; We are not user state...
+ stw r10,ACT_MACT_SPF(r17) ; Set the activation copy
+ stw r11,spcFlags(r26) ; Set per_proc copy
fsnuser:
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F0A ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F07 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
- stw r9,SAVflags(r4) /* Set the flags of the current savearea */
- b EXT(exception_exit) /* Exit from the fray... */
+ b EXT(exception_exit) ; Exit to the fray...
/*
* Initialize the registers to some bogus value
*/
MakeSureThatNoTerroristsCanHurtUsByGod:
-
+
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x7F09 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F06 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
- lis r5,hi16(EXT(FloatInit)) /* Get top secret floating point init value address */
- ori r5,r5,lo16(EXT(FloatInit)) /* Slam bottom */
- lfd f0,0(r5) /* Initialize FP0 */
- fmr f1,f0 ; Do them all
+ lis r5,hi16(EXT(FloatInit)) ; Get top secret floating point init value address
+ ori r5,r5,lo16(EXT(FloatInit)) ; Slam bottom
+ lfd f0,0(r5) ; Initialize FP0
+ fmr f1,f0 ; Do them all
fmr f2,f0
fmr f3,f0
fmr f4,f0
fmr f15,f0
fmr f16,f0
fmr f17,f0
- fsub f31,f31,f31 ; Get set to initialize the FPSCR
fmr f18,f0
fmr f19,f0
fmr f20,f0
- mtfsf 0xff,f31 ; Clear all FPSCR exception eanbles
fmr f21,f0
fmr f22,f0
fmr f23,f0
fmr f29,f0
fmr f30,f0
fmr f31,f0
- b fsenable ; Finish setting it all up...
+ b fsenable ; Finish setting it all up...
+
;
-; Finds an unused floating point area in the activation pointed
-; to by R12s saved contexts. If none are found (unlikely but possible)
-; and R3 is 0, a new area is allocated. If R3 is non-zero, it contains
-; a pointer to an floating point savearea that is free.
+; We get here when we are switching to the same context at the same level and the context
+; is still live. Essentially, all we are doing is turning on the faility. It may have
+; gotten turned off due to doing a context save for the current level or a context switch
+; back to the live guy.
;
-fpsrchsave:
- lwz r6,ACT_MACT_PCB(r12) ; Get the first "normal" savearea
-
-fpsrnorm: mr. r5,r6 ; Is there another?
- beq- fpsrvect ; No, search the vector saveareas...
- lwz r7,SAVflags(r5) ; Get the flags for this guy
- lwz r6,SAVprev(r5) ; Get the previous savearea, just in case
- andis. r8,r7,hi16(SAVfpuvalid) ; Have we found an empty FPU save in normal?
- beq+ fpsrgot ; We found one...
- b fpsrnorm ; Search again...
-
-fpsrvect: lwz r6,ACT_MACT_VMX(r12) ; Get the first "vector" savearea
-
-fpsrvectx: mr. r5,r6 ; Is there another?
- beq- fpsrget ; No, try to allocate one...
- lwz r7,SAVflags(r5) ; Get the flags for this guy
- lwz r6,SAVprevec(r5) ; Get the previous savearea, just in case
- andis. r8,r7,hi16(SAVfpuvalid) ; Have we found an empty FPU save in vector?
- bne- fpsrvectx ; Search again...
-
-fpsrgot: mr r3,r5 ; Get the savearea into the right register
- blr ; Return...
-
-fpsrget: mr. r5,r3 ; Do we allocate or use existing?
- beq+ fpsrallo ; Allocate one...
-
- lwz r7,SAVflags(r3) ; Get the passed in area flags
- blr ; Return...
-;
-; NOTE: save_get will return directly and set R7 to 0...
+
+ .align 5
+
+fsthesame:
+
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x7F0A ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
+ beq- cr1,fsenable ; Not saved yet, nothing to pop, go enable and exit...
+
+ lwz r11,SAVlevel(r30) ; Get the level of top saved context
+ lwz r14,SAVprev+4(r30) ; Get the previous savearea
+
+ cmplw r11,r31 ; Are live and saved the same?
+
+ bne+ fsenable ; Level not the same, nothing to pop, go enable and exit...
+
+ mr r3,r30 ; Get the old savearea (we popped it before)
+ stw r14,FPUsave(r22) ; Pop the savearea from the stack
+ bl EXT(save_ret) ; Toss it
+ b fsenable ; Go enable and exit...
+
+
+;
+; This function invalidates any live floating point context for the passed in facility_context.
+; This is intended to be called just before act_machine_sv_free tosses saveareas.
;
-fpsrallo: b EXT(save_get) ; Get a fresh savearea
+
+ .align 5
+ .globl EXT(toss_live_fpu)
+
+LEXT(toss_live_fpu)
+
+ lis r0,hi16(MASK(MSR_VEC)) ; Get VEC
+ mfmsr r9 ; Get the MSR
+ ori r0,r0,lo16(MASK(MSR_FP)) ; Add in FP
+ rlwinm. r8,r9,0,MSR_FP_BIT,MSR_FP_BIT ; Are floats on right now?
+ andc r9,r9,r0 ; Force off VEC and FP
+ ori r0,r0,lo16(MASK(MSR_EE)) ; Turn off EE
+ andc r0,r9,r0 ; Turn off EE now
+ mtmsr r0 ; No interruptions
+ isync
+ beq+ tlfnotours ; Floats off, can not be live here...
+
+ mfsprg r8,0 ; Get the per proc
+
+;
+; Note that at this point, since floats are on, we are the owner
+; of live state on this processor
+;
+
+ lwz r6,FPUowner(r8) ; Get the thread that owns the floats
+ li r0,0 ; Clear this just in case we need it
+ cmplw r6,r3 ; Are we tossing our own context?
+ bne-- tlfnotours ; Nope...
+
+ lfd f1,Zero(0) ; Make a 0
+ mtfsf 0xFF,f1 ; Clear it
+
+tlfnotours: lwz r11,FPUcpu(r3) ; Get the cpu on which we last loaded context
+ lis r12,hi16(EXT(per_proc_info)) ; Set base per_proc
+ mulli r11,r11,ppSize ; Find offset to the owner per_proc
+ ori r12,r12,lo16(EXT(per_proc_info)) ; Set base per_proc
+ li r10,FPUowner ; Displacement to float owner
+ add r11,r12,r11 ; Point to the owner per_proc
+
+tlfinvothr: lwarx r12,r10,r11 ; Get the owner
+
+ sub r0,r12,r3 ; Subtract one from the other
+ sub r8,r3,r12 ; Subtract the other from the one
+ or r8,r8,r0 ; Combine them
+ srawi r8,r8,31 ; Get a 0 if equal or -1 of not
+ and r12,r12,r8 ; Make 0 if same, unchanged if not
+ stwcx. r12,r10,r11 ; Try to invalidate it
+ bne-- tlfinvothr ; Try again if there was a collision...
+
+ mtmsr r9 ; Restore interruptions
+ isync ; Could be turning off floats here
+ blr ; Leave...
+
/*
* Altivec stuff is here. The techniques used are pretty identical to
* don't want to load any registers we don't have a copy of, we want to set them
* to zero instead.
*
+ * Note that there are some oddities here when we save a context we are using.
+ * It is really not too cool to do this, but what the hey... Anyway,
+ * we turn vectors and fpu off before we leave.
+ * The oddity is that if you use vectors after this, the
+ * savearea containing the context just saved will go away. So, bottom line is
+ * that don't use vectors until after you are done with the saved context.
+ *
*/
-ENTRY(vec_save, TAG_NO_FRAME_USED)
+ .align 5
+ .globl EXT(vec_save)
+
+LEXT(vec_save)
- mfmsr r0 ; Get the MSR
- rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Turn off vector forever
- rlwinm r2,r0,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; But do interrupts only for now
- oris r2,r2,hi16(MASK(MSR_VEC)) ; Enable the vector facility for now also
- mtmsr r2 ; Set the MSR
+
+ lis r2,hi16(MASK(MSR_VEC)) ; Get VEC
+ mfmsr r0 ; Get the MSR
+ ori r2,r2,lo16(MASK(MSR_FP)) ; Add in FP
+ andc r0,r0,r2 ; Force off VEC and FP
+ ori r2,r2,lo16(MASK(MSR_EE)) ; Clear EE
+ andc r2,r0,r2 ; Clear EE for now
+ oris r2,r2,hi16(MASK(MSR_VEC)) ; Enable the vector facility for now also
+ mtmsr r2 ; Set the MSR
isync
- mfsprg r6,0 ; Get the per_processor block
- lwz r12,PP_VMX_THREAD(r6) ; Get the thread that owns the vector
+ mfsprg r6,0 ; Get the per_processor block
+ lwz r12,VMXowner(r6) ; Get the context ID for owner
+
#if FPVECDBG
- mr r7,r0 ; (TEST/DEBUG)
- li r4,0 ; (TEST/DEBUG)
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- mr. r3,r12 ; (TEST/DEBUG)
- li r2,0x5F00 ; (TEST/DEBUG)
- li r5,0 ; (TEST/DEBUG)
- beq- noowneryeu ; (TEST/DEBUG)
- lwz r4,ACT_MACT_VMXlvl(r12) ; (TEST/DEBUG)
- lwz r5,ACT_MACT_VMX(r12) ; (TEST/DEBUG)
-
-noowneryeu: oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
- mr r0,r7 ; (TEST/DEBUG)
+ mr r7,r0 ; (TEST/DEBUG)
+ li r4,0 ; (TEST/DEBUG)
+ mr r10,r3 ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ mr. r3,r12 ; (TEST/DEBUG)
+ li r2,0x5F00 ; (TEST/DEBUG)
+ li r5,0 ; (TEST/DEBUG)
+ beq- noowneryeu ; (TEST/DEBUG)
+ lwz r4,VMXlevel(r12) ; (TEST/DEBUG)
+ lwz r5,VMXsave(r12) ; (TEST/DEBUG)
+
+noowneryeu: oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+ mr r0,r7 ; (TEST/DEBUG)
+ mr r3,r10 ; (TEST/DEBUG)
#endif
- mflr r2 ; Save the return address
- lwz r10,PP_CPU_DATA(r6) ; Get the CPU data pointer
- lhz r11,PP_CPU_NUMBER(r6) ; Get our CPU number
-
- mr. r12,r12 ; Anyone own the vector?
-
- lwz r10,CPU_ACTIVE_THREAD(r10) ; Get the pointer to the active thread
-
- beq- vsret ; Nobody owns the vector, no save required...
-
- lwz r10,THREAD_TOP_ACT(r10) ; Now get the activation that is running
- lwz r9,ACT_MACT_VMXcpu(r12) ; Get the last CPU to use this context
-
- cmplw r12,r10 ; Do we own the thread?
- cmplw cr1,r9,r11 ; Was the context for this processor?
- bne+ vsret ; Facility belongs to some other activation...
- li r3,0 ; Assume we need a fix-me-up
- beq- cr1,vsgoodcpu ; Facility last used on this processor...
- stw r3,PP_VMX_THREAD(r6) ; Clear owner because it was really on the other processor
- b vsret ; Bail now with no save...
-
-vsgoodcpu: lwz r3,ACT_MACT_VMX(r12) ; Get the current vector savearea for the thread
- lwz r9,ACT_MACT_VMXlvl(r12) ; Get our current level indicator
-
- cmplwi cr1,r3,0 ; Have we ever saved this facility context?
- beq- cr1,vsneedone ; Never saved it, so we need an area...
-
- lwz r8,SAVlvlvec(r3) ; Get the level this savearea is for
- cmplwi r8,1 ; See if this is a spare
- cmplw cr1,r9,r8 ; Correct level?
- beq+ vsusespare ; It is still live...
- beq- cr1,vsret ; The current level is already saved, bail out...
-
-vsneedone: li r3,0 ; Tell the routine to allocate an area if none found
- bl vsrchsave ; Find a free savearea
-
- mfsprg r6,0 ; Get back per_processor block
- oris r7,r7,hi16(SAVvmxvalid) ; Set the allocated bit
- lwz r12,PP_VMX_THREAD(r6) ; Get back our thread
- mtlr r2 ; Restore return
- lwz r8,ACT_MACT_VMX(r12) ; Get the current top vector savearea
- lwz r9,ACT_MACT_VMXlvl(r12) ; Get our current level indicator again
- stw r3,ACT_MACT_VMX(r12) ; Set this as the latest vector savearea for the thread
- stw r8,SAVprevec(r3) ; And then chain this in front
- stw r7,SAVflags(r3) ; Set the allocation flags
- stw r12,SAVact(r3) ; Make sure we point to the right guy
-
-vsusespare: stw r9,SAVlvlvec(r3) ; And set the level this savearea is for
- mfcr r2 ; Save non-volatile CRs
- lwz r10,liveVRS(r6) ; Get the right VRSave register
- lis r9,0x5555 ; Mask with odd bits set
- rlwinm r11,r10,1,0,31 ; Shift over 1
- ori r9,r9,0x5555 ; Finish mask
- or r12,r10,r11 ; After this, even bits show which lines to zap
-
- andc r11,r12,r9 ; Clear out odd bits
-
- la r6,savevr0(r3) ; Point to line 0
- rlwinm r4,r11,15,0,15 ; Move line 8-15 flags to high order odd bits
- la r9,savevrvalid(r3) ; Point to the saved register mask field
- or r4,r11,r4 ; Set the odd bits
- ; (bit 0 is line 0, bit 1 is line 8,
- ; bit 2 is line 1, bit 3 is line 9, etc.
- dcba br0,r9 ; Allocate the cache for it
- rlwimi r4,r10,16,16,31 ; Put vrsave 0 - 15 into positions 16 - 31
- la r7,savevr2(r3) ; Point to line 1
- mtcrf 255,r4 ; Load up the CRs
- stw r10,savevrvalid(r3) ; Save the validity information
- mr r8,r6 ; Start registers off
-;
-; Save the current vector state
-;
-
- bf 0,snol0 ; No line 0 to do...
- dcba br0,r6 ; Allocate cache line 0
-
-snol0:
- la r6,savevr4(r3) ; Point to line 2
- bf 2,snol1 ; No line 1 to do...
- dcba br0,r7 ; Allocate cache line 1
-
-snol1:
- la r7,savevr6(r3) ; Point to line 3
- bf 4,snol2 ; No line 2 to do...
- dcba br0,r6 ; Allocate cache line 2
-
-snol2:
- li r11,16 ; Get offset for odd registers
- bf 16,snovr0 ; Do not save VR0...
- stvxl v0,br0,r8 ; Save VR0
-
-snovr0:
- la r9,savevr2(r3) ; Point to V2/V3 pair
- bf 17,snovr1 ; Do not save VR1...
- stvxl v1,r11,r8 ; Save VR1
-
-snovr1:
- la r6,savevr8(r3) ; Point to line 4
- bf 6,snol3 ; No line 3 to do...
- dcba br0,r7 ; Allocate cache line 3
-
-snol3:
- la r8,savevr4(r3) ; Point to V4/V5 pair
- bf 18,snovr2 ; Do not save VR2...
- stvxl v2,br0,r9 ; Save VR2
-
-snovr2:
- bf 19,snovr3 ; Do not save VR3...
- stvxl v3,r11,r9 ; Save VR3
-
-snovr3:
-;
-; Note: CR4 is now free
-;
- la r7,savevr10(r3) ; Point to line 5
- bf 8,snol4 ; No line 4 to do...
- dcba br0,r6 ; Allocate cache line 4
-
-snol4:
- la r9,savevr6(r3) ; Point to R6/R7 pair
- bf 20,snovr4 ; Do not save VR4...
- stvxl v4,br0,r8 ; Save VR4
-
-snovr4:
- bf 21,snovr5 ; Do not save VR5...
- stvxl v5,r11,r8 ; Save VR5
-
-snovr5:
- mtcrf 0x08,r10 ; Set CRs for registers 16-19
- la r6,savevr12(r3) ; Point to line 6
- bf 10,snol5 ; No line 5 to do...
- dcba br0,r7 ; Allocate cache line 5
-
-snol5:
- la r8,savevr8(r3) ; Point to V8/V9 pair
- bf 22,snovr6 ; Do not save VR6...
- stvxl v6,br0,r9 ; Save VR6
-
-snovr6:
- bf 23,snovr7 ; Do not save VR7...
- stvxl v7,r11,r9 ; Save VR7
-
-snovr7:
-;
-; Note: CR5 is now free
-;
- la r7,savevr14(r3) ; Point to line 7
- bf 12,snol6 ; No line 6 to do...
- dcba br0,r6 ; Allocate cache line 6
+ mflr r2 ; Save the return address
+
+vsretry: mr. r12,r12 ; Anyone own the vector?
+ lhz r11,PP_CPU_NUMBER(r6) ; Get our CPU number
+ beq- vsret ; Nobody owns the vector, no save required...
-snol6:
- la r9,savevr10(r3) ; Point to V10/V11 pair
- bf 24,snovr8 ; Do not save VR8...
- stvxl v8,br0,r8 ; Save VR8
+ cmplw cr1,r3,r12 ; Is the specified context live?
-snovr8:
- bf 25,snovr9 ; Do not save VR9...
- stvxl v9,r11,r8 ; Save VR9
+ isync ; Force owner check first
+
+ lwz r9,VMXcpu(r12) ; Get the cpu that context was last on
+ bne- cr1,vsret ; Specified context is not live
-snovr9:
- mtcrf 0x04,r10 ; Set CRs for registers 20-23
- la r6,savevr16(r3) ; Point to line 8
- bf 14,snol7 ; No line 7 to do...
- dcba br0,r7 ; Allocate cache line 7
+ cmplw cr1,r9,r11 ; Was the context for this processor?
+ beq+ cr1,vsgoodcpu ; Facility last used on this processor...
+
+ b vsret ; Someone else claimed this...
-snol7:
- la r8,savevr12(r3) ; Point to V12/V13 pair
- bf 26,snovr10 ; Do not save VR10...
- stvxl v10,br0,r9 ; Save VR10
+ .align 5
-snovr10:
- bf 27,snovr11 ; Do not save VR11...
- stvxl v11,r11,r9 ; Save VR11
+vsgoodcpu: lwz r3,VMXsave(r12) ; Get the current vector savearea for the thread
+ lwz r10,liveVRS(r6) ; Get the right VRSave register
+ lwz r9,VMXlevel(r12) ; Get our current level indicator
-snovr11:
-
-;
-; Note: CR6 is now free
-;
- la r7,savevr18(r3) ; Point to line 9
- bf 1,snol8 ; No line 8 to do...
- dcba br0,r6 ; Allocate cache line 8
-
-snol8:
- la r9,savevr14(r3) ; Point to V14/V15 pair
- bf 28,snovr12 ; Do not save VR12...
- stvxl v12,br0,r8 ; Save VR12
-
-snovr12:
- bf 29,snovr13 ; Do not save VR13...
- stvxl v13,r11,r8 ; Save VR13
-
-snovr13:
- mtcrf 0x02,r10 ; Set CRs for registers 24-27
- la r6,savevr20(r3) ; Point to line 10
- bf 3,snol9 ; No line 9 to do...
- dcba br0,r7 ; Allocate cache line 9
-
-snol9:
- la r8,savevr16(r3) ; Point to V16/V17 pair
- bf 30,snovr14 ; Do not save VR14...
- stvxl v14,br0,r9 ; Save VR14
-
-snovr14:
- bf 31,snovr15 ; Do not save VR15...
- stvxl v15,r11,r9 ; Save VR15
-
-snovr15:
-;
-; Note: CR7 is now free
-;
- la r7,savevr22(r3) ; Point to line 11
- bf 5,snol10 ; No line 10 to do...
- dcba br0,r6 ; Allocate cache line 10
-snol10:
- la r9,savevr18(r3) ; Point to V18/V19 pair
- bf 16,snovr16 ; Do not save VR16...
- stvxl v16,br0,r8 ; Save VR16
+ cmplwi cr1,r3,0 ; Have we ever saved this facility context?
+ beq- cr1,vsneedone ; Never saved it, so we need an area...
-snovr16:
- bf 17,snovr17 ; Do not save VR17...
- stvxl v17,r11,r8 ; Save VR17
+ lwz r8,SAVlevel(r3) ; Get the level this savearea is for
+ mr. r10,r10 ; Is VRsave set to 0?
+ cmplw cr1,r9,r8 ; Correct level?
+ bne- cr1,vsneedone ; Different level, so we need to save...
-snovr17:
- mtcrf 0x01,r10 ; Set CRs for registers 28-31
-;
-; Note: All registers have been or are accounted for in CRs
-;
- la r6,savevr24(r3) ; Point to line 12
- bf 7,snol11 ; No line 11 to do...
- dcba br0,r7 ; Allocate cache line 11
-
-snol11:
- la r8,savevr20(r3) ; Point to V20/V21 pair
- bf 18,snovr18 ; Do not save VR18...
- stvxl v18,br0,r9 ; Save VR18
-
-snovr18:
- bf 19,snovr19 ; Do not save VR19...
- stvxl v19,r11,r9 ; Save VR19
-
-snovr19:
- la r7,savevr26(r3) ; Point to line 13
- bf 9,snol12 ; No line 12 to do...
- dcba br0,r6 ; Allocate cache line 12
-
-snol12:
- la r9,savevr22(r3) ; Point to V22/V23 pair
- bf 20,snovr20 ; Do not save VR20...
- stvxl v20,br0,r8 ; Save VR20
-
-snovr20:
- bf 21,snovr21 ; Do not save VR21...
- stvxl v21,r11,r8 ; Save VR21
-
-snovr21:
- la r6,savevr28(r3) ; Point to line 14
- bf 11,snol13 ; No line 13 to do...
- dcba br0,r7 ; Allocate cache line 13
-
-snol13:
- la r8,savevr24(r3) ; Point to V24/V25 pair
- bf 22,snovr22 ; Do not save VR22...
- stvxl v22,br0,r9 ; Save VR22
-
-snovr22:
- bf 23,snovr23 ; Do not save VR23...
- stvxl v23,r11,r9 ; Save VR23
-
-snovr23:
- la r7,savevr30(r3) ; Point to line 15
- bf 13,snol14 ; No line 14 to do...
- dcba br0,r6 ; Allocate cache line 14
-
-snol14:
- la r9,savevr26(r3) ; Point to V26/V27 pair
- bf 24,snovr24 ; Do not save VR24...
- stvxl v24,br0,r8 ; Save VR24
-
-snovr24:
- bf 25,snovr25 ; Do not save VR25...
- stvxl v25,r11,r8 ; Save VR25
-
-snovr25:
- bf 15,snol15 ; No line 15 to do...
- dcba br0,r7 ; Allocate cache line 15
-
-snol15:
-;
-; Note: All cache lines allocated now
-;
- la r8,savevr28(r3) ; Point to V28/V29 pair
- bf 26,snovr26 ; Do not save VR26...
- stvxl v26,br0,r9 ; Save VR26
-
-snovr26:
- bf 27,snovr27 ; Do not save VR27...
- stvxl v27,r11,r9 ; Save VR27
-
-snovr27:
- la r7,savevr30(r3) ; Point to V30/V31 pair
- bf 28,snovr28 ; Do not save VR28...
- stvxl v28,br0,r8 ; Save VR28
-
-snovr28:
- bf 29,snovr29 ; Do not save VR29...
- stvxl v29,r11,r8 ; Save VR29
-
-snovr29:
- mfvscr v27 ; Get the VSCR
- la r8,savevscr(r3) ; Point to the VSCR save area
- bf 30,snovr30 ; Do not save VR30...
- stvxl v30,br0,r7 ; Save VR30
-
-snovr30:
- dcba br0,r8 ; Allocate VSCR savearea
- bf 31,snovr31 ; Do not save VR31...
- stvxl v31,r11,r7 ; Save VR31
-
-snovr31:
- add r11,r11,r9 ; Point to V27s saved value
- stvxl v27,br0,r8 ; Save the VSCR
- bt 27,v27ok ; V27 has been saved and is marked as wanted
+ bne+ vsret ; VRsave is non-zero so we need to keep what is saved...
+
+ lwz r4,SAVprev+4(r3) ; Pick up the previous area
+ lwz r5,SAVlevel(r4) ; Get the level associated with save
+ stw r4,VMXsave(r12) ; Dequeue this savearea
+ li r4,0 ; Clear
+ stw r5,VMXlevel(r12) ; Save the level
+
+ stw r4,VMXowner(r12) ; Show no live context here
+ eieio
+
+vsbackout: mr r4,r0 ; restore the saved MSR
+ b EXT(save_ret_wMSR) ; Toss the savearea and return from there...
+
+ .align 5
+
+vsneedone: mr. r10,r10 ; Is VRsave set to 0?
+ beq- vsret ; Yeah, they do not care about any of them...
+
+ bl EXT(save_get) ; Get a savearea for the context
+
+ mfsprg r6,0 ; Get back per_processor block
+ li r4,SAVvector ; Get vector tag
+ lwz r12,VMXowner(r6) ; Get back our context ID
+ stb r4,SAVflags+2(r3) ; Mark this savearea as a vector
+ mr. r12,r12 ; See if we were disowned while away. Very, very small chance of it...
+ beq- vsbackout ; If disowned, just toss savearea...
+ lwz r4,facAct(r12) ; Get the activation associated with live context
+ lwz r8,VMXsave(r12) ; Get the current top vector savearea
+ stw r4,SAVact(r3) ; Indicate the right activation for this context
+ lwz r9,VMXlevel(r12) ; Get our current level indicator again
+ stw r3,VMXsave(r12) ; Set this as the most current floating point context
+ stw r8,SAVprev+4(r3) ; And then chain this in front
+
+ stw r9,SAVlevel(r3) ; Set level in savearea
+ mfcr r12 ; save CRs across call to vr_store
+ lwz r10,liveVRS(r6) ; Get the right VRSave register
+
+ bl vr_store ; store live VRs into savearea as required (uses r4-r11)
+
+ mtcrf 255,r12 ; Restore the non-volatile CRs
+ mtlr r2 ; restore return address
- lis r11,hi16(EXT(QNaNbarbarian)) ; V27 is not wanted, so get empty value
- ori r11,r11,lo16(EXT(QNaNbarbarian))
-
-v27ok: mtcrf 255,r2 ; Restore all non-volatile CRs
- lvxl v27,br0,r11 ; Restore or load empty value into V27 because we used it
-
-;
-; Save the current vector state into the savearea of the thread that owns it.
-;
-
-vsret: mtmsr r0 ; Put interrupts on if they were and vector off
+vsret: mtmsr r0 ; Put interrupts on if they were and vector off
isync
blr
*
*/
-ENTRY(vec_switch, TAG_NO_FRAME_USED)
+ .align 5
+ .globl EXT(vec_switch)
+
+LEXT(vec_switch)
#if DEBUG
-#if GDDBG
- mr r7,r4 ; Save input parameter
- lis r3,hi16(EXT(vec_trap_count)) ; Get address of vector trap counter
- ori r3,r3,lo16(EXT(vec_trap_count)) ; Get address of vector trap counter
- lwz r1,0(r3)
- lis r5,hi16(EXT(GratefulDeb)) ; Point to top of display
- ori r5,r5,lo16(EXT(GratefulDeb)) ; Put in bottom part
- addi r1,r1,1
- mtlr r5 ; Set link register
- stw r1,0(r3)
- mr r4,r1
- lis r3,1
- blrl ; Display count
- mr r4,r7 ; Restore the parameter
-#else
lis r3,hi16(EXT(vec_trap_count)) ; Get address of vector trap counter
ori r3,r3,lo16(EXT(vec_trap_count)) ; Get address of vector trap counter
lwz r1,0(r3)
addi r1,r1,1
stw r1,0(r3)
-#endif
#endif /* DEBUG */
- mfsprg r6,0 /* Get the per_processor block */
- mfmsr r19 /* Get the current MSR */
+ mfsprg r26,0 ; Get the per_processor block
+ mfmsr r19 ; Get the current MSR
+ mfsprg r17,1 ; Get the current thread
- lwz r10,PP_CPU_DATA(r6) /* Get the CPU data pointer */
- lwz r12,PP_VMX_THREAD(r6) /* Get the thread that owns the vector */
- lwz r10,CPU_ACTIVE_THREAD(r10) /* Get the pointer to the active thread */
- oris r19,r19,hi16(MASK(MSR_VEC)) /* Enable the vector feature */
- lwz r17,THREAD_TOP_ACT(r10) /* Now get the activation that is running */
+ mr r25,r4 ; Save the entry savearea
+ oris r19,r19,hi16(MASK(MSR_VEC)) ; Enable the vector feature
+ lwz r22,VMXowner(r26) ; Get the thread that owns the vector
+
+ mtmsr r19 ; Enable vector instructions
+ isync
-; R12 has the "old" activation
-; R17 has the "new" activation
+ lwz r27,ACT_MACT_PCB(r17) ; Get the current level
+ lwz r29,curctx(r17) ; Grab the current context anchor of the current thread
+
+; R22 has the "old" context anchor
+; R29 has the "new" context anchor
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F01 ; (TEST/DEBUG)
- mr r3,r12 ; (TEST/DEBUG)
- mr r5,r17 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r18,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r18 ; Restore it
- mfsprg r6,0 ; Get the per_processor block back
-#endif
+ lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F01 ; (TEST/DEBUG)
+ mr r3,r22 ; (TEST/DEBUG)
+ mr r5,r29 ; (TEST/DEBUG)
+ oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
- mr. r12,r12 ; See if there is any live vector status
-
- lhz r18,PP_CPU_NUMBER(r6) ; Get our CPU number
-
- mtmsr r19 /* Set vector available */
- isync
-
+
+ lhz r16,PP_CPU_NUMBER(r26) ; Get the current CPU number
- beq- vsnosave ; No live context, so nothing to save...
-
- lwz r19,ACT_MACT_VMXcpu(r12) ; Get the "old" active CPU
- lwz r15,ACT_MACT_PCB(r12) ; Get the current level of the "old" one
- cmplw r18,r19 ; Check the CPU that the old context is live on
- lwz r14,ACT_MACT_VMX(r12) ; Point to the top of the old context stack
- bne- vsnosave ; Context is not live if used on a different CPU...
- lwz r13,ACT_MACT_VMXlvl(r12) ; Get the "old" active level
+vsvretry: mr. r22,r22 ; See if there is any live vector status
-;
-; First, check to see if all we are doing is enabling because the
-; "new" context is live.
-;
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F02 ; (TEST/DEBUG)
- mr r1,r15 ; (TEST/DEBUG)
- mr r3,r13 ; (TEST/DEBUG)
- mr r5,r14 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r8,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r8 ; Restore it
-#endif
-#endif
+ beq- vsnosave ; No live context, so nothing to save...
- cmplw cr1,r12,r17 ; Is the "old" activation and the "new" the same?
- cmplwi cr2,r14,0 ; Is there any saved context on the "old" activation?
- bne+ cr1,vsmstsave ; The activations are different so "old" context must be saved...
+ isync ; Make sure we see this in the right order
+
+ lwz r30,VMXsave(r22) ; Get the top savearea
+ cmplw cr2,r22,r29 ; Are both old and new the same context?
+ lwz r18,VMXcpu(r22) ; Get the last CPU we ran on
+ cmplwi cr1,r30,0 ; Anything saved yet?
+ cmplw r18,r16 ; Make sure we are on the right processor
+ lwz r31,VMXlevel(r22) ; Get the context level
+
+ lwz r10,liveVRS(r26) ; Get the right VRSave register
+ bne- vsnosave ; No, not on the same processor...
+
;
-; Here we know that both the "old" and "new" activations are the same. We will
-; check the current level and active levels. If they are the same, the context is
-; already live, so all we do is turn on the facility and invalidate the top
-; savearea.
-;
-; If the current level, the active level, and the top savearea level are the
-; same, then the context was saved as part of a thread context switch and neither
-; needs saving or restoration.
-;
-; In all other cases, the context must be saved unless we are just re-enabling
-; vector.
+; Check to see if the live context has already been saved.
+; Also check to see if all we are here just to re-enable the MSR
+; and handle specially if so.
;
- cmplw r13,r15 ; Are the levels the same?
- cmplwi cr2,r14,0 ; Is there any saved context?
- bne- vsmstsave ; Levels are different, we need to save...
-
- beq- cr2,vrenable ; No saved context at all, enable and go...
-
- lwz r20,SAVlvlvec(r14) ; Get the level of the top savearea
-
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F03 ; (TEST/DEBUG)
- mr r3,r15 ; (TEST/DEBUG)
- mr r5,r20 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r8,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r8 ; Restore it
-#endif
-#endif
- cmplw r15,r20 ; Is the top level the same as the current?
- li r0,1 ; Get the invalid flag
- bne- vrenable ; Not the same, just enable and go...
+ cmplw r31,r27 ; See if the current and active levels are the same
+ crand cr0_eq,cr2_eq,cr0_eq ; Remember if both the levels and contexts are the same
+ li r8,0 ; Clear this
- stw r0,SAVlvlvec(r14) ; Invalidate that top savearea
+ beq- vsthesame ; New and old are the same, just go enable...
- b vrenable ; Then enable and go...
-
-;
-; We need to save the "old" context here. The LIFO queueing scheme works
-; out for all cases because if both the "new" and "old" activations are the
-; same, there can not be any saved state to load. the "new" level is
-; truely new.
-;
-; When we save the context, we either use a new savearea, or the free
-; one that is cached at the head of the list.
+ cmplwi cr2,r10,0 ; Check VRSave to see if we really need to save anything...
+ beq- cr1,vsmstsave ; Not saved yet, go do it...
-vsmstsave: beq- cr2,vsgetsave ; There is no possible cached save area
+ lwz r11,SAVlevel(r30) ; Get the level of top saved context
- lwz r5,SAVlvlvec(r14) ; Get the level of first facility savearea
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F04 ; (TEST/DEBUG)
- mr r3,r15 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r8,r4 ; Save this
- mr r7,r5 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r8 ; Restore it
- mr r5,r7 ; Restore it
-#endif
-#endif
- mr r3,r14 ; Assume we are invalid
- cmplwi r5,1 ; Is it invalid?
- cmplw cr1,r5,r13 ; Is the SA level the active one?
- beq+ vsusecache ; Invalid, just use it...
- beq- cr1,vsnosave ; The SA level is active, it is already saved...
-
-vsgetsave: mr r3,r4 ; Use the interrupt save as the context savearea if none cached
+ cmplw r31,r11 ; Are live and saved the same?
+
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F05 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r8,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r8 ; Restore it
- mr r3,r8 ; This too
-#endif
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F02 ; (TEST/DEBUG)
+ mr r3,r30 ; (TEST/DEBUG)
+ mr r5,r31 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
+
+ bne- vsmstsave ; Live context has not been saved yet...
+
+ bne- cr2,vsnosave ; Live context saved and VRSave not 0, no save and keep context...
- bl vsrchsave ; Find a free savearea
+ lwz r4,SAVprev+4(r30) ; Pick up the previous area
+ li r5,0 ; Assume this is the only one (which should be the ususal case)
+ mr. r4,r4 ; Was this the only one?
+ stw r4,VMXsave(r22) ; Dequeue this savearea
+ beq+ vsonlyone ; This was the only one...
+ lwz r5,SAVlevel(r4) ; Get the level associated with previous save
- stw r3,ACT_MACT_VMX(r12) ; Set this as the latest context savearea for the thread
- mfsprg r6,0 ; Get back per_processor block
- stw r14,SAVprevec(r3) ; And then chain this in front
- oris r7,r7,hi16(SAVvmxvalid) ; Set the allocated bit
- stw r12,SAVact(r3) ; Make sure we point to the right guy
- stw r7,SAVflags(r3) ; Set the allocation flags
+vsonlyone: stw r5,VMXlevel(r22) ; Save the level
+ stw r8,VMXowner(r26) ; Clear owner
+ eieio
+ mr r3,r30 ; Copy the savearea we are tossing
+ bl EXT(save_ret) ; Toss the savearea
+ b vsnosave ; Go load up the context...
-vsusecache: la r11,savevr0(r3) ; Point to the 1st line in area
- stw r13,SAVlvlvec(r3) ; Set this context level
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F06 ; (TEST/DEBUG)
- mr r5,r13 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- mr r10,r3
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r8,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r8 ; Restore it
- mr r3,r10
- mfsprg r6,0 ; Get back per_processor block
-#endif
-#endif
+ .align 5
-vsgotsave:
- lwz r10,liveVRS(r6) ; Get the right VRSave register
- lis r9,0x5555 ; Mask with odd bits set
- rlwinm r11,r10,1,0,31 ; Shift over 1
- ori r9,r9,0x5555 ; Finish mask
- or r12,r10,r11 ; After this, even bits show which lines to zap
-
- stw r13,SAVlvlvec(r3) ; Set the savearea level
- andc r13,r12,r9 ; Clear out odd bits
-
- la r20,savevr0(r3) ; Point to line 0
- rlwinm r24,r13,15,0,15 ; Move line 8-15 flags to high order odd bits
- la r23,savevrvalid(r3) ; Point to the saved register mask field
- or r24,r13,r24 ; Set the odd bits
- ; (bit 0 is line 0, bit 1 is line 8,
- ; bit 2 is line 1, bit 3 is line 9, etc.
- dcba br0,r23 ; Allocate the cache for it
- rlwimi r24,r10,16,16,31 ; Put vrsave 0 - 15 into positions 16 - 31
- la r21,savevr2(r3) ; Point to line 1
- mtcrf 255,r24 ; Load up the CRs
- stw r10,savevrvalid(r3) ; Save the validity information
- mr r22,r20 ; Start registers off
-;
-; Save the current vector state
-;
-
- bf 0,nol0 ; No line 0 to do...
- dcba br0,r20 ; Allocate cache line 0
-
-nol0:
- la r20,savevr4(r3) ; Point to line 2
- bf 2,nol1 ; No line 1 to do...
- dcba br0,r21 ; Allocate cache line 1
-
-nol1:
- la r21,savevr6(r3) ; Point to line 3
- bf 4,nol2 ; No line 2 to do...
- dcba br0,r20 ; Allocate cache line 2
-
-nol2:
- li r30,16 ; Get offset for odd registers
- bf 16,novr0 ; Do not save VR0...
- stvxl v0,br0,r22 ; Save VR0
-
-novr0:
- la r23,savevr2(r3) ; Point to V2/V3 pair
- bf 17,novr1 ; Do not save VR1...
- stvxl v1,r30,r22 ; Save VR1
-
-novr1:
- la r20,savevr8(r3) ; Point to line 4
- bf 6,nol3 ; No line 3 to do...
- dcba br0,r21 ; Allocate cache line 3
-
-nol3:
- la r22,savevr4(r3) ; Point to V4/V5 pair
- bf 18,novr2 ; Do not save VR2...
- stvxl v2,br0,r23 ; Save VR2
-
-novr2:
- bf 19,novr3 ; Do not save VR3...
- stvxl v3,r30,r23 ; Save VR3
-
-novr3:
-;
-; Note: CR4 is now free
+
+vsmstsave: stw r8,VMXowner(r26) ; Clear owner
+ eieio
+ beq- cr2,vsnosave ; The VRSave was 0, so there is nothing to save...
+
+ bl EXT(save_get) ; Go get a savearea
+
+ mr. r31,r31 ; Are we saving the user state?
+ la r15,VMXsync(r22) ; Point to the sync word
+ beq++ vswusave ; Yeah, no need for lock...
;
- la r21,savevr10(r3) ; Point to line 5
- bf 8,nol4 ; No line 4 to do...
- dcba br0,r20 ; Allocate cache line 4
-
-nol4:
- la r23,savevr6(r3) ; Point to R6/R7 pair
- bf 20,novr4 ; Do not save VR4...
- stvxl v4,br0,r22 ; Save VR4
-
-novr4:
- bf 21,novr5 ; Do not save VR5...
- stvxl v5,r30,r22 ; Save VR5
-
-novr5:
- mtcrf 0x08,r10 ; Set CRs for registers 16-19
- la r20,savevr12(r3) ; Point to line 6
- bf 10,nol5 ; No line 5 to do...
- dcba br0,r21 ; Allocate cache line 5
-
-nol5:
- la r22,savevr8(r3) ; Point to V8/V9 pair
- bf 22,novr6 ; Do not save VR6...
- stvxl v6,br0,r23 ; Save VR6
-
-novr6:
- bf 23,novr7 ; Do not save VR7...
- stvxl v7,r30,r23 ; Save VR7
-
-novr7:
+; Here we make sure that the live context is not tossed while we are
+; trying to push it. This can happen only for kernel context and
+; then only by a race with act_machine_sv_free.
;
-; Note: CR5 is now free
+; We only need to hold this for a very short time, so no sniffing needed.
+; If we find any change to the level, we just abandon.
;
- la r21,savevr14(r3) ; Point to line 7
- bf 12,nol6 ; No line 6 to do...
- dcba br0,r20 ; Allocate cache line 6
-
-nol6:
- la r23,savevr10(r3) ; Point to V10/V11 pair
- bf 24,novr8 ; Do not save VR8...
- stvxl v8,br0,r22 ; Save VR8
-
-novr8:
- bf 25,novr9 ; Do not save VR9...
- stvxl v9,r30,r22 ; Save VR9
-
-novr9:
- mtcrf 0x04,r10 ; Set CRs for registers 20-23
- la r20,savevr16(r3) ; Point to line 8
- bf 14,nol7 ; No line 7 to do...
- dcba br0,r21 ; Allocate cache line 7
+vswsync: lwarx r19,0,r15 ; Get the sync word
+ li r0,1 ; Get the lock
+ cmplwi cr1,r19,0 ; Is it unlocked?
+ stwcx. r0,0,r15 ; Store lock and test reservation
+ cror cr0_eq,cr1_eq,cr0_eq ; Combine lost reservation and previously locked
+ bne-- vswsync ; Try again if lost reservation or locked...
+
+ isync ; Toss speculation
-nol7:
- la r22,savevr12(r3) ; Point to V12/V13 pair
- bf 26,novr10 ; Do not save VR10...
- stvxl v10,br0,r23 ; Save VR10
+ lwz r0,VMXlevel(r22) ; Pick up the level again
+ li r7,0 ; Get unlock value
+ cmplw r0,r31 ; Same level?
+ beq++ vswusave ; Yeah, we expect it to be...
-novr10:
- bf 27,novr11 ; Do not save VR11...
- stvxl v11,r30,r23 ; Save VR11
+ stw r7,VMXsync(r22) ; Unlock lock. No need to sync here
-novr11:
+ bl EXT(save_ret) ; Toss save area because we are abandoning save
+ b vsnosave ; Skip the save...
-;
-; Note: CR6 is now free
-;
- la r21,savevr18(r3) ; Point to line 9
- bf 1,nol8 ; No line 8 to do...
- dcba br0,r20 ; Allocate cache line 8
-
-nol8:
- la r23,savevr14(r3) ; Point to V14/V15 pair
- bf 28,novr12 ; Do not save VR12...
- stvxl v12,br0,r22 ; Save VR12
-
-novr12:
- bf 29,novr13 ; Do not save VR13...
- stvxl v13,r30,r22 ; Save VR13
-
-novr13:
- mtcrf 0x02,r10 ; Set CRs for registers 24-27
- la r20,savevr20(r3) ; Point to line 10
- bf 3,nol9 ; No line 9 to do...
- dcba br0,r21 ; Allocate cache line 9
-
-nol9:
- la r22,savevr16(r3) ; Point to V16/V17 pair
- bf 30,novr14 ; Do not save VR14...
- stvxl v14,br0,r23 ; Save VR14
-
-novr14:
- bf 31,novr15 ; Do not save VR15...
- stvxl v15,r30,r23 ; Save VR15
-
-novr15:
-;
-; Note: CR7 is now free
-;
- la r21,savevr22(r3) ; Point to line 11
- bf 5,nol10 ; No line 10 to do...
- dcba br0,r20 ; Allocate cache line 10
-
-nol10:
- la r23,savevr18(r3) ; Point to V18/V19 pair
- bf 16,novr16 ; Do not save VR16...
- stvxl v16,br0,r22 ; Save VR16
+ .align 5
+
+vswusave: lwz r12,facAct(r22) ; Get the activation associated with the context
+ stw r3,VMXsave(r22) ; Set this as the latest context savearea for the thread
+ mr. r31,r31 ; Check again if we were user level
+ stw r30,SAVprev+4(r3) ; Point us to the old context
+ stw r31,SAVlevel(r3) ; Tag our level
+ li r7,SAVvector ; Get the vector ID
+ stw r12,SAVact(r3) ; Make sure we point to the right guy
+ stb r7,SAVflags+2(r3) ; Set that we have a vector save area
+
+ li r7,0 ; Get the unlock value
+
+ beq-- vswnulock ; Skip unlock if user (we did not lock it)...
+ eieio ; Make sure that these updates make it out
+ stw r7,VMXsync(r22) ; Unlock it.
-novr16:
- bf 17,novr17 ; Do not save VR17...
- stvxl v17,r30,r22 ; Save VR17
+vswnulock:
+
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F03 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
+
+ lwz r10,liveVRS(r26) ; Get the right VRSave register
+ bl vr_store ; store VRs into savearea according to vrsave (uses r4-r11)
-novr17:
- mtcrf 0x01,r10 ; Set CRs for registers 28-31
+
;
-; Note: All registers have been or are accounted for in CRs
+; The context is all saved now and the facility is free.
;
- la r20,savevr24(r3) ; Point to line 12
- bf 7,nol11 ; No line 11 to do...
- dcba br0,r21 ; Allocate cache line 11
-
-nol11:
- la r22,savevr20(r3) ; Point to V20/V21 pair
- bf 18,novr18 ; Do not save VR18...
- stvxl v18,br0,r23 ; Save VR18
-
-novr18:
- bf 19,novr19 ; Do not save VR19...
- stvxl v19,r30,r23 ; Save VR19
-
-novr19:
- la r21,savevr26(r3) ; Point to line 13
- bf 9,nol12 ; No line 12 to do...
- dcba br0,r20 ; Allocate cache line 12
-
-nol12:
- la r23,savevr22(r3) ; Point to V22/V23 pair
- bf 20,novr20 ; Do not save VR20...
- stvxl v20,br0,r22 ; Save VR20
-
-novr20:
- bf 21,novr21 ; Do not save VR21...
- stvxl v21,r30,r22 ; Save VR21
-
-novr21:
- la r20,savevr28(r3) ; Point to line 14
- bf 11,nol13 ; No line 13 to do...
- dcba br0,r21 ; Allocate cache line 13
-
-nol13:
- la r22,savevr24(r3) ; Point to V24/V25 pair
- bf 22,novr22 ; Do not save VR22...
- stvxl v22,br0,r23 ; Save VR22
-
-novr22:
- bf 23,novr23 ; Do not save VR23...
- stvxl v23,r30,r23 ; Save VR23
-
-novr23:
- la r21,savevr30(r3) ; Point to line 15
- bf 13,nol14 ; No line 14 to do...
- dcba br0,r20 ; Allocate cache line 14
-
-nol14:
- la r23,savevr26(r3) ; Point to V26/V27 pair
- bf 24,novr24 ; Do not save VR24...
- stvxl v24,br0,r22 ; Save VR24
-
-novr24:
- bf 25,novr25 ; Do not save VR25...
- stvxl v25,r30,r22 ; Save VR25
-
-novr25:
- bf 15,nol15 ; No line 15 to do...
- dcba br0,r21 ; Allocate cache line 15
-
-nol15:
+; If we do not we need to fill the registers with junk, because this level has
+; never used them before and some thieving bastard could hack the old values
+; of some thread! Just imagine what would happen if they could! Why, nothing
+; would be safe! My God! It is terrifying!
;
-; Note: All cache lines allocated now
+; Also, along the way, thanks to Ian Ollmann, we generate the 0x7FFFDEAD (QNaNbarbarian)
+; constant that we may need to fill unused vector registers.
;
- la r22,savevr28(r3) ; Point to V28/V29 pair
- bf 26,novr26 ; Do not save VR26...
- stvxl v26,br0,r23 ; Save VR26
-
-novr26:
- bf 27,novr27 ; Do not save VR27...
- stvxl v27,r30,r23 ; Save VR27
-
-novr27:
- la r23,savevr30(r3) ; Point to V30/V31 pair
- bf 28,novr28 ; Do not save VR28...
- stvxl v28,br0,r22 ; Save VR28
-
-novr28:
- mfvscr v27 ; Get the VSCR
- bf 29,novr29 ; Do not save VR29...
- stvxl v29,r30,r22 ; Save VR29
-
-novr29:
- la r22,savevscr(r3) ; Point to the VSCR save area
- bf 30,novr30 ; Do not save VR30...
- stvxl v30,br0,r23 ; Save VR30
-
-novr30:
- dcba br0,r22 ; Allocate VSCR savearea
- bf 31,novr31 ; Do not save VR31...
- stvxl v31,r30,r23 ; Save VR31
-
-novr31:
- stvxl v27,br0,r22 ; Save the VSCR
-
-/*
- * Now check out the current thread and see if we need to load up his context.
- * If we do (and this should be the normal case), do it and then release the
- * savearea.
- *
- * If we don't (remember, we already took care of the case where we just enable
- * the vector), we need to fill the registers with garbage, because this thread has
- * never used them before and some thieving bastard could hack the old values
- * of some thread! Just imagine what would happen if they could! Why, nothing
- * would be safe! My Gosh! It's terrifying!
- */
-vsnosave: lwz r15,ACT_MACT_PCB(r17) ; Get the current level of the "new" one
- lwz r14,ACT_MACT_VMX(r17) ; Point to the top of the "new" context stack
- lwz r13,ACT_MACT_VMXlvl(r17) ; Get the "new" active level
+
+vsnosave: vspltisb v31,-10 ; Get 0xF6F6F6F6
+ lwz r15,ACT_MACT_PCB(r17) ; Get the current level of the "new" one
+ vspltisb v30,5 ; Get 0x05050505
+ lwz r19,VMXcpu(r29) ; Get the last CPU we ran on
+ vspltish v29,4 ; Get 0x00040004
+ lwz r14,VMXsave(r29) ; Point to the top of the "new" context stack
+ vrlb v31,v31,v30 ; Get 0xDEDEDEDE
+
+ stw r16,VMXcpu(r29) ; Claim context for us
+ eieio
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F07 ; (TEST/DEBUG)
- mr r1,r15 ; (TEST/DEBUG)
- mr r3,r14 ; (TEST/DEBUG)
- mr r5,r13 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
+ lwz r13,VMXlevel(r29) ; (TEST/DEBUG)
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F04 ; (TEST/DEBUG)
+ mr r1,r15 ; (TEST/DEBUG)
+ mr r3,r14 ; (TEST/DEBUG)
+ mr r5,r13 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
+
+ lis r18,hi16(EXT(per_proc_info)) ; Set base per_proc
+ vspltisb v28,-2 ; Get 0xFEFEFEFE
+ mulli r19,r19,ppSize ; Find offset to the owner per_proc
+ vsubuhm v31,v31,v29 ; Get 0xDEDADEDA
+ ori r18,r18,lo16(EXT(per_proc_info)) ; Set base per_proc
+ vpkpx v30,v28,v3 ; Get 0x7FFF7FFF
+ li r16,VMXowner ; Displacement to vector owner
+ add r19,r18,r19 ; Point to the owner per_proc
+ vrlb v31,v31,v29 ; Get 0xDEADDEAD
+
+vsinvothr: lwarx r18,r16,r19 ; Get the owner
+
+ sub r0,r18,r29 ; Subtract one from the other
+ sub r11,r29,r18 ; Subtract the other from the one
+ or r11,r11,r0 ; Combine them
+ srawi r11,r11,31 ; Get a 0 if equal or -1 of not
+ and r18,r18,r11 ; Make 0 if same, unchanged if not
+ stwcx. r18,r16,r19 ; Try to invalidate it
+ bne-- vsinvothr ; Try again if there was a collision...
+
+ cmplwi cr1,r14,0 ; Do we possibly have some context to load?
+ vmrghh v31,v30,v31 ; Get 0x7FFFDEAD. V31 keeps this value until the bitter end
+ stw r15,VMXlevel(r29) ; Set the "new" active level
+ eieio
+ stw r29,VMXowner(r26) ; Mark us as having the live context
- cmplwi cr1,r14,0 ; Do we possibly have some context to load?
- stw r15,ACT_MACT_VMXlvl(r17) ; Set the "new" active level
- la r23,savevscr(r14) ; Point to the VSCR
- stw r18,ACT_MACT_VMXcpu(r17) ; Set the active CPU
- la r20,savevr0(r14) ; Point to first line to bring in
- stw r17,PP_VMX_THREAD(r6) ; Store current thread address in vmx_thread to claim vector for thread
- beq- cr1,ProtectTheAmericanWay ; Nothing to restore, first time use...
- lwz r0,SAVlvlvec(r14) ; Get the level of first facility savearea
- cmplw r0,r15 ; Top level correct to load?
- bne- ProtectTheAmericanWay ; No, go initialize...
+ beq-- cr1,ProtectTheAmericanWay ; Nothing to restore, first time use...
+
+ lwz r3,SAVprev+4(r14) ; Get the previous context
+ lwz r0,SAVlevel(r14) ; Get the level of first facility savearea
+ cmplw r0,r15 ; Top level correct to load?
+ bne-- ProtectTheAmericanWay ; No, go initialize...
+ stw r3,VMXsave(r29) ; Pop the context (we will toss the savearea later)
+
#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F08 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- mr r8,r3
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r22,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r22 ; Restore it
- mr r3,r8
-#endif
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F05 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
#endif
- li r0,1 ; Get the level invalid indication
- lwz r22,savevrsave(r4) ; Get the most current VRSAVE
- lwz r10,savevrvalid(r14) ; Get the valid VRs in the savearea
- lis r9,0x5555 ; Mask with odd bits set
- and r10,r10,r22 ; Figure out just what registers need to be loaded
- ori r9,r9,0x5555 ; Finish mask
- rlwinm r11,r10,1,0,31 ; Shift over 1
- stw r0,SAVlvlvec(r14) ; Mark the savearea invalid because we are activating again
- or r12,r10,r11 ; After this, even bits show which lines to touch
- dcbt br0,r23 ; Touch in the VSCR
- andc r13,r12,r9 ; Clear out odd bits
-
- la r20,savevr0(r14) ; Point to line 0
- rlwinm r3,r13,15,0,15 ; Move line 8-15 flags to high order odd bits
- la r21,savevr2(r3) ; Point to line 1
- or r3,r13,r3 ; Set the odd bits
- ; (bit 0 is line 0, bit 1 is line 8,
- ; bit 2 is line 1, bit 3 is line 9, etc.
- lvxl v31,br0,r23 ; Get the VSCR
- rlwimi r3,r10,16,16,31 ; Put vrsave 0 - 15 into positions 16 - 31
- mtvscr v31 ; Slam the VSCR value
- mtcrf 255,r3 ; Load up the CRs
- mr r22,r20 ; Start registers off
-;
-; Load the new vector state
-;
-
- bf 0,lnol0 ; No line 0 to do...
- dcbt br0,r20 ; Touch cache line 0
-
-lnol0:
- la r20,savevr4(r14) ; Point to line 2
- bf 2,lnol1 ; No line 1 to do...
- dcbt br0,r21 ; Touch cache line 1
-
-lnol1:
- la r21,savevr6(r14) ; Point to line 3
- bf 4,lnol2 ; No line 2 to do...
- dcbt br0,r20 ; Touch cache line 2
-
-lnol2:
- li r30,16 ; Get offset for odd registers
- bf 16,lnovr0 ; Do not restore VR0...
- lvxl v0,br0,r22 ; Restore VR0
-
-lnovr0:
- la r23,savevr2(r14) ; Point to V2/V3 pair
- bf 17,lnovr1 ; Do not restore VR1...
- lvxl v1,r30,r22 ; Restore VR1
-
-lnovr1:
- la r20,savevr8(r14) ; Point to line 4
- bf 6,lnol3 ; No line 3 to do...
- dcbt br0,r21 ; Touch cache line 3
-
-lnol3:
- la r22,savevr4(r14) ; Point to V4/V5 pair
- bf 18,lnovr2 ; Do not restore VR2...
- lvxl v2,br0,r23 ; Restore VR2
-
-lnovr2:
- bf 19,lnovr3 ; Do not restore VR3...
- lvxl v3,r30,r23 ; Restore VR3
-
-lnovr3:
-;
-; Note: CR4 is now free
-;
- la r21,savevr10(r14) ; Point to line 5
- bf 8,lnol4 ; No line 4 to do...
- dcbt br0,r20 ; Touch cache line 4
-
-lnol4:
- la r23,savevr6(r14) ; Point to R6/R7 pair
- bf 20,lnovr4 ; Do not restore VR4...
- lvxl v4,br0,r22 ; Restore VR4
-
-lnovr4:
- bf 21,lnovr5 ; Do not restore VR5...
- lvxl v5,r30,r22 ; Restore VR5
-
-lnovr5:
- mtcrf 0x08,r10 ; Set CRs for registers 16-19
- la r20,savevr12(r14) ; Point to line 6
- bf 10,lnol5 ; No line 5 to do...
- dcbt br0,r21 ; Touch cache line 5
-
-lnol5:
- la r22,savevr8(r14) ; Point to V8/V9 pair
- bf 22,lnovr6 ; Do not restore VR6...
- lvxl v6,br0,r23 ; Restore VR6
-
-lnovr6:
- bf 23,lnovr7 ; Do not restore VR7...
- lvxl v7,r30,r23 ; Restore VR7
-
-lnovr7:
-;
-; Note: CR5 is now free
-;
- la r21,savevr14(r14) ; Point to line 7
- bf 12,lnol6 ; No line 6 to do...
- dcbt br0,r20 ; Touch cache line 6
-
-lnol6:
- la r23,savevr10(r14) ; Point to V10/V11 pair
- bf 24,lnovr8 ; Do not restore VR8...
- lvxl v8,br0,r22 ; Restore VR8
+ lwz r10,savevrvalid(r14) ; Get the valid VRs in the savearea
+ lwz r22,savevrsave(r25) ; Get the most current VRSAVE
+ and r10,r10,r22 ; Figure out just what registers need to be loaded
+ mr r3,r14 ; r3 <- ptr to savearea with VRs
+ bl vr_load ; load VRs from save area based on vrsave in r10
+
+ bl EXT(save_ret) ; Toss the save area after loading VRs
+
+vrenable: lwz r8,savesrr1+4(r25) ; Get the msr of the interrupted guy
+ oris r8,r8,hi16(MASK(MSR_VEC)) ; Enable the vector facility
+ lwz r10,ACT_MACT_SPF(r17) ; Get the act special flags
+ lwz r11,spcFlags(r26) ; Get per_proc spec flags cause not in sync with act
+ oris r10,r10,hi16(vectorUsed|vectorCng) ; Set that we used vectors
+ oris r11,r11,hi16(vectorUsed|vectorCng) ; Set that we used vectors
+ rlwinm. r0,r8,0,MSR_PR_BIT,MSR_PR_BIT ; See if we are doing this for user state
+ stw r8,savesrr1+4(r25) ; Set the msr of the interrupted guy
+ mr r3,r25 ; Pass virtual address of the savearea
+ beq- vrnuser ; We are not user state...
+ stw r10,ACT_MACT_SPF(r17) ; Set the activation copy
+ stw r11,spcFlags(r26) ; Set per_proc copy
+
+vrnuser:
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F07 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
+ b EXT(exception_exit) ; Exit to the fray...
+
+/*
+ * Initialize the registers to some bogus value
+ */
+
+ProtectTheAmericanWay:
-lnovr8:
- bf 25,lnovr9 ; Do not save VR9...
- lvxl v9,r30,r22 ; Restore VR9
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F06 ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
-lnovr9:
- mtcrf 0x04,r10 ; Set CRs for registers 20-23
- la r20,savevr16(r14) ; Point to line 8
- bf 14,lnol7 ; No line 7 to do...
- dcbt br0,r21 ; Touch cache line 7
+ vor v0,v31,v31 ; Copy into the next register
+ vor v1,v31,v31 ; Copy into the next register
+ vor v2,v31,v31 ; Copy into the next register
+ vor v3,v31,v31 ; Copy into the next register
+ vor v4,v31,v31 ; Copy into the next register
+ vor v5,v31,v31 ; Copy into the next register
+ vor v6,v31,v31 ; Copy into the next register
+ vor v7,v31,v31 ; Copy into the next register
+ vor v8,v31,v31 ; Copy into the next register
+ vor v9,v31,v31 ; Copy into the next register
+ vor v10,v31,v31 ; Copy into the next register
+ vor v11,v31,v31 ; Copy into the next register
+ vor v12,v31,v31 ; Copy into the next register
+ vor v13,v31,v31 ; Copy into the next register
+ vor v14,v31,v31 ; Copy into the next register
+ vor v15,v31,v31 ; Copy into the next register
+ vor v16,v31,v31 ; Copy into the next register
+ vor v17,v31,v31 ; Copy into the next register
+ vor v18,v31,v31 ; Copy into the next register
+ vor v19,v31,v31 ; Copy into the next register
+ vor v20,v31,v31 ; Copy into the next register
+ vor v21,v31,v31 ; Copy into the next register
+ vor v22,v31,v31 ; Copy into the next register
+ vor v23,v31,v31 ; Copy into the next register
+ vor v24,v31,v31 ; Copy into the next register
+ vor v25,v31,v31 ; Copy into the next register
+ vor v26,v31,v31 ; Copy into the next register
+ vor v27,v31,v31 ; Copy into the next register
+ vor v28,v31,v31 ; Copy into the next register
+ vor v29,v31,v31 ; Copy into the next register
+ vor v30,v31,v31 ; Copy into the next register
+ b vrenable ; Finish setting it all up...
+
+
+
+;
+; We get here when we are switching to the same context at the same level and the context
+; is still live. Essentially, all we are doing is turning on the faility. It may have
+; gotten turned off due to doing a context save for the current level or a context switch
+; back to the live guy.
+;
+
+ .align 5
+
+vsthesame:
+
+#if FPVECDBG
+ lis r0,hi16(CutTrace) ; (TEST/DEBUG)
+ li r2,0x5F0A ; (TEST/DEBUG)
+ oris r0,r0,lo16(CutTrace) ; (TEST/DEBUG)
+ sc ; (TEST/DEBUG)
+#endif
+ beq- cr1,vrenable ; Not saved yet, nothing to pop, go enable and exit...
-lnol7:
- la r22,savevr12(r14) ; Point to V12/V13 pair
- bf 26,lnovr10 ; Do not restore VR10...
- lvxl v10,br0,r23 ; Restore VR10
+ lwz r11,SAVlevel(r30) ; Get the level of top saved context
+ lwz r14,SAVprev+4(r30) ; Get the previous savearea
-lnovr10:
- bf 27,lnovr11 ; Do not restore VR11...
- lvxl v11,r30,r23 ; Restore VR11
+ cmplw r11,r31 ; Are live and saved the same?
+
+ bne+ vrenable ; Level not the same, nothing to pop, go enable and exit...
-lnovr11:
+ mr r3,r30 ; Get the old savearea (we popped it before)
+ stw r11,VMXsave(r22) ; Pop the vector stack
+ bl EXT(save_ret) ; Toss it
+ b vrenable ; Go enable and exit...
+
;
-; Note: CR6 is now free
+; This function invalidates any live vector context for the passed in facility_context.
+; This is intended to be called just before act_machine_sv_free tosses saveareas.
;
- la r21,savevr18(r14) ; Point to line 9
- bf 1,lnol8 ; No line 8 to do...
- dcbt br0,r20 ; Touch cache line 8
-
-lnol8:
- la r23,savevr14(r14) ; Point to V14/V15 pair
- bf 28,lnovr12 ; Do not restore VR12...
- lvxl v12,br0,r22 ; Restore VR12
-
-lnovr12:
- bf 29,lnovr13 ; Do not restore VR13...
- lvxl v13,r30,r22 ; Restore VR13
-
-lnovr13:
- mtcrf 0x02,r10 ; Set CRs for registers 24-27
- la r20,savevr20(r14) ; Point to line 10
- bf 3,lnol9 ; No line 9 to do...
- dcbt br0,r21 ; Touch cache line 9
-
-lnol9:
- la r22,savevr16(r14) ; Point to V16/V17 pair
- bf 30,lnovr14 ; Do not restore VR14...
- lvxl v14,br0,r23 ; Restore VR14
-
-lnovr14:
- bf 31,lnovr15 ; Do not restore VR15...
- lvxl v15,r30,r23 ; Restore VR15
-
-lnovr15:
+
+ .align 5
+ .globl EXT(toss_live_vec)
+
+LEXT(toss_live_vec)
+
+ lis r0,hi16(MASK(MSR_VEC)) ; Get VEC
+ mfmsr r9 ; Get the MSR
+ ori r0,r0,lo16(MASK(MSR_FP)) ; Add in FP
+ rlwinm. r8,r9,0,MSR_VEC_BIT,MSR_VEC_BIT ; Are vectors on right now?
+ andc r9,r9,r0 ; Force off VEC and FP
+ ori r0,r0,lo16(MASK(MSR_EE)) ; Turn off EE
+ andc r0,r9,r0 ; Turn off EE now
+ mtmsr r0 ; No interruptions
+ isync
+ beq+ tlvnotours ; Vector off, can not be live here...
+
+ mfsprg r8,0 ; Get the per proc
+
;
-; Note: CR7 is now free
+; Note that at this point, since vecs are on, we are the owner
+; of live state on this processor
;
- la r21,savevr22(r14) ; Point to line 11
- bf 5,lnol10 ; No line 10 to do...
- dcbt br0,r20 ; Touch cache line 10
-
-lnol10:
- la r23,savevr18(r14) ; Point to V18/V19 pair
- bf 16,lnovr16 ; Do not restore VR16...
- lvxl v16,br0,r22 ; Restore VR16
+
+ lwz r6,VMXowner(r8) ; Get the thread that owns the vector
+ li r0,0 ; Clear this just in case we need it
+ cmplw r6,r3 ; Are we tossing our own context?
+ bne- tlvnotours ; Nope...
-lnovr16:
- bf 17,lnovr17 ; Do not restore VR17...
- lvxl v17,r30,r22 ; Restore VR17
+ vspltish v1,1 ; Turn on the non-Java bit and saturate
+ vspltisw v0,1 ; Turn on the saturate bit
+ vxor v1,v1,v0 ; Turn off saturate
+ mtspr vrsave,r0 ; Clear VRSAVE
+ mtvscr v1 ; Set the non-java, no saturate status
+
+tlvnotours: lwz r11,VMXcpu(r3) ; Get the cpu on which we last loaded context
+ lis r12,hi16(EXT(per_proc_info)) ; Set base per_proc
+ mulli r11,r11,ppSize ; Find offset to the owner per_proc
+ ori r12,r12,lo16(EXT(per_proc_info)) ; Set base per_proc
+ li r10,VMXowner ; Displacement to vector owner
+ add r11,r12,r11 ; Point to the owner per_proc
+ li r0,0 ; Set a 0 to invalidate context
-lnovr17:
- mtcrf 0x01,r10 ; Set CRs for registers 28-31
-;
-; Note: All registers have been or are accounted for in CRs
-;
- la r20,savevr24(r14) ; Point to line 12
- bf 7,lnol11 ; No line 11 to do...
- dcbt br0,r21 ; Touch cache line 11
-
-lnol11:
- la r22,savevr20(r14) ; Point to V20/V21 pair
- bf 18,lnovr18 ; Do not restore VR18...
- lvxl v18,br0,r23 ; Restore VR18
-
-lnovr18:
- bf 19,lnovr19 ; Do not restore VR19...
- lvxl v19,r30,r23 ; Restore VR19
-
-lnovr19:
- la r21,savevr26(r14) ; Point to line 13
- bf 9,lnol12 ; No line 12 to do...
- dcbt br0,r20 ; Touch cache line 12
-
-lnol12:
- la r23,savevr22(r14) ; Point to V22/V23 pair
- bf 20,lnovr20 ; Do not restore VR20...
- lvxl v20,br0,r22 ; Restore VR20
-
-lnovr20:
- bf 21,lnovr21 ; Do not restore VR21...
- lvxl v21,r30,r22 ; Restore VR21
-
-lnovr21:
- la r20,savevr28(r14) ; Point to line 14
- bf 11,lnol13 ; No line 13 to do...
- dcbt br0,r21 ; Touch cache line 13
-
-lnol13:
- la r22,savevr24(r14) ; Point to V24/V25 pair
- bf 22,lnovr22 ; Do not restore VR22...
- lvxl v22,br0,r23 ; Restore VR22
-
-lnovr22:
- bf 23,lnovr23 ; Do not restore VR23...
- lvxl v23,r30,r23 ; Restore VR23
-
-lnovr23:
- la r21,savevr30(r14) ; Point to line 15
- bf 13,lnol14 ; No line 14 to do...
- dcbt br0,r20 ; Touch cache line 14
-
-lnol14:
- la r23,savevr26(r14) ; Point to V26/V27 pair
- bf 24,lnovr24 ; Do not restore VR24...
- lvxl v24,br0,r22 ; Restore VR24
-
-lnovr24:
- bf 25,lnovr25 ; Do not restore VR25...
- lvxl v25,r30,r22 ; Restore VR25
-
-lnovr25:
- bf 15,lnol15 ; No line 15 to do...
- dcbt br0,r21 ; Touch cache line 15
-
-lnol15:
+tlvinvothr: lwarx r12,r10,r11 ; Get the owner
+
+ sub r0,r12,r3 ; Subtract one from the other
+ sub r8,r3,r12 ; Subtract the other from the one
+ or r8,r8,r0 ; Combine them
+ srawi r8,r8,31 ; Get a 0 if equal or -1 of not
+ and r12,r12,r8 ; Make 0 if same, unchanged if not
+ stwcx. r12,r10,r11 ; Try to invalidate it
+ bne-- tlvinvothr ; Try again if there was a collision...
+
+ mtmsr r9 ; Restore interruptions
+ isync ; Could be turning off vectors here
+ blr ; Leave....
+
+#if 0
;
-; Note: All needed cache lines have been touched now
+; This function invalidates any live vector context for the passed in facility_context
+; if the level is current. It also tosses the corresponding savearea if there is one.
+; This function is primarily used whenever we detect a VRSave that is all zeros.
;
- la r22,savevr28(r14) ; Point to V28/V29 pair
- bf 26,lnovr26 ; Do not restore VR26...
- lvxl v26,br0,r23 ; Restore VR26
-
-lnovr26:
- bf 27,lnovr27 ; Do not restore VR27...
- lvxl v27,r30,r23 ; Restore VR27
-
-lnovr27:
- la r23,savevr30(r14) ; Point to V30/V31 pair
- bf 28,lnovr28 ; Do not restore VR28...
- lvxl v28,br0,r22 ; Restore VR28
-
-lnovr28:
- bf 29,lnovr29 ; Do not restore VR29...
- lvxl v29,r30,r22 ; Restore VR29
+
+ .align 5
+ .globl EXT(vec_trash)
+
+LEXT(vec_trash)
-lnovr29:
- bf 30,lnovr30 ; Do not restore VR30...
- lvxl v30,br0,r23 ; Restore VR30
+ lwz r12,facAct(r3) ; Get the activation
+ lwz r11,VMXlevel(r3) ; Get the context level
+ lwz r10,ACT_MACT_PCB(r12) ; Grab the current level for the thread
+ lwz r9,VMXsave(r3) ; Get the savearea, if any
+ cmplw r10,r11 ; Are we at the right level?
+ cmplwi cr1,r9,0 ; Remember if there is a savearea
+ bnelr+ ; No, we do nothing...
-lnovr30:
-;
-; Everything is restored now except for VR31. We need it to get
-; the QNaNBarbarian value to put into idle vector registers
-;
+ lwz r11,VMXcpu(r3) ; Get the cpu on which we last loaded context
+ lis r12,hi16(EXT(per_proc_info)) ; Set base per_proc
+ mulli r11,r11,ppSize ; Find offset to the owner per_proc
+ ori r12,r12,lo16(EXT(per_proc_info)) ; Set base per_proc
+ li r10,VMXowner ; Displacement to vector owner
+ add r11,r12,r11 ; Point to the owner per_proc
- lis r5,hi16(EXT(QNaNbarbarian)) ; Get address of empty value
- cmpwi r10,-1 ; Handle the quick case of all registers in use
- ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Get low address of empty value
- beq- mstlvr31 ; Not likely, but all are in use...
- mtcrf 255,r10 ; Get mask of valid registers
- lvxl v31,br0,r5 ; Initialize VR31 to the empty value
-
- bt 0,ni0 ; Register is ok already...
- vor v0,v31,v31 ; Copy into the next register
-ni0:
- bt 1,ni1 ; Register is ok already...
- vor v1,v31,v31 ; Copy into the next register
-ni1:
- bt 2,ni2 ; Register is ok already...
- vor v2,v31,v31 ; Copy into the next register
-ni2:
- bt 3,ni3 ; Register is ok already...
- vor v3,v31,v31 ; Copy into the next register
-ni3:
- bt 4,ni4 ; Register is ok already...
- vor v4,v31,v31 ; Copy into the next register
-ni4:
- bt 5,ni5 ; Register is ok already...
- vor v5,v31,v31 ; Copy into the next register
-ni5:
- bt 6,ni6 ; Register is ok already...
- vor v6,v31,v31 ; Copy into the next register
-ni6:
- bt 7,ni7 ; Register is ok already...
- vor v7,v31,v31 ; Copy into the next register
-ni7:
- bt 8,ni8 ; Register is ok already...
- vor v8,v31,v31 ; Copy into the next register
-ni8:
- bt 9,ni9 ; Register is ok already...
- vor v9,v31,v31 ; Copy into the next register
-ni9:
- bt 10,ni10 ; Register is ok already...
- vor v10,v31,v31 ; Copy into the next register
-ni10:
- bt 11,ni11 ; Register is ok already...
- vor v11,v31,v31 ; Copy into the next register
-ni11:
- bt 12,ni12 ; Register is ok already...
- vor v12,v31,v31 ; Copy into the next register
-ni12:
- bt 13,ni13 ; Register is ok already...
- vor v13,v31,v31 ; Copy into the next register
-ni13:
- bt 14,ni14 ; Register is ok already...
- vor v14,v31,v31 ; Copy into the next register
-ni14:
- bt 15,ni15 ; Register is ok already...
- vor v15,v31,v31 ; Copy into the next register
-ni15:
- bt 16,ni16 ; Register is ok already...
- vor v16,v31,v31 ; Copy into the next register
-ni16:
- bt 17,ni17 ; Register is ok already...
- vor v17,v31,v31 ; Copy into the next register
-ni17:
- bt 18,ni18 ; Register is ok already...
- vor v18,v31,v31 ; Copy into the next register
-ni18:
- bt 19,ni19 ; Register is ok already...
- vor v19,v31,v31 ; Copy into the next register
-ni19:
- bt 20,ni20 ; Register is ok already...
- vor v20,v31,v31 ; Copy into the next register
-ni20:
- bt 21,ni21 ; Register is ok already...
- vor v21,v31,v31 ; Copy into the next register
-ni21:
- bt 22,ni22 ; Register is ok already...
- vor v22,v31,v31 ; Copy into the next register
-ni22:
- bt 23,ni23 ; Register is ok already...
- vor v23,v31,v31 ; Copy into the next register
-ni23:
- bt 24,ni24 ; Register is ok already...
- vor v24,v31,v31 ; Copy into the next register
-ni24:
- bt 25,ni25 ; Register is ok already...
- vor v25,v31,v31 ; Copy into the next register
-ni25:
- bt 26,ni26 ; Register is ok already...
- vor v26,v31,v31 ; Copy into the next register
-ni26:
- bt 27,ni27 ; Register is ok already...
- vor v27,v31,v31 ; Copy into the next register
-ni27:
- bt 28,ni28 ; Register is ok already...
- vor v28,v31,v31 ; Copy into the next register
-ni28:
- bt 29,ni29 ; Register is ok already...
- vor v29,v31,v31 ; Copy into the next register
-ni29:
- bt 30,ni30 ; Register is ok already...
- vor v30,v31,v31 ; Copy into the next register
-ni30:
- bf 31,lnovr31 ; R31 is empty, no need to restore...
-
-mstlvr31: lvxl v31,r30,r23 ; Restore VR31
-
-lnovr31:
-
-vrenable:
- lwz r9,SAVflags(r4) /* Get the flags of the current savearea */
- lwz r8,savesrr1(r4) ; Get the msr of the interrupted guy
- rlwinm r5,r4,0,0,19 /* Get the page address of the savearea */
- oris r8,r8,hi16(MASK(MSR_VEC)) ; Enable the vector facility
- lwz r10,ACT_MACT_SPF(r17) ; Get the special flags
- lis r7,hi16(SAVattach) /* Get the attached flag */
- lwz r5,SACvrswap(r5) /* Get Virtual to Real translation */
- oris r10,r10,hi16(vectorUsed|vectorCng) ; Set that we used vectors
- mr. r15,r15 ; See if we are doing this for user state
- stw r8,savesrr1(r4) ; Set the msr of the interrupted guy
- andc r9,r9,r7 /* Clear the attached bit */
- xor r3,r4,r5 /* Get the real address of the savearea */
- stw r9,SAVflags(r4) /* Set the flags of the current savearea */
- bne- vrnuser ; We are not user state...
- stw r10,ACT_MACT_SPF(r17) ; Set the activation copy
- stw r10,spcFlags(r6) ; Set per_proc copy
+vtinvothr: lwarx r12,r10,r11 ; Get the owner
-vrnuser:
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F0A ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- mr r8,r3 ; Save this
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r3,r8 ; Restore it
-#endif
-#endif
- b EXT(exception_exit) /* Exit from the fray... */
+ sub r0,r12,r3 ; Subtract one from the other
+ sub r8,r3,r12 ; Subtract the other from the one
+ or r8,r8,r0 ; Combine them
+ srawi r8,r8,31 ; Get a 0 if equal or -1 of not
+ and r12,r12,r8 ; Make 0 if same, unchanged if not
+ stwcx. r12,r10,r11 ; Try to invalidate it
+ bne-- vtinvothr ; Try again if there was a collision...
-/*
- * Initialize the registers to some bogus value
- * We make sure that non-Java mode is the default here
- */
-ProtectTheAmericanWay:
+ beqlr++ cr1 ; Leave if there is no savearea
+ lwz r8,SAVlevel(r9) ; Get the level of the savearea
+ cmplw r8,r11 ; Savearea for the current level?
+ bnelr++ ; No, nothing to release...
-#if FPVECDBG
- lis r0,HIGH_ADDR(CutTrace) ; (TEST/DEBUG)
- li r2,0x5F09 ; (TEST/DEBUG)
- oris r0,r0,LOW_ADDR(CutTrace) ; (TEST/DEBUG)
- sc ; (TEST/DEBUG)
-#if GDDBG
- lis r3,hi16(EXT(GratefulDeb)) ; Point to top of display
- mr r8,r4 ; Save this
- ori r3,r3,lo16(EXT(GratefulDeb)) ; Put in bottom part
- mr r4,r2 ; Set value
- mtlr r3 ; Set link register
- li r3,1 ; Display address
- blrl ; Display it
- mr r4,r8 ; Restore it
-#endif
-#endif
- lis r5,hi16(EXT(QNaNbarbarian)) ; Get address of empty value
- vspltish v1,1 ; Turn on the non-Java bit and saturate
- ori r5,r5,lo16(EXT(QNaNbarbarian)) ; Get low address of empty value
- vspltisw v2,1 ; Turn on the saturate bit
- lvxl v0,br0,r5 ; Initialize VR0
- vxor v1,v1,v2 ; Turn off saturate
-
- vor v2,v0,v0 ; Copy into the next register
- mtvscr v1 ; Clear the vector status register
- vor v3,v0,v0 ; Copy into the next register
- vor v1,v0,v0 ; Copy into the next register
- vor v4,v0,v0 ; Copy into the next register
- vor v5,v0,v0 ; Copy into the next register
- vor v6,v0,v0 ; Copy into the next register
- vor v7,v0,v0 ; Copy into the next register
- vor v8,v0,v0 ; Copy into the next register
- vor v9,v0,v0 ; Copy into the next register
- vor v10,v0,v0 ; Copy into the next register
- vor v11,v0,v0 ; Copy into the next register
- vor v12,v0,v0 ; Copy into the next register
- vor v13,v0,v0 ; Copy into the next register
- vor v14,v0,v0 ; Copy into the next register
- vor v15,v0,v0 ; Copy into the next register
- vor v16,v0,v0 ; Copy into the next register
- vor v17,v0,v0 ; Copy into the next register
- vor v18,v0,v0 ; Copy into the next register
- vor v19,v0,v0 ; Copy into the next register
- vor v20,v0,v0 ; Copy into the next register
- vor v21,v0,v0 ; Copy into the next register
- vor v22,v0,v0 ; Copy into the next register
- vor v23,v0,v0 ; Copy into the next register
- vor v24,v0,v0 ; Copy into the next register
- vor v25,v0,v0 ; Copy into the next register
- vor v26,v0,v0 ; Copy into the next register
- vor v27,v0,v0 ; Copy into the next register
- vor v28,v0,v0 ; Copy into the next register
- vor v29,v0,v0 ; Copy into the next register
- vor v30,v0,v0 ; Copy into the next register
- vor v31,v0,v0 ; Copy into the next register
- b vrenable ; Finish setting it all up...
+ lwz r8,SAVprev+4(r9) ; Pick up the previous area
+ mr. r8,r8 ; Is there a previous?
+ beq-- vtnoprev ; Nope...
+ lwz r7,SAVlevel(r8) ; Get the level associated with save
+vtnoprev: stw r8,VMXsave(r3) ; Dequeue this savearea
+ stw r7,VMXlevel(r3) ; Pop the level
+
+ mr r3,r9 ; Get the savearea to release
+ b EXT(save_ret) ; Go and toss the save area (note, we will return from there)...
+#endif
+
;
-; Finds a unused vector area in the activation pointed
-; to by R12s saved contexts. If none are found (unlikely but possible)
-; and R3 is 0, a new area is allocated. If R3 is non-zero, it contains
-; a pointer to a vector savearea that is free.
-;
+; Just some test code to force vector and/or floating point in the kernel
+;
-vsrchsave: lwz r6,ACT_MACT_PCB(r12) ; Get the first "normal" savearea
-
-vsrnorm: mr. r5,r6 ; Is there another?
- beq- vsrvect ; No, search the floating point saveareas...
- lwz r7,SAVflags(r5) ; Get the flags for this guy
- lwz r6,SAVprev(r5) ; Get the previous savearea, just in case
- andis. r8,r7,hi16(SAVvmxvalid) ; Have we found an empty vector save in normal?
- beq+ vsrgot ; We found one...
- b vsrnorm ; Search again...
+ .align 5
+ .globl EXT(fctx_test)
-vsrvect: lwz r6,ACT_MACT_FPU(r12) ; Get the first "floating point" savearea
+LEXT(fctx_test)
-vsrvectx: mr. r5,r6 ; Is there another?
- beq- vsrget ; No, try to allocate one...
- lwz r7,SAVflags(r5) ; Get the flags for this guy
- lwz r6,SAVprefp(r5) ; Get the previous savearea, just in case
- andis. r8,r7,hi16(SAVvmxvalid) ; Have we found an empty vector save in float?
- bne- vsrvectx ; Search again...
+ mfsprg r3,1 ; Get the current thread
+ mr. r3,r3 ; Are we actually up and running?
+ beqlr- ; No...
-vsrgot: mr r3,r5 ; Get the savearea into the right register
- blr ; Return...
+ fmr f0,f0 ; Use floating point
+ mftb r4 ; Get time base for a random number
+ li r5,1 ; Get a potential vrsave to use
+ andi. r4,r4,0x3F ; Get a number from 0 - 63
+ slw r5,r5,r4 ; Choose a register to save (should be 0 half the time)
+ mtspr vrsave,r5 ; Set VRSave
+ vor v0,v0,v0 ; Use vectors
+ blr
-vsrget: mr. r5,r3 ; Do we allocate or use existing?
- beq+ vsrallo ; Allocate one...
-
- lwz r7,SAVflags(r3) ; Get the passed in area flags
- blr ; Return...
-;
-; NOTE: save_get will return directly and set R7 to 0...
-;
-vsrallo: b EXT(save_get) ; Get a fresh savearea
+// *******************
+// * f p _ s t o r e *
+// *******************
+//
+// Store FPRs into a save area. Called by fpu_save and fpu_switch.
+//
+// When called:
+// floating pt is enabled
+// r3 = ptr to save area
+//
+// We destroy:
+// r11.
+
+fp_store:
+ mfsprg r11,2 ; get feature flags
+ mtcrf 0x02,r11 ; put cache line size bits in cr6
+ la r11,savefp0(r3) ; point to 1st line
+ dcbz128 0,r11 ; establish 1st line no matter what linesize is
+ bt-- pf32Byteb,fp_st32 ; skip if a 32-byte machine
+
+// Store the FPRs on a 128-byte machine.
+
+ stfd f0,savefp0(r3)
+ stfd f1,savefp1(r3)
+ la r11,savefp16(r3) ; Point to the 2nd cache line
+ stfd f2,savefp2(r3)
+ stfd f3,savefp3(r3)
+ dcbz128 0,r11 ; establish 2nd line
+ stfd f4,savefp4(r3)
+ stfd f5,savefp5(r3)
+ stfd f6,savefp6(r3)
+ stfd f7,savefp7(r3)
+ stfd f8,savefp8(r3)
+ stfd f9,savefp9(r3)
+ stfd f10,savefp10(r3)
+ stfd f11,savefp11(r3)
+ stfd f12,savefp12(r3)
+ stfd f13,savefp13(r3)
+ stfd f14,savefp14(r3)
+ stfd f15,savefp15(r3)
+ stfd f16,savefp16(r3)
+ stfd f17,savefp17(r3)
+ stfd f18,savefp18(r3)
+ stfd f19,savefp19(r3)
+ stfd f20,savefp20(r3)
+ stfd f21,savefp21(r3)
+ stfd f22,savefp22(r3)
+ stfd f23,savefp23(r3)
+ stfd f24,savefp24(r3)
+ stfd f25,savefp25(r3)
+ stfd f26,savefp26(r3)
+ stfd f27,savefp27(r3)
+ stfd f28,savefp28(r3)
+ stfd f29,savefp29(r3)
+ stfd f30,savefp30(r3)
+ stfd f31,savefp31(r3)
+ blr
+
+// Store FPRs on a 32-byte machine.
-/*
- * void lfs(fpsp,fpdp)
- *
- * load the single precision float to the double
- *
- * This routine is used by the alignment handler.
- *
- */
-ENTRY(lfs, TAG_NO_FRAME_USED)
- lfs f1, 0(r3)
- stfd f1, 0(r4)
- blr
+fp_st32:
+ la r11,savefp4(r3) ; Point to the 2nd line
+ stfd f0,savefp0(r3)
+ dcbz 0,r11 ; Allocate cache
+ stfd f1,savefp1(r3)
+ stfd f2,savefp2(r3)
+ la r11,savefp8(r3) ; Point to the 3rd line
+ stfd f3,savefp3(r3)
+ dcbz 0,r11 ; Allocate cache
+ stfd f4,savefp4(r3)
+ stfd f5,savefp5(r3)
+ stfd f6,savefp6(r3)
+ la r11,savefp12(r3) ; Point to the 4th line
+ stfd f7,savefp7(r3)
+ dcbz 0,r11 ; Allocate cache
+ stfd f8,savefp8(r3)
+ stfd f9,savefp9(r3)
+ stfd f10,savefp10(r3)
+ la r11,savefp16(r3) ; Point to the 5th line
+ stfd f11,savefp11(r3)
+ dcbz 0,r11 ; Allocate cache
+ stfd f12,savefp12(r3)
+ stfd f13,savefp13(r3)
+ stfd f14,savefp14(r3)
+ la r11,savefp20(r3) ; Point to the 6th line
+ stfd f15,savefp15(r3)
+ dcbz 0,r11 ; Allocate cache
+ stfd f16,savefp16(r3)
+ stfd f17,savefp17(r3)
+ stfd f18,savefp18(r3)
+ la r11,savefp24(r3) ; Point to the 7th line
+ stfd f19,savefp19(r3)
+ dcbz 0,r11 ; Allocate cache
+ stfd f20,savefp20(r3)
-/*
- * fpsp stfs(fpdp,fpsp)
- *
- * store the double precision float to the single
- *
- * This routine is used by the alignment handler.
- *
- */
-ENTRY(stfs, TAG_NO_FRAME_USED)
- lfd f1, 0(r3)
- stfs f1, 0(r4)
- blr
+ stfd f21,savefp21(r3)
+ stfd f22,savefp22(r3)
+ la r11,savefp28(r3) ; Point to the 8th line
+ stfd f23,savefp23(r3)
+ dcbz 0,r11 ; allocate it
+ stfd f24,savefp24(r3)
+ stfd f25,savefp25(r3)
+ stfd f26,savefp26(r3)
+ stfd f27,savefp27(r3)
+ stfd f28,savefp28(r3)
+ stfd f29,savefp29(r3)
+ stfd f30,savefp30(r3)
+ stfd f31,savefp31(r3)
+ blr
+
+
+// *******************
+// * v r _ s t o r e *
+// *******************
+//
+// Store VRs into savearea, according to bits set in passed vrsave bitfield. This routine is used
+// both by vec_save and vec_switch. In order to minimize conditional branches and touching in
+// unnecessary cache blocks, we either save all or none of the VRs in a block. We have separate paths
+// for each cache block size.
+//
+// When called:
+// interrupts are off, vectors are enabled
+// r3 = ptr to save area
+// r10 = vrsave (not 0)
+//
+// We destroy:
+// r4 - r11, all CRs.
+
+vr_store:
+ mfsprg r9,2 ; get feature flags
+ stw r10,savevrvalid(r3) ; Save the validity information in savearea
+ slwi r8,r10,1 ; Shift over 1
+ mtcrf 0x02,r9 ; put cache line size bits in cr6 where we can test
+ or r8,r10,r8 ; r8 <- even bits show which pairs are in use
+ bt-- pf32Byteb,vr_st32 ; skip if 32-byte cacheline processor
+
+
+; Save vectors on a 128-byte linesize processor. We save all or none of the 8 registers in each of
+; the four cache lines. This minimizes mispredicted branches yet handles cache lines optimally.
+
+ slwi r7,r8,2 ; shift groups-of-2 over by 2
+ li r4,16 ; load offsets for X-form stores
+ or r8,r7,r8 ; show if any in group of 4 are in use
+ li r5,32
+ slwi r7,r8,4 ; shift groups-of-4 over by 4
+ li r6,48
+ or r11,r7,r8 ; show if any in group of 8 are in use
+ li r7,64
+ mtcrf 0x80,r11 ; set CRs one at a time (faster)
+ li r8,80
+ mtcrf 0x20,r11
+ li r9,96
+ mtcrf 0x08,r11
+ li r10,112
+ mtcrf 0x02,r11
+
+ bf 0,vr_st64b ; skip if none of vr0-vr7 are in use
+ la r11,savevr0(r3) ; get address of this group of registers in save area
+ dcbz128 0,r11 ; zero the line
+ stvxl v0,0,r11 ; save 8 VRs in the line
+ stvxl v1,r4,r11
+ stvxl v2,r5,r11
+ stvxl v3,r6,r11
+ stvxl v4,r7,r11
+ stvxl v5,r8,r11
+ stvxl v6,r9,r11
+ stvxl v7,r10,r11
+
+vr_st64b:
+ bf 8,vr_st64c ; skip if none of vr8-vr15 are in use
+ la r11,savevr8(r3) ; get address of this group of registers in save area
+ dcbz128 0,r11 ; zero the line
+ stvxl v8,0,r11 ; save 8 VRs in the line
+ stvxl v9,r4,r11
+ stvxl v10,r5,r11
+ stvxl v11,r6,r11
+ stvxl v12,r7,r11
+ stvxl v13,r8,r11
+ stvxl v14,r9,r11
+ stvxl v15,r10,r11
+
+vr_st64c:
+ bf 16,vr_st64d ; skip if none of vr16-vr23 are in use
+ la r11,savevr16(r3) ; get address of this group of registers in save area
+ dcbz128 0,r11 ; zero the line
+ stvxl v16,0,r11 ; save 8 VRs in the line
+ stvxl v17,r4,r11
+ stvxl v18,r5,r11
+ stvxl v19,r6,r11
+ stvxl v20,r7,r11
+ stvxl v21,r8,r11
+ stvxl v22,r9,r11
+ stvxl v23,r10,r11
+
+vr_st64d:
+ bflr 24 ; done if none of vr24-vr31 are in use
+ la r11,savevr24(r3) ; get address of this group of registers in save area
+ dcbz128 0,r11 ; zero the line
+ stvxl v24,0,r11 ; save 8 VRs in the line
+ stvxl v25,r4,r11
+ stvxl v26,r5,r11
+ stvxl v27,r6,r11
+ stvxl v28,r7,r11
+ stvxl v29,r8,r11
+ stvxl v30,r9,r11
+ stvxl v31,r10,r11
+ blr
+
+; Save vectors on a 32-byte linesize processor. We save in 16 groups of 2: we either save both
+; or neither in each group. This cuts down on conditional branches.
+; r8 = bitmask with bit n set (for even n) if either of that pair of VRs is in use
+; r3 = savearea
+
+vr_st32:
+ mtcrf 0xFF,r8 ; set CR bits so we can branch on them
+ li r4,16 ; load offset for X-form stores
+
+ bf 0,vr_st32b ; skip if neither VR in this pair is in use
+ la r11,savevr0(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v0,0,r11 ; save the two VRs in the line
+ stvxl v1,r4,r11
+
+vr_st32b:
+ bf 2,vr_st32c ; skip if neither VR in this pair is in use
+ la r11,savevr2(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v2,0,r11 ; save the two VRs in the line
+ stvxl v3,r4,r11
+
+vr_st32c:
+ bf 4,vr_st32d ; skip if neither VR in this pair is in use
+ la r11,savevr4(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v4,0,r11 ; save the two VRs in the line
+ stvxl v5,r4,r11
+
+vr_st32d:
+ bf 6,vr_st32e ; skip if neither VR in this pair is in use
+ la r11,savevr6(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v6,0,r11 ; save the two VRs in the line
+ stvxl v7,r4,r11
+
+vr_st32e:
+ bf 8,vr_st32f ; skip if neither VR in this pair is in use
+ la r11,savevr8(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v8,0,r11 ; save the two VRs in the line
+ stvxl v9,r4,r11
+
+vr_st32f:
+ bf 10,vr_st32g ; skip if neither VR in this pair is in use
+ la r11,savevr10(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v10,0,r11 ; save the two VRs in the line
+ stvxl v11,r4,r11
+
+vr_st32g:
+ bf 12,vr_st32h ; skip if neither VR in this pair is in use
+ la r11,savevr12(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v12,0,r11 ; save the two VRs in the line
+ stvxl v13,r4,r11
+
+vr_st32h:
+ bf 14,vr_st32i ; skip if neither VR in this pair is in use
+ la r11,savevr14(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v14,0,r11 ; save the two VRs in the line
+ stvxl v15,r4,r11
+
+vr_st32i:
+ bf 16,vr_st32j ; skip if neither VR in this pair is in use
+ la r11,savevr16(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v16,0,r11 ; save the two VRs in the line
+ stvxl v17,r4,r11
+
+vr_st32j:
+ bf 18,vr_st32k ; skip if neither VR in this pair is in use
+ la r11,savevr18(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v18,0,r11 ; save the two VRs in the line
+ stvxl v19,r4,r11
+
+vr_st32k:
+ bf 20,vr_st32l ; skip if neither VR in this pair is in use
+ la r11,savevr20(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v20,0,r11 ; save the two VRs in the line
+ stvxl v21,r4,r11
+
+vr_st32l:
+ bf 22,vr_st32m ; skip if neither VR in this pair is in use
+ la r11,savevr22(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v22,0,r11 ; save the two VRs in the line
+ stvxl v23,r4,r11
+
+vr_st32m:
+ bf 24,vr_st32n ; skip if neither VR in this pair is in use
+ la r11,savevr24(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v24,0,r11 ; save the two VRs in the line
+ stvxl v25,r4,r11
+
+vr_st32n:
+ bf 26,vr_st32o ; skip if neither VR in this pair is in use
+ la r11,savevr26(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v26,0,r11 ; save the two VRs in the line
+ stvxl v27,r4,r11
+
+vr_st32o:
+ bf 28,vr_st32p ; skip if neither VR in this pair is in use
+ la r11,savevr28(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v28,0,r11 ; save the two VRs in the line
+ stvxl v29,r4,r11
+
+vr_st32p:
+ bflr 30 ; done if neither VR in this pair is in use
+ la r11,savevr30(r3) ; get address of this group of registers in save area
+ dcba 0,r11 ; establish the line wo reading it
+ stvxl v30,0,r11 ; save the two VRs in the line
+ stvxl v31,r4,r11
+ blr
+
+
+// *****************
+// * v r _ l o a d *
+// *****************
+//
+// Load live VRs from a savearea, according to bits set in a passed vector. This is the reverse
+// of "vr_store". Like it, we avoid touching unnecessary cache blocks and minimize conditional
+// branches by loading all VRs from a cache line, if we have to load any. If we don't load the VRs
+// in a cache line, we bug them. Note that this behavior is slightly different from earlier kernels,
+// which would bug all VRs that aren't live.
+//
+// When called:
+// interrupts are off, vectors are enabled
+// r3 = ptr to save area
+// r10 = vector of live regs to load (ie, savevrsave & savevrvalid, may be 0)
+// v31 = bugbug constant (0x7FFFDEAD7FFFDEAD7FFFDEAD7FFFDEAD)
+//
+// We destroy:
+// r4 - r11, all CRs.
+
+vr_load:
+ mfsprg r9,2 ; get feature flags
+ li r6,1 ; assuming 32-byte, get (#VRs)-1 in a cacheline
+ mtcrf 0x02,r9 ; set cache line size bits in cr6
+ lis r7,0xC000 ; assuming 32-byte, set bits 0-1
+ bt-- pf32Byteb,vr_ld0 ; skip if 32-bit processor
+ li r6,7 ; 128-byte machines have 8 VRs in a cacheline
+ lis r7,0xFF00 ; so set bits 0-7
+
+// Loop touching in cache blocks we will load from.
+// r3 = savearea ptr
+// r5 = we light bits for the VRs we will be loading
+// r6 = 1 if 32-byte, 7 if 128-byte
+// r7 = 0xC0000000 if 32-byte, 0xFF000000 if 128-byte
+// r10 = live VR bits
+// v31 = bugbug constant
+
+vr_ld0:
+ li r5,0 ; initialize set of VRs to load
+ la r11,savevr0(r3) ; get address of register file
+ b vr_ld2 ; enter loop in middle
+
+ .align 5
+vr_ld1: ; loop over each cache line we will load
+ dcbt r4,r11 ; start prefetch of the line
+ andc r10,r10,r9 ; turn off the bits in this line
+ or r5,r5,r9 ; we will load all these
+vr_ld2: ; initial entry pt
+ cntlzw r4,r10 ; get offset to next live VR
+ andc r4,r4,r6 ; cacheline align it
+ srw. r9,r7,r4 ; position bits for VRs in that cache line
+ slwi r4,r4,4 ; get byte offset within register file to that line
+ bne vr_ld1 ; loop if more bits in r10
+
+ bf-- pf128Byteb,vr_ld32 ; skip if not 128-byte lines
+
+// Handle a processor with 128-byte cache lines. Four groups of 8 VRs.
+// r3 = savearea ptr
+// r5 = 1st bit in each cacheline is 1 iff any reg in that line must be loaded
+// r11 = addr(savevr0)
+// v31 = bugbug constant
+
+ mtcrf 0x80,r5 ; set up bits for conditional branches
+ li r4,16 ; load offsets for X-form stores
+ li r6,48
+ mtcrf 0x20,r5 ; load CRs ona at a time, which is faster
+ li r7,64
+ li r8,80
+ mtcrf 0x08,r5
+ li r9,96
+ li r10,112
+ mtcrf 0x02,r5
+ li r5,32
+
+ bt 0,vr_ld128a ; skip if this line must be loaded
+ vor v0,v31,v31 ; no VR must be loaded, so bug them all
+ vor v1,v31,v31
+ vor v2,v31,v31
+ vor v3,v31,v31
+ vor v4,v31,v31
+ vor v5,v31,v31
+ vor v6,v31,v31
+ vor v7,v31,v31
+ b vr_ld128b
+vr_ld128a: ; must load from this line
+ lvxl v0,0,r11
+ lvxl v1,r4,r11
+ lvxl v2,r5,r11
+ lvxl v3,r6,r11
+ lvxl v4,r7,r11
+ lvxl v5,r8,r11
+ lvxl v6,r9,r11
+ lvxl v7,r10,r11
+
+vr_ld128b: ; here to handle next cache line
+ la r11,savevr8(r3) ; load offset to it
+ bt 8,vr_ld128c ; skip if this line must be loaded
+ vor v8,v31,v31 ; no VR must be loaded, so bug them all
+ vor v9,v31,v31
+ vor v10,v31,v31
+ vor v11,v31,v31
+ vor v12,v31,v31
+ vor v13,v31,v31
+ vor v14,v31,v31
+ vor v15,v31,v31
+ b vr_ld128d
+vr_ld128c: ; must load from this line
+ lvxl v8,0,r11
+ lvxl v9,r4,r11
+ lvxl v10,r5,r11
+ lvxl v11,r6,r11
+ lvxl v12,r7,r11
+ lvxl v13,r8,r11
+ lvxl v14,r9,r11
+ lvxl v15,r10,r11
+
+vr_ld128d: ; here to handle next cache line
+ la r11,savevr16(r3) ; load offset to it
+ bt 16,vr_ld128e ; skip if this line must be loaded
+ vor v16,v31,v31 ; no VR must be loaded, so bug them all
+ vor v17,v31,v31
+ vor v18,v31,v31
+ vor v19,v31,v31
+ vor v20,v31,v31
+ vor v21,v31,v31
+ vor v22,v31,v31
+ vor v23,v31,v31
+ b vr_ld128f
+vr_ld128e: ; must load from this line
+ lvxl v16,0,r11
+ lvxl v17,r4,r11
+ lvxl v18,r5,r11
+ lvxl v19,r6,r11
+ lvxl v20,r7,r11
+ lvxl v21,r8,r11
+ lvxl v22,r9,r11
+ lvxl v23,r10,r11
+
+vr_ld128f: ; here to handle next cache line
+ la r11,savevr24(r3) ; load offset to it
+ bt 24,vr_ld128g ; skip if this line must be loaded
+ vor v24,v31,v31 ; no VR must be loaded, so bug them all
+ vor v25,v31,v31
+ vor v26,v31,v31
+ vor v27,v31,v31
+ vor v28,v31,v31
+ vor v29,v31,v31
+ vor v30,v31,v31
+ blr
+vr_ld128g: ; must load from this line
+ lvxl v24,0,r11
+ lvxl v25,r4,r11
+ lvxl v26,r5,r11
+ lvxl v27,r6,r11
+ lvxl v28,r7,r11
+ lvxl v29,r8,r11
+ lvxl v30,r9,r11
+ lvxl v31,r10,r11
+ blr
+
+// Handle a processor with 32-byte cache lines. Sixteen groups of two VRs.
+// r5 = 1st bit in each cacheline is 1 iff any reg in that line must be loaded
+// r11 = addr(savevr0)
+
+vr_ld32:
+ mtcrf 0xFF,r5 ; set up bits for conditional branches
+ li r4,16 ; load offset for X-form stores
+
+ bt 0,vr_ld32load0 ; skip if we must load this line
+ vor v0,v31,v31 ; neither VR is live, so bug them both
+ vor v1,v31,v31
+ b vr_ld32test2
+vr_ld32load0: ; must load VRs in this line
+ lvxl v0,0,r11
+ lvxl v1,r4,r11
+
+vr_ld32test2: ; here to handle next cache line
+ la r11,savevr2(r3) ; get offset to next cache line
+ bt 2,vr_ld32load2 ; skip if we must load this line
+ vor v2,v31,v31 ; neither VR is live, so bug them both
+ vor v3,v31,v31
+ b vr_ld32test4
+vr_ld32load2: ; must load VRs in this line
+ lvxl v2,0,r11
+ lvxl v3,r4,r11
+
+vr_ld32test4: ; here to handle next cache line
+ la r11,savevr4(r3) ; get offset to next cache line
+ bt 4,vr_ld32load4 ; skip if we must load this line
+ vor v4,v31,v31 ; neither VR is live, so bug them both
+ vor v5,v31,v31
+ b vr_ld32test6
+vr_ld32load4: ; must load VRs in this line
+ lvxl v4,0,r11
+ lvxl v5,r4,r11
+
+vr_ld32test6: ; here to handle next cache line
+ la r11,savevr6(r3) ; get offset to next cache line
+ bt 6,vr_ld32load6 ; skip if we must load this line
+ vor v6,v31,v31 ; neither VR is live, so bug them both
+ vor v7,v31,v31
+ b vr_ld32test8
+vr_ld32load6: ; must load VRs in this line
+ lvxl v6,0,r11
+ lvxl v7,r4,r11
+
+vr_ld32test8: ; here to handle next cache line
+ la r11,savevr8(r3) ; get offset to next cache line
+ bt 8,vr_ld32load8 ; skip if we must load this line
+ vor v8,v31,v31 ; neither VR is live, so bug them both
+ vor v9,v31,v31
+ b vr_ld32test10
+vr_ld32load8: ; must load VRs in this line
+ lvxl v8,0,r11
+ lvxl v9,r4,r11
+
+vr_ld32test10: ; here to handle next cache line
+ la r11,savevr10(r3) ; get offset to next cache line
+ bt 10,vr_ld32load10 ; skip if we must load this line
+ vor v10,v31,v31 ; neither VR is live, so bug them both
+ vor v11,v31,v31
+ b vr_ld32test12
+vr_ld32load10: ; must load VRs in this line
+ lvxl v10,0,r11
+ lvxl v11,r4,r11
+
+vr_ld32test12: ; here to handle next cache line
+ la r11,savevr12(r3) ; get offset to next cache line
+ bt 12,vr_ld32load12 ; skip if we must load this line
+ vor v12,v31,v31 ; neither VR is live, so bug them both
+ vor v13,v31,v31
+ b vr_ld32test14
+vr_ld32load12: ; must load VRs in this line
+ lvxl v12,0,r11
+ lvxl v13,r4,r11
+
+vr_ld32test14: ; here to handle next cache line
+ la r11,savevr14(r3) ; get offset to next cache line
+ bt 14,vr_ld32load14 ; skip if we must load this line
+ vor v14,v31,v31 ; neither VR is live, so bug them both
+ vor v15,v31,v31
+ b vr_ld32test16
+vr_ld32load14: ; must load VRs in this line
+ lvxl v14,0,r11
+ lvxl v15,r4,r11
+
+vr_ld32test16: ; here to handle next cache line
+ la r11,savevr16(r3) ; get offset to next cache line
+ bt 16,vr_ld32load16 ; skip if we must load this line
+ vor v16,v31,v31 ; neither VR is live, so bug them both
+ vor v17,v31,v31
+ b vr_ld32test18
+vr_ld32load16: ; must load VRs in this line
+ lvxl v16,0,r11
+ lvxl v17,r4,r11
+
+vr_ld32test18: ; here to handle next cache line
+ la r11,savevr18(r3) ; get offset to next cache line
+ bt 18,vr_ld32load18 ; skip if we must load this line
+ vor v18,v31,v31 ; neither VR is live, so bug them both
+ vor v19,v31,v31
+ b vr_ld32test20
+vr_ld32load18: ; must load VRs in this line
+ lvxl v18,0,r11
+ lvxl v19,r4,r11
+
+vr_ld32test20: ; here to handle next cache line
+ la r11,savevr20(r3) ; get offset to next cache line
+ bt 20,vr_ld32load20 ; skip if we must load this line
+ vor v20,v31,v31 ; neither VR is live, so bug them both
+ vor v21,v31,v31
+ b vr_ld32test22
+vr_ld32load20: ; must load VRs in this line
+ lvxl v20,0,r11
+ lvxl v21,r4,r11
+
+vr_ld32test22: ; here to handle next cache line
+ la r11,savevr22(r3) ; get offset to next cache line
+ bt 22,vr_ld32load22 ; skip if we must load this line
+ vor v22,v31,v31 ; neither VR is live, so bug them both
+ vor v23,v31,v31
+ b vr_ld32test24
+vr_ld32load22: ; must load VRs in this line
+ lvxl v22,0,r11
+ lvxl v23,r4,r11
+
+vr_ld32test24: ; here to handle next cache line
+ la r11,savevr24(r3) ; get offset to next cache line
+ bt 24,vr_ld32load24 ; skip if we must load this line
+ vor v24,v31,v31 ; neither VR is live, so bug them both
+ vor v25,v31,v31
+ b vr_ld32test26
+vr_ld32load24: ; must load VRs in this line
+ lvxl v24,0,r11
+ lvxl v25,r4,r11
+
+vr_ld32test26: ; here to handle next cache line
+ la r11,savevr26(r3) ; get offset to next cache line
+ bt 26,vr_ld32load26 ; skip if we must load this line
+ vor v26,v31,v31 ; neither VR is live, so bug them both
+ vor v27,v31,v31
+ b vr_ld32test28
+vr_ld32load26: ; must load VRs in this line
+ lvxl v26,0,r11
+ lvxl v27,r4,r11
+
+vr_ld32test28: ; here to handle next cache line
+ la r11,savevr28(r3) ; get offset to next cache line
+ bt 28,vr_ld32load28 ; skip if we must load this line
+ vor v28,v31,v31 ; neither VR is live, so bug them both
+ vor v29,v31,v31
+ b vr_ld32test30
+vr_ld32load28: ; must load VRs in this line
+ lvxl v28,0,r11
+ lvxl v29,r4,r11
+
+vr_ld32test30: ; here to handle next cache line
+ la r11,savevr30(r3) ; get offset to next cache line
+ bt 30,vr_ld32load30 ; skip if we must load this line
+ vor v30,v31,v31 ; neither VR is live, so bug them both
+ blr
+vr_ld32load30: ; must load VRs in this line
+ lvxl v30,0,r11
+ lvxl v31,r4,r11
+ blr
projects / apple / xnu.git / blobdiff