eieio /* Make sure that the tlbie happens first */
tlbsync /* wait for everyone to catch up */
+ isync
its603a: sync /* Make sure of it all */
stw r11,0(r12) /* Clear the tlbie lock */
eieio /* Make sure that the tlbie happens first */
tlbsync /* wait for everyone to catch up */
+ isync
its603p: stw r11,0(r12) /* Clear the lock */
srw r5,r5,r8 /* Make a "free slot" mask */
eieio /* Make sure that the tlbie happens first */
tlbsync /* wait for everyone to catch up */
+ isync
its603pv: stw r11,0(r12) /* Clear the lock */
srw r5,r5,r8 /* Make a "free slot" mask */
eieio /* Make sure that the tlbie happens first */
tlbsync /* wait for everyone to catch up */
+ isync
its603av: stw r11,0(r12) /* Clear the lock */
srw r5,r5,r8 /* Make a "free slot" mask */
eieio /* Make sure that the tlbie happens first */
tlbsync /* wait for everyone to catch up */
+ isync
its603co: stw r11,0(r12) /* Clear the lock */
srw r5,r5,r8 /* Make a "free slot" mask */
eieio ; Make sure that the tlbie happens first
tlbsync ; wait for everyone to catch up
+ isync
htr603: stw r11,0(r12) ; Clear the lock
srw r5,r5,r8 ; Make a "free slot" mask
eieio /* Make sure that the tlbie happens first */
tlbsync /* wait for everyone to catch up */
+ isync
its603: rlwinm. r21,r21,0,0,0 ; See if we just stole an autogenned entry
sync /* Make sure of it all */
blt rbHash ; Nope, length is right
subi r6,r4,32+31 ; Back down to correct length
-rbHash: xor r2,r8,r5 ; Hash into table
+rbHash: rlwinm r5,r5,0,10,25 ; Keep only the page index
+ xor r2,r8,r5 ; Hash into table
and r2,r2,r4 ; Wrap into the table
add r2,r2,r12 ; Point right at the PCA
eieio ; Make sure that the tlbie happens first
tlbsync ; wait for everyone to catch up
+ isync
rbits603a: sync ; Wait for quiet again
stw r2,0(r12) ; Unlock invalidates