xnu-3247.1.106.tar.gz

[apple/xnu.git] / osfmk / i386 / cpuid.h

diff --git a/osfmk/i386/cpuid.h b/osfmk/i386/cpuid.h
index acaa81cd175c5a4a3e520f5044c677c7c65cea7c..adb8c4a62742a6af30affcc54d3a4d06a8de70d3 100644 (file)
--- a/osfmk/i386/cpuid.h
+++ b/osfmk/i386/cpuid.h
@@ -1,23 +1,29 @@
 /*
 /*

- * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
+ * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.

  *
  *

- * @APPLE_LICENSE_HEADER_START@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_START@

  * 
  * 

- * The contents of this file constitute Original Code as defined in and
- * are subject to the Apple Public Source License Version 1.1 (the
- * "License").  You may not use this file except in compliance with the
- * License.  Please obtain a copy of the License at
- * http://www.apple.com/publicsource and read it before using this file.
+ * This file contains Original Code and/or Modifications of Original Code
+ * as defined in and that are subject to the Apple Public Source License
+ * Version 2.0 (the 'License'). You may not use this file except in
+ * compliance with the License. The rights granted to you under the License
+ * may not be used to create, or enable the creation or redistribution of,
+ * unlawful or unlicensed copies of an Apple operating system, or to
+ * circumvent, violate, or enable the circumvention or violation of, any
+ * terms of an Apple operating system software license agreement.

  * 
  * 

- * This Original Code and all software distributed under the License are
- * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
+ * Please obtain a copy of the License at
+ * http://www.opensource.apple.com/apsl/ and read it before using this file.
+ * 
+ * The Original Code and all software distributed under the License are
+ * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER

  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,

- * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
- * License for the specific language governing rights and limitations
- * under the License.
+ * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
+ * Please see the License for the specific language governing rights and
+ * limitations under the License.

  * 
  * 

- * @APPLE_LICENSE_HEADER_END@
+ * @APPLE_OSREFERENCE_LICENSE_HEADER_END@

  */
 /*
  * @OSF_COPYRIGHT@
  */
 /*
  * @OSF_COPYRIGHT@


@@ -35,17 +41,11 @@
 
 #ifdef __APPLE_API_PRIVATE
 
 
 #ifdef __APPLE_API_PRIVATE
 

-#define        CPUID_VID_SIZE          12

 #define        CPUID_VID_INTEL         "GenuineIntel"
 #define        CPUID_VID_INTEL         "GenuineIntel"

-#define        CPUID_VID_UMC           "UMC UMC UMC "

 #define        CPUID_VID_AMD           "AuthenticAMD"
 #define        CPUID_VID_AMD           "AuthenticAMD"

-#define        CPUID_VID_CYRIX         "CyrixInstead"
-#define        CPUID_VID_NEXGEN        "NexGenDriven"
-#define CPUID_VID_CENTAUR       "CentaurHauls"
-#define CPUID_VID_RISE          "RiseRiseRise"
-#define CPUID_VID_SIS           "SiS SiS SiS "
-#define CPUID_VID_TRANSMETA     "GenuineTMx86"
-#define CPUID_VID_NSC           "Geode by NSC"
+
+#define CPUID_VMM_ID_VMWARE            "VMwareVMware"
+#define CPUID_VMM_ID_PARALLELS "Parallels\0\0\0"

 
 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
 
 
 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
 


@@ -56,53 +56,86 @@
  * The CPUID_FEATURE_XXX values define 64-bit values
  * returned in %ecx:%edx to a CPUID request with %eax of 1: 
  */
  * The CPUID_FEATURE_XXX values define 64-bit values
  * returned in %ecx:%edx to a CPUID request with %eax of 1: 
  */

-#define        CPUID_FEATURE_FPU     _Bit(0)   /* Floating point unit on-chip */
-#define        CPUID_FEATURE_VME     _Bit(1)   /* Virtual Mode Extension */
-#define        CPUID_FEATURE_DE      _Bit(2)   /* Debugging Extension */
-#define        CPUID_FEATURE_PSE     _Bit(3)   /* Page Size Extension */
-#define        CPUID_FEATURE_TSC     _Bit(4)   /* Time Stamp Counter */
-#define        CPUID_FEATURE_MSR     _Bit(5)   /* Model Specific Registers */
-#define CPUID_FEATURE_PAE     _Bit(6)  /* Physical Address Extension */
-#define        CPUID_FEATURE_MCE     _Bit(7)   /* Machine Check Exception */
-#define        CPUID_FEATURE_CX8     _Bit(8)   /* CMPXCHG8B */
-#define        CPUID_FEATURE_APIC    _Bit(9)   /* On-chip APIC */
-#define CPUID_FEATURE_SEP     _Bit(11) /* Fast System Call */
-#define        CPUID_FEATURE_MTRR    _Bit(12)  /* Memory Type Range Register */
-#define        CPUID_FEATURE_PGE     _Bit(13)  /* Page Global Enable */
-#define        CPUID_FEATURE_MCA     _Bit(14)  /* Machine Check Architecture */
-#define        CPUID_FEATURE_CMOV    _Bit(15)  /* Conditional Move Instruction */
-#define CPUID_FEATURE_PAT     _Bit(16) /* Page Attribute Table */
-#define CPUID_FEATURE_PSE36   _Bit(17) /* 36-bit Page Size Extension */
-#define CPUID_FEATURE_PSN     _Bit(18) /* Processor Serial Number */
-#define CPUID_FEATURE_CLFSH   _Bit(19) /* CLFLUSH Instruction supported */
-#define CPUID_FEATURE_DS      _Bit(21) /* Debug Store */
-#define CPUID_FEATURE_ACPI    _Bit(22) /* Thermal monitor and Clock Ctrl */
-#define CPUID_FEATURE_MMX     _Bit(23) /* MMX supported */
-#define CPUID_FEATURE_FXSR    _Bit(24) /* Fast floating pt save/restore */
-#define CPUID_FEATURE_SSE     _Bit(25) /* Streaming SIMD extensions */
-#define CPUID_FEATURE_SSE2    _Bit(26) /* Streaming SIMD extensions 2 */
-#define CPUID_FEATURE_SS      _Bit(27) /* Self-Snoop */
-#define CPUID_FEATURE_HTT     _Bit(28) /* Hyper-Threading Technology */
-#define CPUID_FEATURE_TM      _Bit(29) /* Thermal Monitor (TM1) */
-#define CPUID_FEATURE_PBE     _Bit(31) /* Pend Break Enable */
-
-#define CPUID_FEATURE_SSE3    _HBit(0) /* Prescott New Inst. */
-#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
-#define CPUID_FEATURE_DSCPL   _HBit(4) /* Debug Store CPL */
-#define CPUID_FEATURE_VMX     _HBit(5) /* VMX */
-#define CPUID_FEATURE_SMX     _HBit(6) /* SMX */
-#define CPUID_FEATURE_EST     _HBit(7) /* Enhanced SpeedsTep (GV3) */
-#define CPUID_FEATURE_TM2     _HBit(8) /* Thermal Monitor 2 */
-#define CPUID_FEATURE_SSSE3   _HBit(9) /* Supplemental SSE3 instructions */
-#define CPUID_FEATURE_MNI     CPUID_FEATURE_SSSE3
-#define CPUID_FEATURE_CID     _HBit(10)        /* L1 Context ID */
-#define CPUID_FEATURE_CX16    _HBit(13)        /* CmpXchg16b instruction */
-#define CPUID_FEATURE_xTPR    _HBit(14)        /* Send Task PRiority msgs */
-#define CPUID_FEATURE_PDCM    _HBit(15)        /* Perf/Debug Capability MSR */
-#define CPUID_FEATURE_DCA     _HBit(18)        /* Direct Cache Control */
-#define CPUID_FEATURE_SSE4_1  _HBit(19)        /* Streaming SIMD extensions 4.1 */
-#define CPUID_FEATURE_SSE4_2  _HBit(20)        /* Streaming SIMD extensions 4.2 */
-#define CPUID_FEATURE_POPCNT  _HBit(23)        /* POPCNT instruction */
+#define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
+#define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
+#define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
+#define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
+#define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
+#define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
+#define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
+#define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
+#define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
+#define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
+#define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
+#define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
+#define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
+#define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
+#define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
+#define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
+#define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
+#define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
+#define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
+#define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
+#define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
+#define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
+#define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
+#define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
+#define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
+#define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
+#define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
+#define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
+#define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
+ 
+#define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
+#define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
+#define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
+#define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
+#define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
+#define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
+#define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
+#define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
+#define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
+#define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
+#define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
+#define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_FMA       _HBit(12) /* Fused-Multiply-Add support */
+#define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
+#define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
+#define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */
+
+#define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
+#define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
+#define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
+#define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
+#define CPUID_FEATURE_x2APIC    _HBit(21) /* Extended APIC Mode */
+#define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
+#define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
+#define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
+#define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
+#define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
+#define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
+#define CPUID_FEATURE_AVX1_0   _HBit(28) /* AVX 1.0 instructions */
+#define CPUID_FEATURE_F16C     _HBit(29) /* Float16 convert instructions */
+#define CPUID_FEATURE_RDRAND   _HBit(30) /* RDRAND instruction */
+#define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
+
+/*
+ * Leaf 7, subleaf 0 additional features.
+ * Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
+ */
+#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)   /* FS/GS base read/write */
+#define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)   /* TSC thread offset */
+#define CPUID_LEAF7_FEATURE_BMI1     _Bit(3)   /* Bit Manipulation Instrs, set 1 */
+#define CPUID_LEAF7_FEATURE_HLE      _Bit(4)   /* Hardware Lock Elision*/
+#define CPUID_LEAF7_FEATURE_AVX2     _Bit(5)   /* AVX2 Instructions */
+#define CPUID_LEAF7_FEATURE_SMEP     _Bit(7)   /* Supervisor Mode Execute Protect */
+#define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)   /* Bit Manipulation Instrs, set 2 */
+#define CPUID_LEAF7_FEATURE_ERMS     _Bit(9)   /* Enhanced Rep Movsb/Stosb */
+#define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)  /* INVPCID intruction, TDB */
+#define CPUID_LEAF7_FEATURE_RTM      _Bit(11)  /* RTM */
+#define CPUID_LEAF7_FEATURE_RDSEED   _Bit(18)  /* RDSEED Instruction */
+#define CPUID_LEAF7_FEATURE_ADX      _Bit(19)  /* ADX Instructions */
+#define CPUID_LEAF7_FEATURE_SMAP     _Bit(20)  /* Supervisor Mode Access Protect */

 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 
 /*
  * The CPUID_EXTFEATURE_XXX values define 64-bit values


@@ -110,216 +143,72 @@
  */
 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)    /* SYSCALL/sysret */
 #define CPUID_EXTFEATURE_XD       _Bit(20)     /* eXecute Disable */
  */
 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)    /* SYSCALL/sysret */
 #define CPUID_EXTFEATURE_XD       _Bit(20)     /* eXecute Disable */

+
+#define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)    /* 1GB pages */
+#define CPUID_EXTFEATURE_RDTSCP           _Bit(27)     /* RDTSCP */

 #define CPUID_EXTFEATURE_EM64T    _Bit(29)     /* Extended Mem 64 Technology */
 
 #define CPUID_EXTFEATURE_EM64T    _Bit(29)     /* Extended Mem 64 Technology */
 

-#define CPUID_EXTFEATURE_LAHF     _HBit(20)    /* LAFH/SAHF instructions */
-
-
-#define        CPUID_TYPE_OEM              0x0 /* Original processor */
-#define        CPUID_TYPE_OVERDRIVE        0x1 /* Overdrive processor */
-#define        CPUID_TYPE_DUAL             0x2 /* Can be used as dual processor */
-#define        CPUID_TYPE_RESERVED         0x3 /* Reserved */
-
-#define        CPUID_FAMILY_386            0x3 /* Intel 386 (not part of CPUID) */
-
-#define        CPUID_MODEL_I386_DX         0x0 /* Intel 386 (not part of CPUID) */
-
-#define        CPUID_FAMILY_486            0x4 /* Intel 486 */
-
-#define        CPUID_MODEL_I486_DX         0x0 /* Intel 486DX */
-#define        CPUID_MODEL_I486_DX_S       0x1 /* Intel 486DX-S */
-#define        CPUID_MODEL_I486_SX         0x2 /* Intel 486SX */
-#define        CPUID_MODEL_I486_DX2        0x3 /* Intel 486DX2 */
-#define        CPUID_MODEL_I486_SL         0x4 /* Intel 486SL */
-#define        CPUID_MODEL_I486_SX2        0x5 /* Intel 486SX2 */
-#define        CPUID_MODEL_I486_DX2WB      0x7 /* Intel 486DX2WB */
-#define        CPUID_MODEL_I486_DX4        0x8 /* Intel 486DX4 */
-#define        CPUID_MODEL_I486_DX4WB      0x9 /* Intel 486DX4WB */
-
-#define        CPUID_MODEL_AM486_DX        0x1 /* AMD 486DX */
-#define        CPUID_MODEL_AM486_DX2       0x3 /* AMD 486DX2 */
-#define        CPUID_MODEL_AM486_DX2WB     0x7 /* AMD 486DX2WB */
-#define        CPUID_MODEL_AM486_DX4       0x8 /* AMD 486DX4 */
-#define        CPUID_MODEL_AM486_DX4WB     0x9 /* AMD 486DX4WB */
-#define        CPUID_MODEL_AM486_5X86      0xE /* AMD 5x86 */
-#define        CPUID_MODEL_AM486_5X86WB    0xF /* AMD 5x86WB */
-
-#define CPUID_MODEL_MEDIAGX         0x4 /* Cyrix MediaGX */
-#define        CPUID_MODEL_CYRIX5X86       0x9 /* CYRIX 5X86 */
-
-#define        CPUID_FAMILY_586            0x5 /* Intel Pentium, AMD K5/K6*/
-
-#define        CPUID_MODEL_UMC5D           0x1 /* UMC U5D */
-#define        CPUID_MODEL_UMC5S           0x2 /* UMC U5S */
-#define        CPUID_MODEL_UMC486_DX2      0x3 /* UMC U486_DX2 */
-#define        CPUID_MODEL_UMC486_SX2      0x5 /* UMC U486_SX2 */
-
-#define        CPUID_MODEL_P5A             0x0 /* Intel P5 60/66 Step A */
-#define        CPUID_MODEL_P5              0x1 /* Intel P5 60/66 */
-#define        CPUID_MODEL_P54             0x2 /* Intel P5 75/80/100/120/133/166 */
-#define        CPUID_MODEL_P24T            0x3 /* Intel P5 Overdrive 63/83 */
-
-#define CPUID_MODEL_K5M0            0x0 /* AMD-K5 Model 0 */
-#define CPUID_MODEL_K5M1            0x1 /* AMD-K5 Model 1 */
-#define CPUID_MODEL_K5M2            0x2 /* AMD-K5 Model 2 */
-#define CPUID_MODEL_K5M3            0x3 /* AMD-K5 Model 3 */
-#define CPUID_MODEL_K6M6            0x6 /* AMD-K6 Model 6 */
-#define CPUID_MODEL_K6M7            0x7 /* AMD-K6 Model 7 */
-#define CPUID_MODEL_K6_2            0x8 /* AMD-K6-2 Model 8 */
-#define CPUID_MODEL_K6_III          0x9 /* AMD-K6-III Model 9 */
-
-#define CPUID_MODEL_CYRIX_M1              0x2 /* Cyrix M1 */
-#define CPUID_MODEL_MEDIAGX_MMX           0x4 /* Cyrix MediaGX MMX Enhanced */
-
-#define        CPUID_FAMILY_686            0x6 /* Intel Pentium Pro, II, III; AMD Athlon */
-
-#define        CPUID_MODEL_P6              0x1 /* Intel P6 */
-#define        CPUID_MODEL_PII             0x3 /* Intel PII */
-#define CPUID_MODEL_P65             0x5 /* Intel PII/Xeon/Celeron model 5 */
-#define CPUID_MODEL_P66             0x6 /* Intel Celeron model 6 */
-#define CPUID_MODEL_P67             0x7 /* Intel PIII/Xeon model 7 */
-#define CPUID_MODEL_P68             0x8 /* Intel PIII/Xeon/Celeron model 8 */
-#define CPUID_MODEL_PM9             0x9 /* Intel Pentium M model 9 */
-#define CPUID_MODEL_P6A             0xA /* Intel PIII Xeon model A */
-#define CPUID_MODEL_P6B             0xB /* Intel PIII model B */
-#define CPUID_MODEL_PMD             0xD /* Intel Pentium M model D */
-#define CPUID_MODEL_CORE            0xE /* Intel Core Solo & Duo */
-#define CPUID_MODEL_YONAH           CPUID_MODEL_YONAH
-#define CPUID_MODEL_CORE2          0xF /* Intel Core2 Duo */
-#define CPUID_MODEL_MEROM           CPUID_MODEL_CORE2
-#define CPUID_MODEL_PENRYN          0x17
-
-#define CPUID_MODEL_ATHLON_M1       0x1 /* AMD Athlon Model 1 */
-#define CPUID_MODEL_ATHLON_M2       0x2 /* AMD Athlon Model 2 */
-#define CPUID_MODEL_DURON_M3        0x3 /* AMD Duron Model 3 */
-#define CPUID_MODEL_ATHLON_M4       0x4 /* AMD Athlon Model 4 */
-#define CPUID_MODEL_ATHLON_M6       0x6 /* (Mobile) AMD Athlon/Duron MP/XP/4 Model 6 */
-#define CPUID_MODEL_DURON_M7        0x7 /* (Mobile) AMD Duron Model 7 */
-#define CPUID_MODEL_ATHLON_M8       0x8 /* (Mobile) Athlon XP/MP/XP-M Model 8 */
-#define CPUID_MODEL_ATHLON_M10      0xA /* (Mobile) AMD Athlon XP/MP/XP-M/XP-M(LV) Model 10 */
-
-#define CPUID_MODEL_CYRIX_M2        0x0 /* Cyrix M2 */
-#define CPUID_MODEL_CYRIX_MII       0x2 /* VIA Cyrix MII (6x86MX) */
-#define CPUID_MODEL_VIA_CYRIX_M2    0x5 /* VIA C3 Cyrix M2 */
-#define CPUID_MODEL_WINCHIP_C5A     0x6 /* VIA C3 WinChip C5A */
-#define CPUID_MODEL_WINCHIP_C5BC    0x7 /* VIA C3 WinChip C5B/C5C */
-#define CPUID_MODEL_WINCHIP_C5N     0x8 /* VIA C3 WinChip C5N */
-#define CPUID_MODEL_WINCHIP_C5XLP   0x9 /* VIA C3 WinChip C5P */
-
-#define CPUID_MODEL_NX586           0x0 /* NexGen Nx586 */
-
-#define CPUID_MODEL_RISE_MP6_0      0x0 /* Rise mP6 */
-#define CPUID_MODEL_RISE_MP6_2      0x2 /* Rise mP6 */
-
-#define CPUID_MODEL_SIS_55X         0x0 /* SIS 55x */
-
-#define CPUID_MODEL_TM_CRUSOE       0x4 /* Transmeta Crusoe TM3x00 and TM5x00 */
-
-#define CPUID_MODEL_CENTAUR_C6            0x4 /* Centaur C6 */
-#define CPUID_MODEL_CENTAUR_C2            0x8 /* Centaur C2 */
-#define CPUID_MODEL_CENTAUR_C3            0x9 /* Centaur C3 */
-
-#define CPUID_MODEL_GX1               0x4 /* AMD Geode GX1 */
-#define CPUID_MODEL_GX2               0x5 /* AMD Geode GX */
-
-#define        CPUID_FAMILY_ITANIUM        0x7 /* Intel Intanium */
-#define CPUID_FAMILY_EXTENDED       0xF /* Intel Pentium 4, Itanium II */
-
-#define CPUID_EXTFAMILY_PENTIUM4    0x0 /* Intel Pentium 4 */
-#define CPUID_EXTFAMILY_ITANIUM2    0x1 /* Intel Itanium 2 */
-
-#define CPUID_MODEL_ATHLON64        0x4 /* AMD Athlon 64 Model 4 */
-#define CPUID_MODEL_OPTERON         0x5 /* AMD Opteron Model 4 */
-
-#define CPUID_BRAND_UNSUPPORTED     0x00
-#define CPUID_BRAND_CELERON_1       0x01 /* Intel Celeron */
-#define CPUID_BRAND_PENTIUM_III_2   0x02 /* Intel Pentium III */
-#define CPUID_BRAND_PIII_XEON       0x03 /* Intel Pentium III Xeon / Celeron */
-#define CPUID_BRAND_PENTIUM_III_4   0x04 /* Intel Pentium III */
-#define CPUID_BRAND_PENTIUM_III_M   0x05 /* Mobile Intel Pentium III-M */
-#define CPUID_BRAND_M_CELERON_7     0x07 /* Mobile Intel Celeron */
-#define CPUID_BRAND_PENTIUM4_8      0x08 /* Intel Pentium 4 */
-#define CPUID_BRAND_PENTIUM4_9      0x09 /* Intel Pentium 4 */
-#define CPUID_BRAND_CELERON_A       0x0A /* Intel Celeron */
-#define CPUID_BRAND_XEON            0x0B /* Intel Xeon (MP) */
-#define CPUID_BRAND_XEON_MP         0x0C /* Intel Xeon MP */
-#define CPUID_BRAND_PENTIUM4_M      0x0E /* Mobile Intel Pentium 4-M / Xeon */
-#define CPUID_BRAND_M_CELERON_F     0x0F /* Mobile Intel Celeron */
-#define CPUID_BRAND_MOBILE_17       0x11 /* Mobile Genuine Intel */
-#define CPUID_BRAND_CELERON_M       0x12 /* Intel Celeron M */
-#define CPUID_BRAND_M_CELERON_13    0x13 /* Mobile Intel Celeron */
-#define CPUID_BRAND_CELERON_14      0x14 /* Intel Celeron */
-#define CPUID_BRAND_MOBILE_15       0x15 /* Mobile Genuine Intel */
-#define CPUID_BRAND_PENTIUM_M       0x16 /* Intel Pentium M */
-#define CPUID_BRAND_M_CELERON_17    0x17 /* Mobile Intel Celeron */
-
-#define        CPUID_CACHE_SIZE        16      /* Number of descriptor vales */
-
-#define        CPUID_CACHE_NULL           0x00 /* NULL */
-#define        CPUID_CACHE_ITLB_4K        0x01 /* Instruction TLB: 4K pages */
-#define        CPUID_CACHE_ITLB_4M        0x02 /* Instruction TLB: 4M pages */
-#define        CPUID_CACHE_DTLB_4K        0x03 /* Data TLB: 4K pages */
-#define        CPUID_CACHE_DTLB_4M        0x04 /* Data TLB: 4M pages */
-#define        CPUID_CACHE_ICACHE_8K      0x06 /* Instruction cache: 8K */
-#define        CPUID_CACHE_ICACHE_16K     0x08 /* Instruction cache: 16K */
-#define        CPUID_CACHE_DCACHE_8K      0x0A /* Data cache: 8K */
-#define        CPUID_CACHE_DCACHE_16K     0x0C /* Data cache: 16K */
-#define CPUID_CACHE_L3_512K        0x22 /* L3: 512K */
-#define CPUID_CACHE_L3_1M          0x23 /* L3: 1M */
-#define CPUID_CACHE_L3_2M          0x25 /* L3: 2M */
-#define CPUID_CACHE_L3_4M          0x29 /* L3: 4M */
-#define CPUID_CACHE_DCACHE_32K     0x2C /* Data cache: 32K, 8-way */
-#define CPUID_CACHE_ICACHE_32K     0x30 /* Instruction cache: 32K, 8-way */
-#define CPUID_CACHE_L2_128K_S4     0x39 /* L2: 128K, 4-way, sectored */
-#define CPUID_CACHE_L2_128K_S2     0x3B /* L2: 128K, 2-way, sectored */
-#define CPUID_CACHE_L2_256K_S4     0x3C /* L2: 256K, 4-way, sectored */
-#define CPUID_CACHE_NOCACHE        0x40 /* No 2nd level or 3rd-level cache */
-#define        CPUID_CACHE_L2_128K        0x41 /* L2: 128K */
-#define        CPUID_CACHE_L2_256K        0x42 /* L2: 256K */
-#define        CPUID_CACHE_L2_512K        0x43 /* L2: 512K */
-#define        CPUID_CACHE_L2_1M_4        0x44 /* L2: 1M, 4-way */
-#define        CPUID_CACHE_L2_2M_4        0x45 /* L2: 2M, 4-way */
-#define CPUID_CACHE_L3_4M_4_64     0x46 /* L3:  4M,  4-way, 64 bytes */
-#define CPUID_CACHE_L3_8M_8_64     0x47 /* L3:  8M,  8-way, 64 bytes*/
-#define CPUID_CACHE_L2_4M_16_64    0x49 /* L2:  4M, 16-way, 64 bytes */
-#define CPUID_CACHE_L2_6M_12_64    0x4A /* L2:  6M, 12-way, 64 bytes */
-#define CPUID_CACHE_L2_8M_16_64    0x4B /* L2:  8M, 16-way, 64 bytes */
-#define CPUID_CACHE_L2_12M_12_64   0x4C /* L2: 12M, 12-way, 64 bytes */
-#define CPUID_CACHE_L2_16M_16_64   0x4D /* L2: 16M, 16-way, 64 bytes */
-#define CPUID_CACHE_L2_6M_24_64    0x4E /* L2:  6M, 24-way, 64 bytes */
-#define CPUID_CACHE_ITLB_64        0x50 /* Instruction TLB: 64 entries */
-#define CPUID_CACHE_ITLB_128       0x51 /* Instruction TLB: 128 entries */
-#define CPUID_CACHE_ITLB_256       0x52 /* Instruction TLB: 256 entries */
-#define CPUID_CACHE_DTLB_64        0x5B /* Data TLB: 64 entries */
-#define CPUID_CACHE_DTLB_128       0x5C /* Data TLB: 128 entries */
-#define CPUID_CACHE_DTLB_256       0x5D /* Data TLB: 256 entries */
-#define        CPUID_CACHE_DCACHE_16K_8_64 0x60 /* Data cache: 16K, 8-way, 64 bytes */
-#define        CPUID_CACHE_DCACHE_8K_4_64  0x66 /* Data cache:  8K, 4-way, 64 bytes */
-#define        CPUID_CACHE_DCACHE_16K_4_64 0x67 /* Data cache: 16K, 4-way, 64 bytes */
-#define        CPUID_CACHE_DCACHE_32K_4_64 0x68 /* Data cache: 32K, 4-way, 64 bytes */
-#define CPUID_CACHE_TRACE_12K_8    0x70 /* Trace cache 12K-uop, 8-way */
-#define CPUID_CACHE_TRACE_16K_8    0x71 /* Trace cache 16K-uop, 8-way */
-#define CPUID_CACHE_TRACE_32K_8    0x72 /* Trace cache 32K-uop, 8-way */
-#define        CPUID_CACHE_L2_1M_4_64     0x78 /* L2:   1M, 4-way, 64 bytes */
-#define        CPUID_CACHE_L2_128K_8_64_2 0x79 /* L2: 128K, 8-way, 64b, 2 lines/sec */
-#define        CPUID_CACHE_L2_256K_8_64_2 0x7A /* L2: 256K, 8-way, 64b, 2 lines/sec */
-#define        CPUID_CACHE_L2_512K_8_64_2 0x7B /* L2: 512K, 8-way, 64b, 2 lines/sec */
-#define        CPUID_CACHE_L2_1M_8_64_2   0x7C /* L2:   1M, 8-way, 64b, 2 lines/sec */
-#define        CPUID_CACHE_L2_2M_8_64     0x7D /* L2:   2M, 8-way, 64 bytes */
-#define        CPUID_CACHE_L2_512K_2_64   0x7F /* L2: 512K, 2-way, 64 bytes */
-#define CPUID_CACHE_L2_256K_8_32   0x82 /* L2: 256K, 8-way, 32 bytes */
-#define CPUID_CACHE_L2_512K_8_32   0x83 /* L2: 512K, 8-way, 32 bytes */
-#define CPUID_CACHE_L2_1M_8_32     0x84 /* L2:   1M, 8-way, 32 bytes */
-#define CPUID_CACHE_L2_2M_8_32     0x85 /* L2:   2M, 8-way, 32 bytes */
-#define CPUID_CACHE_L2_512K_4_64   0x86 /* L2: 512K, 4-way, 64 bytes */
-#define CPUID_CACHE_L2_1M_8_64     0x87 /* L2:   1M, 8-way, 64 bytes */
-#define CPUID_CACHE_ITLB_4K_128_4  0xB0 /* ITLB: 4KB, 128 entries, 4-way */
-#define CPUID_CACHE_ITLB_4M_4_4    0xB1 /* ITLB: 4MB,   4 entries, 4-way, or  */
-#define CPUID_CACHE_ITLB_2M_8_4    0xB1 /* ITLB: 2MB,   8 entries, 4-way */
-#define CPUID_CACHE_DTLB_4K_128_4  0xB3 /* DTLB: 4KB, 128 entries, 4-way */
-#define CPUID_CACHE_DTLB_4K_256_4  0xB3 /* DTLB: 4KB, 256 entries, 4-way */
-#define CPUID_CACHE_PREFETCH_64    0xF0 /* 64-Byte Prefetching */
-#define CPUID_CACHE_PREFETCH_128   0xF1 /* 128-Byte Prefetching */
+#define CPUID_EXTFEATURE_LAHF     _HBit(0)     /* LAFH/SAHF instructions */
+#define CPUID_EXTFEATURE_LZCNT     _HBit(5)    /* LZCNT instruction */
+#define CPUID_EXTFEATURE_PREFETCHW _HBit(8)    /* PREFETCHW instruction */
+
+/*
+ * The CPUID_EXTFEATURE_XXX values define 64-bit values
+ * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: 
+ */
+#define CPUID_EXTFEATURE_TSCI      _Bit(8)     /* TSC Invariant */
+
+/*
+ * CPUID_X86_64_H_FEATURE_SUBSET and CPUID_X86_64_H_LEAF7_FEATURE_SUBSET
+ * indicate the bitmask of features that must be present before the system
+ * is eligible to run the "x86_64h" "Haswell feature subset" slice.
+ */
+#define CPUID_X86_64_H_FEATURE_SUBSET ( CPUID_FEATURE_FMA    | \
+                                        CPUID_FEATURE_SSE4_2 | \
+                                        CPUID_FEATURE_MOVBE  | \
+                                        CPUID_FEATURE_POPCNT | \
+                                        CPUID_FEATURE_AVX1_0   \
+                                      )
+
+#define CPUID_X86_64_H_EXTFEATURE_SUBSET ( CPUID_EXTFEATURE_LZCNT \
+                                         )
+
+#define CPUID_X86_64_H_LEAF7_FEATURE_SUBSET ( CPUID_LEAF7_FEATURE_BMI1 | \
+                                              CPUID_LEAF7_FEATURE_AVX2 | \
+                                              CPUID_LEAF7_FEATURE_BMI2   \
+                                            )
+
+#define        CPUID_CACHE_SIZE        16      /* Number of descriptor values */
+
+#define CPUID_MWAIT_EXTENSION  _Bit(0) /* enumeration of WMAIT extensions */
+#define CPUID_MWAIT_BREAK      _Bit(1) /* interrupts are break events     */
+
+#define CPUID_MODEL_YONAH              0x0E
+#define CPUID_MODEL_MEROM              0x0F
+#define CPUID_MODEL_PENRYN             0x17
+#define CPUID_MODEL_NEHALEM            0x1A
+#define CPUID_MODEL_FIELDS             0x1E    /* Lynnfield, Clarksfield */
+#define CPUID_MODEL_DALES              0x1F    /* Havendale, Auburndale */
+#define CPUID_MODEL_NEHALEM_EX         0x2E
+#define CPUID_MODEL_DALES_32NM         0x25    /* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE           0x2C    /* Gulftown, Westmere-EP/-WS */
+#define CPUID_MODEL_WESTMERE_EX                0x2F
+#define CPUID_MODEL_SANDYBRIDGE                0x2A
+#define CPUID_MODEL_JAKETOWN           0x2D
+#define CPUID_MODEL_IVYBRIDGE          0x3A
+#define CPUID_MODEL_IVYBRIDGE_EP       0x3E
+#define CPUID_MODEL_CRYSTALWELL                0x46
+#define CPUID_MODEL_HASWELL            0x3C
+#define CPUID_MODEL_HASWELL_EP         0x3F
+#define CPUID_MODEL_HASWELL_ULT                0x45
+#define CPUID_MODEL_BROADWELL          0x3D
+#define CPUID_MODEL_BROADWELL_ULX      0x3D
+#define CPUID_MODEL_BROADWELL_ULT      0x3D
+#define CPUID_MODEL_BRYSTALWELL                0x47
+
+#define CPUID_VMM_FAMILY_UNKNOWN       0x0
+#define CPUID_VMM_FAMILY_VMWARE                0x1
+#define CPUID_VMM_FAMILY_PARALLELS     0x2

 
 #ifndef ASSEMBLER
 #include <stdint.h>
 
 #ifndef ASSEMBLER
 #include <stdint.h>


@@ -332,7 +221,7 @@ typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
 static inline void
 cpuid(uint32_t *data)
 {
 static inline void
 cpuid(uint32_t *data)
 {

-       asm("cpuid"
+       __asm__ volatile ("cpuid"

                : "=a" (data[eax]),
                  "=b" (data[ebx]),
                  "=c" (data[ecx]),
                : "=a" (data[eax]),
                  "=b" (data[ebx]),
                  "=c" (data[ecx]),


@@ -342,20 +231,24 @@ cpuid(uint32_t *data)
                  "c"  (data[ecx]),
                  "d"  (data[edx]));
 }
                  "c"  (data[ecx]),
                  "d"  (data[edx]));
 }

+

 static inline void
 do_cpuid(uint32_t selector, uint32_t *data)
 {
 static inline void
 do_cpuid(uint32_t selector, uint32_t *data)
 {

-       asm("cpuid"
+       __asm__ volatile ("cpuid"

                : "=a" (data[0]),
                  "=b" (data[1]),
                  "=c" (data[2]),
                  "=d" (data[3])
                : "=a" (data[0]),
                  "=b" (data[1]),
                  "=c" (data[2]),
                  "=d" (data[3])

-               : "a"(selector));
+               : "a"(selector),
+                 "b" (0),
+                 "c" (0),
+                 "d" (0));

 }
 
 /*
 }
 
 /*

- * Cache ID descriptor structure.
- * Note: description string absent in kernel.
+ * Cache ID descriptor structure, used to parse CPUID leaf 2.
+ * Note: not used in kernel.

  */
 typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; 
 typedef struct {
  */
 typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ; 
 typedef struct {


@@ -376,13 +269,53 @@ typedef struct {
        { value, type, size, linesize }
 #endif /* KERNEL */
 
        { value, type, size, linesize }
 #endif /* KERNEL */
 

+/* Monitor/mwait Leaf: */
+typedef struct {
+       uint32_t        linesize_min;
+       uint32_t        linesize_max;
+       uint32_t        extensions;
+       uint32_t        sub_Cstates;
+} cpuid_mwait_leaf_t;
+
+/* Thermal and Power Management Leaf: */
+typedef struct {
+       boolean_t       sensor;
+       boolean_t       dynamic_acceleration;
+       boolean_t       invariant_APIC_timer;
+       boolean_t       core_power_limits;
+       boolean_t       fine_grain_clock_mod;
+       boolean_t       package_thermal_intr;
+       uint32_t        thresholds;
+       boolean_t       ACNT_MCNT;
+       boolean_t       hardware_feedback;
+       boolean_t       energy_policy;
+} cpuid_thermal_leaf_t;
+
+
+/* XSAVE Feature Leaf: */
+typedef struct {
+       uint32_t        extended_state[4];      /* eax .. edx */
+} cpuid_xsave_leaf_t;
+
+
+/* Architectural Performance Monitoring Leaf: */
+typedef struct {
+       uint8_t         version;
+       uint8_t         number;
+       uint8_t         width;
+       uint8_t         events_number;
+       uint32_t        events;
+       uint8_t         fixed_number;
+       uint8_t         fixed_width;
+} cpuid_arch_perf_leaf_t;
+

 /* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
 typedef struct {
        char            cpuid_vendor[16];
        char            cpuid_brand_string[48];
        const char      *cpuid_model_string;
 
 /* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
 typedef struct {
        char            cpuid_vendor[16];
        char            cpuid_brand_string[48];
        const char      *cpuid_model_string;
 

-       cpu_type_t      cpuid_type;                                     /* this is *not* a cpu_type_t in our <mach/machine.h> */
+       cpu_type_t      cpuid_type;     /* this is *not* a cpu_type_t in our <mach/machine.h> */

        uint8_t         cpuid_family;
        uint8_t         cpuid_model;
        uint8_t         cpuid_extmodel;
        uint8_t         cpuid_family;
        uint8_t         cpuid_model;
        uint8_t         cpuid_extmodel;


@@ -392,6 +325,7 @@ typedef struct {
        uint64_t        cpuid_extfeatures;
        uint32_t        cpuid_signature;
        uint8_t         cpuid_brand; 
        uint64_t        cpuid_extfeatures;
        uint32_t        cpuid_signature;
        uint8_t         cpuid_brand; 

+       uint8_t         cpuid_processor_flag;

        
        uint32_t        cache_size[LCACHE_MAX];
        uint32_t        cache_linesize;
        
        uint32_t        cache_size[LCACHE_MAX];
        uint32_t        cache_linesize;


@@ -401,11 +335,66 @@ typedef struct {
        uint32_t        cpuid_cores_per_package;
        uint32_t        cpuid_logical_per_package;
        uint32_t        cache_sharing[LCACHE_MAX];
        uint32_t        cpuid_cores_per_package;
        uint32_t        cpuid_logical_per_package;
        uint32_t        cache_sharing[LCACHE_MAX];

+       uint32_t        cache_partitions[LCACHE_MAX];

 
 

-       cpu_type_t              cpuid_cpu_type;                 /* <mach/machine.h> */
+       cpu_type_t      cpuid_cpu_type;                 /* <mach/machine.h> */

        cpu_subtype_t   cpuid_cpu_subtype;              /* <mach/machine.h> */  
        cpu_subtype_t   cpuid_cpu_subtype;              /* <mach/machine.h> */  

+
+       /* Per-vendor info */
+       cpuid_mwait_leaf_t      cpuid_mwait_leaf;       
+#define cpuid_mwait_linesize_max       cpuid_mwait_leaf.linesize_max
+#define cpuid_mwait_linesize_min       cpuid_mwait_leaf.linesize_min
+#define cpuid_mwait_extensions         cpuid_mwait_leaf.extensions
+#define cpuid_mwait_sub_Cstates                cpuid_mwait_leaf.sub_Cstates
+       cpuid_thermal_leaf_t    cpuid_thermal_leaf;
+       cpuid_arch_perf_leaf_t  cpuid_arch_perf_leaf;
+       uint32_t        unused[4];                      /* cpuid_xsave_leaf */
+
+       /* Cache details: */
+       uint32_t        cpuid_cache_linesize;
+       uint32_t        cpuid_cache_L2_associativity;
+       uint32_t        cpuid_cache_size;
+
+       /* Virtual and physical address aize: */
+       uint32_t        cpuid_address_bits_physical;
+       uint32_t        cpuid_address_bits_virtual;
+
+       uint32_t        cpuid_microcode_version;
+
+       /* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
+       uint32_t        cpuid_tlb[2][2][2];
+                       #define TLB_INST        0
+                       #define TLB_DATA        1
+                       #define TLB_SMALL       0
+                       #define TLB_LARGE       1
+       uint32_t        cpuid_stlb;
+
+       uint32_t        core_count;
+       uint32_t        thread_count;
+
+       /* Max leaf ids available from CPUID */
+       uint32_t        cpuid_max_basic;
+       uint32_t        cpuid_max_ext;
+
+       /* Family-specific info links */
+       uint32_t                cpuid_cpufamily;
+       cpuid_mwait_leaf_t      *cpuid_mwait_leafp;     
+       cpuid_thermal_leaf_t    *cpuid_thermal_leafp;
+       cpuid_arch_perf_leaf_t  *cpuid_arch_perf_leafp;
+       cpuid_xsave_leaf_t      *cpuid_xsave_leafp;
+       uint64_t                cpuid_leaf7_features;
+       cpuid_xsave_leaf_t      cpuid_xsave_leaf[2];

 } i386_cpu_info_t;
 
 } i386_cpu_info_t;
 

+#ifdef MACH_KERNEL_PRIVATE
+typedef struct {
+       char            cpuid_vmm_vendor[16];
+       uint32_t        cpuid_vmm_family;
+       uint32_t        cpuid_vmm_bus_frequency;
+       uint32_t        cpuid_vmm_tsc_frequency;
+} i386_vmm_info_t;
+#endif
+

 #ifdef __cplusplus
 extern "C" {
 #endif
 #ifdef __cplusplus
 extern "C" {
 #endif


@@ -420,16 +409,23 @@ extern void               cpuid_feature_display(const char *);
 extern void            cpuid_extfeature_display(const char *);
 extern char *          cpuid_get_feature_names(uint64_t, char *, unsigned);
 extern char *          cpuid_get_extfeature_names(uint64_t, char *, unsigned);
 extern void            cpuid_extfeature_display(const char *);
 extern char *          cpuid_get_feature_names(uint64_t, char *, unsigned);
 extern char *          cpuid_get_extfeature_names(uint64_t, char *, unsigned);

+extern char *          cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);

 
 extern uint64_t                cpuid_features(void);
 extern uint64_t                cpuid_extfeatures(void);
 
 extern uint64_t                cpuid_features(void);
 extern uint64_t                cpuid_extfeatures(void);

+extern uint64_t                cpuid_leaf7_features(void);

 extern uint32_t                cpuid_family(void);
 extern uint32_t                cpuid_family(void);

+extern uint32_t                cpuid_cpufamily(void);

        
        

-extern void            cpuid_get_info(i386_cpu_info_t *info_p);

 extern i386_cpu_info_t *cpuid_info(void);
 extern i386_cpu_info_t *cpuid_info(void);

-

 extern void            cpuid_set_info(void);
 
 extern void            cpuid_set_info(void);
 

+#ifdef MACH_KERNEL_PRIVATE
+extern boolean_t       cpuid_vmm_present(void);
+extern i386_vmm_info_t *cpuid_vmm_info(void);
+extern uint32_t                cpuid_vmm_family(void);
+#endif
+

 #ifdef __cplusplus
 }
 #endif
 #ifdef __cplusplus
 }
 #endif