#define CPUID_VID_INTEL "GenuineIntel"
#define CPUID_VID_AMD "AuthenticAMD"
+#define CPUID_VMM_ID_VMWARE "VMwareVMware"
+
#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
#define _Bit(n) (1ULL << n)
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
+#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
+#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
+#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
-#define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
+#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
+#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
+#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
+#define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */
+#define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */
+
+/*
+ * Leaf 7, subleaf 0 additional features.
+ * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
+ */
+#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
+#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
+#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9) /* ENhanced Fast STRinG copy */
+#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */
+#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */
+#define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/
+#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */
+#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */
+#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */
+#define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* TBD */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
-#define CPUID_MODEL_YONAH 0x0E
-#define CPUID_MODEL_MEROM 0x0F
-#define CPUID_MODEL_PENRYN 0x17
-#define CPUID_MODEL_NEHALEM 0x1A
-#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield, Jasper */
-#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
-#define CPUID_MODEL_NEHALEM_EX 0x2E
-#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
-#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP, Westmere-WS */
-#define CPUID_MODEL_WESTMERE_EX 0x2F
-/* Additional internal models go here */
-#define CPUID_MODEL_SANDYBRIDGE 0x2A
-#define CPUID_MODEL_JAKETOWN 0x2D
+#define CPUID_MODEL_YONAH 0x0E
+#define CPUID_MODEL_MEROM 0x0F
+#define CPUID_MODEL_PENRYN 0x17
+#define CPUID_MODEL_NEHALEM 0x1A
+#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield */
+#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
+#define CPUID_MODEL_NEHALEM_EX 0x2E
+#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
+#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP/-WS */
+#define CPUID_MODEL_WESTMERE_EX 0x2F
+#define CPUID_MODEL_SANDYBRIDGE 0x2A
+#define CPUID_MODEL_JAKETOWN 0x2D
+#define CPUID_MODEL_IVYBRIDGE 0x3A
+#ifdef PRIVATE
+#define CPUID_MODEL_IVYBRIDGE_EP 0x3E
+#define CPUID_MODEL_CRYSTALWELL 0x46
+#endif
+#define CPUID_MODEL_HASWELL 0x3C
+#define CPUID_MODEL_HASWELL_SVR 0x3F
+#define CPUID_MODEL_HASWELL_ULT 0x45
+
+#define CPUID_VMM_FAMILY_UNKNOWN 0x0
+#define CPUID_VMM_FAMILY_VMWARE 0x1
#ifndef ASSEMBLER
#include <stdint.h>
uint64_t cpuid_extfeatures;
uint32_t cpuid_signature;
uint8_t cpuid_brand;
+ uint8_t cpuid_processor_flag;
uint32_t cache_size[LCACHE_MAX];
uint32_t cache_linesize;
cpuid_thermal_leaf_t *cpuid_thermal_leafp;
cpuid_arch_perf_leaf_t *cpuid_arch_perf_leafp;
cpuid_xsave_leaf_t *cpuid_xsave_leafp;
+ uint32_t cpuid_leaf7_features;
} i386_cpu_info_t;
+#ifdef MACH_KERNEL_PRIVATE
+typedef struct {
+ char cpuid_vmm_vendor[16];
+ uint32_t cpuid_vmm_family;
+ uint32_t cpuid_vmm_bus_frequency;
+ uint32_t cpuid_vmm_tsc_frequency;
+} i386_vmm_info_t;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
extern void cpuid_extfeature_display(const char *);
extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
+extern char * cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);
extern uint64_t cpuid_features(void);
extern uint64_t cpuid_extfeatures(void);
+extern uint64_t cpuid_leaf7_features(void);
extern uint32_t cpuid_family(void);
extern uint32_t cpuid_cpufamily(void);
-extern void cpuid_get_info(i386_cpu_info_t *info_p);
extern i386_cpu_info_t *cpuid_info(void);
-
extern void cpuid_set_info(void);
+#ifdef MACH_KERNEL_PRIVATE
+extern boolean_t cpuid_vmm_present(void);
+extern i386_vmm_info_t *cpuid_vmm_info(void);
+extern uint32_t cpuid_vmm_family(void);
+#endif
+
#ifdef __cplusplus
}
#endif
projects / apple / xnu.git / blobdiff