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1 /*
2 * Copyright (c) 2000-2020 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /* CMU_ENDHIST */
32 /*
33 * Mach Operating System
34 * Copyright (c) 1991,1990 Carnegie Mellon University
35 * All Rights Reserved.
36 *
37 * Permission to use, copy, modify and distribute this software and its
38 * documentation is hereby granted, provided that both the copyright
39 * notice and this permission notice appear in all copies of the
40 * software, derivative works or modified versions, and any portions
41 * thereof, and that both notices appear in supporting documentation.
42 *
43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
46 *
47 * Carnegie Mellon requests users of this software to return to
48 *
49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
50 * School of Computer Science
51 * Carnegie Mellon University
52 * Pittsburgh PA 15213-3890
53 *
54 * any improvements or extensions that they make and grant Carnegie Mellon
55 * the rights to redistribute these changes.
56 */
57
58 /*
59 */
60
61 /*
62 * Processor registers for i386 and i486.
63 */
64 #ifndef _I386_PROC_REG_H_
65 #define _I386_PROC_REG_H_
66
67 /*
68 * Model Specific Registers
69 */
70 #define MSR_P5_TSC 0x10 /* Time Stamp Register */
71 #define MSR_P5_CESR 0x11 /* Control and Event Select Register */
72 #define MSR_P5_CTR0 0x12 /* Counter #0 */
73 #define MSR_P5_CTR1 0x13 /* Counter #1 */
74
75 #define MSR_P5_CESR_PC 0x0200 /* Pin Control */
76 #define MSR_P5_CESR_CC 0x01C0 /* Counter Control mask */
77 #define MSR_P5_CESR_ES 0x003F /* Event Control mask */
78
79 #define MSR_P5_CESR_SHIFT 16 /* Shift to get Counter 1 */
80 #define MSR_P5_CESR_MASK (MSR_P5_CESR_PC|\
81 MSR_P5_CESR_CC|\
82 MSR_P5_CESR_ES) /* Mask Counter */
83
84 #define MSR_P5_CESR_CC_CLOCK 0x0100 /* Clock Counting (otherwise Event) */
85 #define MSR_P5_CESR_CC_DISABLE 0x0000 /* Disable counter */
86 #define MSR_P5_CESR_CC_CPL012 0x0040 /* Count if the CPL == 0, 1, 2 */
87 #define MSR_P5_CESR_CC_CPL3 0x0080 /* Count if the CPL == 3 */
88 #define MSR_P5_CESR_CC_CPL 0x00C0 /* Count regardless of the CPL */
89
90 #define MSR_P5_CESR_ES_DATA_READ 0x000000 /* Data Read */
91 #define MSR_P5_CESR_ES_DATA_WRITE 0x000001 /* Data Write */
92 #define MSR_P5_CESR_ES_DATA_RW 0x101000 /* Data Read or Write */
93 #define MSR_P5_CESR_ES_DATA_TLB_MISS 0x000010 /* Data TLB Miss */
94 #define MSR_P5_CESR_ES_DATA_READ_MISS 0x000011 /* Data Read Miss */
95 #define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */
96 #define MSR_P5_CESR_ES_DATA_RW_MISS 0x101001 /* Data Read or Write Miss */
97 #define MSR_P5_CESR_ES_HIT_EM 0x000101 /* Write (hit) to M|E state */
98 #define MSR_P5_CESR_ES_DATA_CACHE_WB 0x000110 /* Cache lines written back */
99 #define MSR_P5_CESR_ES_EXTERNAL_SNOOP 0x000111 /* External Snoop */
100 #define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */
101 #define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */
102 #define MSR_P5_CESR_ES_BANK_CONFLICTS 0x001010 /* Bank conflicts */
103 #define MSR_P5_CESR_ES_MISALIGNED 0x001011 /* Misaligned Memory or I/O */
104 #define MSR_P5_CESR_ES_CODE_READ 0x001100 /* Code Read */
105 #define MSR_P5_CESR_ES_CODE_TLB_MISS 0x001101 /* Code TLB miss */
106 #define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */
107 #define MSR_P5_CESR_ES_SEGMENT_LOADED 0x001111 /* Any segment reg. loaded */
108 #define MSR_P5_CESR_ES_BRANCHE 0x010010 /* Branches */
109 #define MSR_P5_CESR_ES_BTB_HIT 0x010011 /* BTB Hits */
110 #define MSR_P5_CESR_ES_BRANCHE_BTB 0x010100 /* Taken branch or BTB Hit */
111 #define MSR_P5_CESR_ES_PIPELINE_FLUSH 0x010101 /* Pipeline Flushes */
112 #define MSR_P5_CESR_ES_INSTRUCTION 0x010110 /* Instruction executed */
113 #define MSR_P5_CESR_ES_INSTRUCTION_V 0x010111 /* Inst. executed (v-pipe) */
114 #define MSR_P5_CESR_ES_BUS_CYCLE 0x011000 /* Clocks while bus cycle */
115 #define MSR_P5_CESR_ES_FULL_WRITE_BUF 0x011001 /* Clocks while full wrt buf. */
116 #define MSR_P5_CESR_ES_DATA_MEM_READ 0x011010 /* Pipeline waiting for read */
117 #define MSR_P5_CESR_ES_WRITE_EM 0x011011 /* Stall on write E|M state */
118 #define MSR_P5_CESR_ES_LOCKED_CYCLE 0x011100 /* Locked bus cycles */
119 #define MSR_P5_CESR_ES_IO_CYCLE 0x011101 /* I/O Read or Write cycles */
120 #define MSR_P5_CESR_ES_NON_CACHEABLE 0x011110 /* Non-cacheable Mem. read */
121 #define MSR_P5_CESR_ES_AGI 0x011111 /* Stall because of AGI */
122 #define MSR_P5_CESR_ES_FLOP 0x100010 /* Floating Point operations */
123 #define MSR_P5_CESR_ES_BREAK_DR0 0x100011 /* Breakpoint matches on DR0 */
124 #define MSR_P5_CESR_ES_BREAK_DR1 0x100100 /* Breakpoint matches on DR1 */
125 #define MSR_P5_CESR_ES_BREAK_DR2 0x100101 /* Breakpoint matches on DR2 */
126 #define MSR_P5_CESR_ES_BREAK_DR3 0x100110 /* Breakpoint matches on DR3 */
127 #define MSR_P5_CESR_ES_HARDWARE_IT 0x100111 /* Hardware interrupts */
128
129 /*
130 * CR0
131 */
132 #define CR0_PG 0x80000000 /* Enable paging */
133 #define CR0_CD 0x40000000 /* i486: Cache disable */
134 #define CR0_NW 0x20000000 /* i486: No write-through */
135 #define CR0_AM 0x00040000 /* i486: Alignment check mask */
136 #define CR0_WP 0x00010000 /* i486: Write-protect kernel access */
137 #define CR0_NE 0x00000020 /* i486: Handle numeric exceptions */
138 #define CR0_ET 0x00000010 /* Extension type is 80387 */
139 /* (not official) */
140 #define CR0_TS 0x00000008 /* Task switch */
141 #define CR0_EM 0x00000004 /* Emulate coprocessor */
142 #define CR0_MP 0x00000002 /* Monitor coprocessor */
143 #define CR0_PE 0x00000001 /* Enable protected mode */
144
145 /*
146 * CR4
147 */
148 #define CR4_SEE 0x00008000 /* Secure Enclave Enable XXX */
149 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Protect */
150 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execute Protect */
151 #define CR4_OSXSAVE 0x00040000 /* OS supports XSAVE */
152 #define CR4_PCIDE 0x00020000 /* PCID Enable */
153 #define CR4_RDWRFSGS 0x00010000 /* RDWRFSGS Enable */
154 #define CR4_SMXE 0x00004000 /* Enable SMX operation */
155 #define CR4_VMXE 0x00002000 /* Enable VMX operation */
156 #define CR4_OSXMM 0x00000400 /* SSE/SSE2 exception support in OS */
157 #define CR4_OSFXS 0x00000200 /* SSE/SSE2 OS supports FXSave */
158 #define CR4_PCE 0x00000100 /* Performance-Monitor Count Enable */
159 #define CR4_PGE 0x00000080 /* Page Global Enable */
160 #define CR4_MCE 0x00000040 /* Machine Check Exceptions */
161 #define CR4_PAE 0x00000020 /* Physical Address Extensions */
162 #define CR4_PSE 0x00000010 /* Page Size Extensions */
163 #define CR4_DE 0x00000008 /* Debugging Extensions */
164 #define CR4_TSD 0x00000004 /* Time Stamp Disable */
165 #define CR4_PVI 0x00000002 /* Protected-mode Virtual Interrupts */
166 #define CR4_VME 0x00000001 /* Virtual-8086 Mode Extensions */
167
168 /*
169 * XCR0 - XFEATURE_ENABLED_MASK (a.k.a. XFEM) register
170 */
171 #define XCR0_X87 (1ULL << 0) /* x87, FPU/MMX (always set) */
172 #define XCR0_SSE (1ULL << 1) /* SSE supported by XSAVE/XRESTORE */
173 #define XCR0_YMM (1ULL << 2) /* YMM state available */
174 #define XCR0_BNDREGS (1ULL << 3) /* MPX Bounds register state */
175 #define XCR0_BNDCSR (1ULL << 4) /* MPX Bounds configuration/state */
176 #define XCR0_OPMASK (1ULL << 5) /* Opmask register state */
177 #define XCR0_ZMM_HI256 (1ULL << 6) /* ZMM upper 256-bit state */
178 #define XCR0_HI16_ZMM (1ULL << 7) /* ZMM16..ZMM31 512-bit state */
179 #define XFEM_X87 XCR0_X87
180 #define XFEM_SSE XCR0_SSE
181 #define XFEM_YMM XCR0_YMM
182 #define XFEM_BNDREGS XCR0_BNDREGS
183 #define XFEM_BNDCSR XCR0_BNDCSR
184 #define XFEM_OPMASK XCR0_OPMASK
185 #define XFEM_ZMM_HI256 XCR0_ZMM_HI256
186 #define XFEM_HI16_ZMM XCR0_HI16_ZMM
187 #define XFEM_ZMM (XFEM_ZMM_HI256 | XFEM_HI16_ZMM | XFEM_OPMASK)
188 #define XCR0 (0)
189
190 #define PMAP_PCID_PRESERVE (1ULL << 63)
191 #define PMAP_PCID_MASK (0xFFF)
192
193 #define EARLY_GSBASE_MAGIC 0xffffdeadbeefee00
194
195 /*
196 * If thread groups are needed for x86, set this to 1
197 */
198 #define CONFIG_THREAD_GROUPS 0
199
200 /*
201 * MAX_PSETS allows the scheduler to create statically sized
202 * scheduling data structures (such as an array of processor sets, clutch
203 * buckets in Edge scheduler etc.).
204 *
205 * <Edge Multi-cluster Support Needed>
206 */
207 #define MAX_PSETS 64
208 #define MAX_CPUS 64
209
210 #ifndef ASSEMBLER
211
212 #include <sys/cdefs.h>
213 #include <stdint.h>
214
215 __BEGIN_DECLS
216
217 #define set_ts() set_cr0(get_cr0() | CR0_TS)
218
219 static inline uint16_t
220 get_es(void)
221 {
222 uint16_t es;
223 __asm__ volatile ("mov %%es, %0" : "=r" (es));
224 return es;
225 }
226
227 static inline void
228 set_es(uint16_t es)
229 {
230 __asm__ volatile ("mov %0, %%es" : : "r" (es));
231 }
232
233 static inline uint16_t
234 get_ds(void)
235 {
236 uint16_t ds;
237 __asm__ volatile ("mov %%ds, %0" : "=r" (ds));
238 return ds;
239 }
240
241 static inline void
242 set_ds(uint16_t ds)
243 {
244 __asm__ volatile ("mov %0, %%ds" : : "r" (ds));
245 }
246
247 static inline uint16_t
248 get_fs(void)
249 {
250 uint16_t fs;
251 __asm__ volatile ("mov %%fs, %0" : "=r" (fs));
252 return fs;
253 }
254
255 static inline void
256 set_fs(uint16_t fs)
257 {
258 __asm__ volatile ("mov %0, %%fs" : : "r" (fs));
259 }
260
261 static inline uint16_t
262 get_gs(void)
263 {
264 uint16_t gs;
265 __asm__ volatile ("mov %%gs, %0" : "=r" (gs));
266 return gs;
267 }
268
269 static inline void
270 set_gs(uint16_t gs)
271 {
272 __asm__ volatile ("mov %0, %%gs" : : "r" (gs));
273 }
274
275 static inline uint16_t
276 get_ss(void)
277 {
278 uint16_t ss;
279 __asm__ volatile ("mov %%ss, %0" : "=r" (ss));
280 return ss;
281 }
282
283 static inline void
284 set_ss(uint16_t ss)
285 {
286 __asm__ volatile ("mov %0, %%ss" : : "r" (ss));
287 }
288
289 static inline uintptr_t
290 get_cr0(void)
291 {
292 uintptr_t cr0;
293 __asm__ volatile ("mov %%cr0, %0" : "=r" (cr0));
294 return cr0;
295 }
296
297 static inline void
298 set_cr0(uintptr_t value)
299 {
300 __asm__ volatile ("mov %0, %%cr0" : : "r" (value));
301 }
302
303 static inline uintptr_t
304 get_cr2(void)
305 {
306 uintptr_t cr2;
307 __asm__ volatile ("mov %%cr2, %0" : "=r" (cr2));
308 return cr2;
309 }
310
311 static inline uintptr_t
312 get_cr3_raw(void)
313 {
314 uintptr_t cr3;
315 __asm__ volatile ("mov %%cr3, %0" : "=r" (cr3));
316 return cr3;
317 }
318
319 static inline void
320 set_cr3_raw(uintptr_t value)
321 {
322 __asm__ volatile ("mov %0, %%cr3" : : "r" (value));
323 }
324
325 static inline uintptr_t
326 get_cr3_base(void)
327 {
328 uintptr_t cr3;
329 __asm__ volatile ("mov %%cr3, %0" : "=r" (cr3));
330 return cr3 & ~(0xFFFULL);
331 }
332
333 static inline void
334 set_cr3_composed(uintptr_t base, uint16_t pcid, uint64_t preserve)
335 {
336 __asm__ volatile ("mov %0, %%cr3" : : "r" (base | pcid | ( (preserve) << 63) ));
337 }
338
339 static inline uintptr_t
340 get_cr4(void)
341 {
342 uintptr_t cr4;
343 __asm__ volatile ("mov %%cr4, %0" : "=r" (cr4));
344 return cr4;
345 }
346
347 static inline void
348 set_cr4(uintptr_t value)
349 {
350 __asm__ volatile ("mov %0, %%cr4" : : "r" (value));
351 }
352
353 static inline uintptr_t
354 x86_get_flags(void)
355 {
356 uintptr_t erflags;
357 __asm__ volatile ("pushf; pop %0" : "=r" (erflags));
358 return erflags;
359 }
360
361 static inline void
362 clear_ts(void)
363 {
364 __asm__ volatile ("clts");
365 }
366
367 static inline unsigned short
368 get_tr(void)
369 {
370 unsigned short seg;
371 __asm__ volatile ("str %0" : "=rm" (seg));
372 return seg;
373 }
374
375 static inline void
376 set_tr(unsigned int seg)
377 {
378 __asm__ volatile ("ltr %0" : : "rm" ((unsigned short)(seg)));
379 }
380
381 static inline unsigned short
382 sldt(void)
383 {
384 unsigned short seg;
385 __asm__ volatile ("sldt %0" : "=rm" (seg));
386 return seg;
387 }
388
389 static inline void
390 lldt(unsigned int seg)
391 {
392 __asm__ volatile ("lldt %0" : : "rm" ((unsigned short)(seg)));
393 }
394
395 static inline void
396 lgdt(uintptr_t *desc)
397 {
398 __asm__ volatile ("lgdt %0" : : "m" (*desc));
399 }
400
401 static inline void
402 lidt(uintptr_t *desc)
403 {
404 __asm__ volatile ("lidt %0" : : "m" (*desc));
405 }
406
407 static inline void
408 swapgs(void)
409 {
410 __asm__ volatile ("swapgs");
411 }
412
413 static inline void
414 hlt(void)
415 {
416 __asm__ volatile ("hlt");
417 }
418
419 #ifdef MACH_KERNEL_PRIVATE
420
421 extern int rdmsr64_carefully(uint32_t msr, uint64_t *val);
422 extern int wrmsr64_carefully(uint32_t msr, uint64_t val);
423 #endif /* MACH_KERNEL_PRIVATE */
424
425 static inline void
426 wbinvd(void)
427 {
428 __asm__ volatile ("wbinvd");
429 }
430
431 static inline void
432 invlpg(uintptr_t addr)
433 {
434 __asm__ volatile ("invlpg (%0)" :: "r" (addr) : "memory");
435 }
436
437 static inline void
438 clac(void)
439 {
440 __asm__ volatile ("clac");
441 }
442
443 static inline void
444 stac(void)
445 {
446 __asm__ volatile ("stac");
447 }
448
449 /*
450 * Access to machine-specific registers (available on 586 and better only)
451 * Note: the rd* operations modify the parameters directly (without using
452 * pointer indirection), this allows gcc to optimize better
453 */
454
455 #define rdmsr(msr, lo, hi) \
456 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
457
458 #define wrmsr(msr, lo, hi) \
459 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
460
461 #define rdtsc(lo, hi) \
462 __asm__ volatile("lfence; rdtsc" : "=a" (lo), "=d" (hi))
463
464 #define rdtsc_nofence(lo, hi) \
465 __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi))
466
467 #define write_tsc(lo, hi) wrmsr(0x10, lo, hi)
468
469 #define rdpmc(counter, lo, hi) \
470 __asm__ volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (counter))
471
472 #ifdef XNU_KERNEL_PRIVATE
473
474 #define X86_MAX_LBRS 32
475 struct x86_lbr_record {
476 /*
477 * Note that some CPUs convey extra info in the upper bits of the from/to fields,
478 * whereas others convey that information in the LBR_INFO companion MSRs.
479 * The proper info will be extracted based on the CPU family detected at runtime
480 * when LBR thread state is requested.
481 */
482 uint64_t from_rip;
483 uint64_t to_rip;
484 uint64_t info;
485 };
486
487 typedef struct x86_lbrs {
488 uint64_t lbr_tos;
489 struct x86_lbr_record lbrs[X86_MAX_LBRS];
490 } x86_lbrs_t;
491
492
493 extern void do_mfence(void);
494 #define mfence() do_mfence()
495 #endif
496
497 #ifdef __LP64__
498 static inline uint64_t
499 rdpmc64(uint32_t pmc)
500 {
501 uint32_t lo = 0, hi = 0;
502 rdpmc(pmc, lo, hi);
503 return (((uint64_t)hi) << 32) | ((uint64_t)lo);
504 }
505
506 static inline uint64_t
507 rdmsr64(uint32_t msr)
508 {
509 uint32_t lo = 0, hi = 0;
510 rdmsr(msr, lo, hi);
511 return (((uint64_t)hi) << 32) | ((uint64_t)lo);
512 }
513
514 static inline void
515 wrmsr64(uint32_t msr, uint64_t val)
516 {
517 wrmsr(msr, (val & 0xFFFFFFFFUL), ((val >> 32) & 0xFFFFFFFFUL));
518 }
519
520 static inline uint64_t
521 rdtsc64(void)
522 {
523 uint64_t lo, hi;
524 rdtsc(lo, hi);
525 return ((hi) << 32) | (lo);
526 }
527
528 static inline uint64_t
529 rdtsc64_nofence(void)
530 {
531 uint64_t lo, hi;
532 rdtsc_nofence(lo, hi);
533 return ((hi) << 32) | (lo);
534 }
535
536 static inline uint64_t
537 rdtscp64(uint32_t *aux)
538 {
539 uint64_t lo, hi;
540 __asm__ volatile ("rdtscp; mov %%ecx, %1"
541 : "=a" (lo), "=d" (hi), "=m" (*aux)
542 :
543 : "ecx");
544 return ((hi) << 32) | (lo);
545 }
546 #endif /* __LP64__ */
547
548 /*
549 * rdmsr_carefully() returns 0 when the MSR has been read successfully,
550 * or non-zero (1) if the MSR does not exist.
551 * The implementation is in locore.s.
552 */
553 extern int rdmsr_carefully(uint32_t msr, uint32_t *lo, uint32_t *hi);
554 __END_DECLS
555
556 #endif /* ASSEMBLER */
557
558 #define MSR_IA32_P5_MC_ADDR 0
559 #define MSR_IA32_P5_MC_TYPE 1
560 #define MSR_IA32_PLATFORM_ID 0x17
561 #define MSR_IA32_EBL_CR_POWERON 0x2a
562
563 #define MSR_IA32_APIC_BASE 0x1b
564 #define MSR_IA32_APIC_BASE_BSP (1<<8)
565 #define MSR_IA32_APIC_BASE_EXTENDED (1<<10)
566 #define MSR_IA32_APIC_BASE_ENABLE (1<<11)
567 #define MSR_IA32_APIC_BASE_BASE (0xfffff<<12)
568
569 #define MSR_CORE_THREAD_COUNT 0x35
570
571 #define MSR_IA32_FEATURE_CONTROL 0x3a
572 #define MSR_IA32_FEATCTL_LOCK (1<<0)
573 #define MSR_IA32_FEATCTL_VMXON_SMX (1<<1)
574 #define MSR_IA32_FEATCTL_VMXON (1<<2)
575 #define MSR_IA32_FEATCTL_CSTATE_SMI (1<<16)
576
577 #define MSR_IA32_UPDT_TRIG 0x79
578 #define MSR_IA32_BIOS_SIGN_ID 0x8b
579 #define MSR_IA32_UCODE_WRITE MSR_IA32_UPDT_TRIG
580 #define MSR_IA32_UCODE_REV MSR_IA32_BIOS_SIGN_ID
581
582 #define MSR_IA32_PERFCTR0 0xc1
583 #define MSR_IA32_PERFCTR1 0xc2
584 #define MSR_IA32_PERFCTR3 0xc3
585 #define MSR_IA32_PERFCTR4 0xc4
586
587 #define MSR_PLATFORM_INFO 0xce
588
589 #define MSR_IA32_MPERF 0xE7
590 #define MSR_IA32_APERF 0xE8
591
592 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
593 #define MSR_IA32_ARCH_CAPABILITIES_RDCL_NO (1ULL << 0)
594 #define MSR_IA32_ARCH_CAPABILITIES_IBRS_ALL (1ULL << 1)
595 #define MSR_IA32_ARCH_CAPABILITIES_RSBA (1ULL << 2)
596 #define MSR_IA32_ARCH_CAPABILITIES_L1DF_NO (1ULL << 3)
597 #define MSR_IA32_ARCH_CAPABILITIES_SSB_NO (1ULL << 4)
598 #define MSR_IA32_ARCH_CAPABILITIES_MDS_NO (1ULL << 5)
599 #define MSR_IA32_ARCH_CAPABILITIES_IFU_NO (1ULL << 6) /* This CPU is not susceptible to the instruction-fetch erratum */
600 #define MSR_IA32_ARCH_CAPABILITIES_TSX_CTRL (1ULL << 7) /* This CPU supports the TSX_CTRL MSR */
601 #define MSR_IA32_ARCH_CAPABILITIES_TAA_NO (1ULL << 8) /* This CPU is not susceptible to TAA */
602
603 #define MSR_IA32_TSX_FORCE_ABORT 0x10f
604 #define MSR_IA32_TSXFA_RTM_FORCE_ABORT (1ULL << 0) /* Bit 0 */
605
606 #define MSR_IA32_BBL_CR_CTL 0x119
607
608 #define MSR_IA32_TSX_CTRL 0x122
609 #define MSR_IA32_TSXCTRL_RTM_DISABLE (1ULL << 0) /* Bit 0 */
610 #define MSR_IA32_TSXCTRL_TSX_CPU_CLEAR (1ULL << 1) /* Bit 1 */
611
612 #define MSR_IA32_MCU_OPT_CTRL 0x123
613 #define MSR_IA32_MCUOPTCTRL_RNGDS_MITG_DIS (1ULL << 0) /* Bit 0 */
614
615 #define MSR_IA32_SYSENTER_CS 0x174
616 #define MSR_IA32_SYSENTER_ESP 0x175
617 #define MSR_IA32_SYSENTER_EIP 0x176
618
619 #define MSR_IA32_MCG_CAP 0x179
620 #define MSR_IA32_MCG_STATUS 0x17a
621 #define MSR_IA32_MCG_CTL 0x17b
622
623 #define MSR_IA32_EVNTSEL0 0x186
624 #define MSR_IA32_EVNTSEL1 0x187
625 #define MSR_IA32_EVNTSEL2 0x188
626 #define MSR_IA32_EVNTSEL3 0x189
627
628 #define MSR_FLEX_RATIO 0x194
629 #define MSR_IA32_PERF_STS 0x198
630 #define MSR_IA32_PERF_CTL 0x199
631 #define MSR_IA32_CLOCK_MODULATION 0x19a
632
633 #define MSR_IA32_MISC_ENABLE 0x1a0
634 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1
635 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2
636
637 #define MSR_IA32_LBR_SELECT 0x1c8
638 #define LBR_SELECT_CPL_EQ_0 (1ULL) /* R/W When set, do not capture branches ending in ring 0 */
639 #define LBR_SELECT_CPL_NEQ_0 (1ULL << 1) /* R/W When set, do not capture branches ending in ring >0 */
640 #define LBR_SELECT_JCC (1ULL << 2) /* R/W When set, do not capture conditional branches */
641 #define LBR_SELECT_NEAR_REL_CALL (1ULL << 3) /* R/W When set, do not capture near relative calls */
642 #define LBR_SELECT_NEAR_IND_CALL (1ULL << 4) /* R/W When set, do not capture near indirect calls */
643 #define LBR_SELECT_NEAR_RET (1ULL << 5) /* R/W When set, do not capture near returns */
644 #define LBR_SELECT_NEAR_IND_JMP (1ULL << 6) /* R/W When set, do not capture near indirect jumps except near indirect calls and near returns */
645 #define LBR_SELECT_NEAR_REL_JMP (1ULL << 7) /* R/W When set, do not capture near relative jumps except near relative calls. */
646 #define LBR_SELECT_FAR_BRANCH (1ULL << 8) /* R/W When set, do not capture far branches */
647 #define LBR_SELECT_HSW_EN_CALLSTACK1 (1ULL << 9) /* Enable LBR stack to use LIFO filtering to capture Call stack profile */
648
649 #define MSR_IA32_LASTBRANCH_TOS 0x1c9
650
651 /* LBR INFO MSR fields (SKL and later) */
652 /* Same fields can be used for HSW in the FROM_x LBR MSRs */
653 #define MSR_IA32_LBRINFO_TSX_ABORT (1ULL << 61)
654 #define MSR_IA32_LBRINFO_IN_TSX (1ULL << 62)
655 #define MSR_IA32_LBRINFO_MISPREDICT (1ULL << 63)
656 #define MSR_IA32_LBRINFO_CYCLECNT_MASK (0xFFFFULL)
657
658 #define MSR_IA32_DEBUGCTLMSR 0x1d9
659 #define DEBUGCTL_LBR_ENA (1U)
660
661 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
662 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
663 #define MSR_IA32_LASTINTFROMIP 0x1dd
664 #define MSR_IA32_LASTINTTOIP 0x1de
665
666 #define MSR_IA32_CR_PAT 0x277
667
668 #define MSR_IA32_MTRRCAP 0xfe
669 #define MSR_IA32_MTRR_DEF_TYPE 0x2ff
670 #define MSR_IA32_MTRR_PHYSBASE(n) (0x200 + 2*(n))
671 #define MSR_IA32_MTRR_PHYSMASK(n) (0x200 + 2*(n) + 1)
672 #define MSR_IA32_MTRR_FIX64K_00000 0x250
673 #define MSR_IA32_MTRR_FIX16K_80000 0x258
674 #define MSR_IA32_MTRR_FIX16K_A0000 0x259
675 #define MSR_IA32_MTRR_FIX4K_C0000 0x268
676 #define MSR_IA32_MTRR_FIX4K_C8000 0x269
677 #define MSR_IA32_MTRR_FIX4K_D0000 0x26a
678 #define MSR_IA32_MTRR_FIX4K_D8000 0x26b
679 #define MSR_IA32_MTRR_FIX4K_E0000 0x26c
680 #define MSR_IA32_MTRR_FIX4K_E8000 0x26d
681 #define MSR_IA32_MTRR_FIX4K_F0000 0x26e
682 #define MSR_IA32_MTRR_FIX4K_F8000 0x26f
683
684 #define MSR_IA32_PERF_FIXED_CTR0 0x309
685
686 #define MSR_IA32_PERF_CAPABILITIES 0x345
687 #define PERFCAP_LBR_FMT_MASK (0x3f)
688 #define PERFCAP_LBR_TYPE(msrval) ((msrval) & PERFCAP_LBR_FMT_MASK)
689 #define PERFCAP_LBR_TYPE_MISPRED 3 /* NHM */
690 #define PERFCAP_LBR_TYPE_TSXINFO 4 /* HSW/BDW */
691 #define PERFCAP_LBR_TYPE_EIP_WITH_LBRINFO 5 /* SKL+ */
692 /* Types 6 & 7 are for Goldmont and Goldmont Plus, respectively */
693
694 #define LBR_TYPE_MISPRED_FROMRIP(from_rip) (((from_rip) & 0xFFFFFFFFFFFFULL) | (((from_rip) & (1ULL << 47)) ? 0xFFFF000000000000ULL : 0))
695 #define LBR_TYPE_MISPRED_MISPREDICT(from_rip) (((from_rip) & MSR_IA32_LBRINFO_MISPREDICT) ? 1 : 0)
696
697 #define LBR_TYPE_TSXINFO_FROMRIP(from_rip) (LBR_TYPE_MISPRED_FROMRIP(from_rip))
698 #define LBR_TYPE_TSXINFO_MISPREDICT(from_rip) (((from_rip) & MSR_IA32_LBRINFO_MISPREDICT) ? 1 : 0)
699 #define LBR_TYPE_TSXINFO_TSX_ABORT(from_rip) (((from_rip) & MSR_IA32_LBRINFO_TSX_ABORT) ? 1 : 0)
700 #define LBR_TYPE_TSXINFO_IN_TSX(from_rip) (((from_rip) & MSR_IA32_LBRINFO_IN_TSX) ? 1 : 0)
701
702 #define LBR_TYPE_EIP_WITH_LBRINFO_MISPREDICT(lbrinfo) LBR_TYPE_TSXINFO_MISPREDICT(lbrinfo)
703 #define LBR_TYPE_EIP_WITH_LBRINFO_TSX_ABORT(lbrinfo) LBR_TYPE_TSXINFO_TSX_ABORT(lbrinfo)
704 #define LBR_TYPE_EIP_WITH_LBRINFO_IN_TSX(lbrinfo) LBR_TYPE_TSXINFO_IN_TSX(lbrinfo)
705 #define LBR_TYPE_EIP_WITH_LBRINFO_CYC_COUNT(lbrinfo) ((lbrinfo) & 0xFFFFULL)
706
707
708 #define MSR_IA32_PERF_FIXED_CTR_CTRL 0x38D
709 #define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
710 #define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
711 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
712
713 #define MSR_IA32_PKG_C3_RESIDENCY 0x3F8
714 #define MSR_IA32_PKG_C6_RESIDENCY 0x3F9
715 #define MSR_IA32_PKG_C7_RESIDENCY 0x3FA
716
717 #define MSR_IA32_CORE_C3_RESIDENCY 0x3FC
718 #define MSR_IA32_CORE_C6_RESIDENCY 0x3FD
719 #define MSR_IA32_CORE_C7_RESIDENCY 0x3FE
720
721 #define MSR_IA32_MC0_CTL 0x400
722 #define MSR_IA32_MC0_STATUS 0x401
723 #define MSR_IA32_MC0_ADDR 0x402
724 #define MSR_IA32_MC0_MISC 0x403
725
726 #define MSR_IA32_VMX_BASE 0x480
727 #define MSR_IA32_VMX_BASIC MSR_IA32_VMX_BASE
728 #define MSR_IA32_VMX_PINBASED_CTLS MSR_IA32_VMX_BASE+1
729 #define MSR_IA32_VMX_PROCBASED_CTLS MSR_IA32_VMX_BASE+2
730 #define MSR_IA32_VMX_EXIT_CTLS MSR_IA32_VMX_BASE+3
731 #define MSR_IA32_VMX_ENTRY_CTLS MSR_IA32_VMX_BASE+4
732 #define MSR_IA32_VMX_MISC MSR_IA32_VMX_BASE+5
733 #define MSR_IA32_VMX_CR0_FIXED0 MSR_IA32_VMX_BASE+6
734 #define MSR_IA32_VMX_CR0_FIXED1 MSR_IA32_VMX_BASE+7
735 #define MSR_IA32_VMX_CR4_FIXED0 MSR_IA32_VMX_BASE+8
736 #define MSR_IA32_VMX_CR4_FIXED1 MSR_IA32_VMX_BASE+9
737 #define MSR_IA32_VMX_VMCS_ENUM MSR_IA32_VMX_BASE+10
738 #define MSR_IA32_VMX_PROCBASED_CTLS2 MSR_IA32_VMX_BASE+11
739 #define MSR_IA32_VMX_EPT_VPID_CAP MSR_IA32_VMX_BASE+12
740 #define MSR_IA32_VMX_EPT_VPID_CAP_AD_SHIFT 21
741 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS MSR_IA32_VMX_BASE+13
742 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS MSR_IA32_VMX_BASE+14
743 #define MSR_IA32_VMX_TRUE_VMEXIT_CTLS MSR_IA32_VMX_BASE+15
744 #define MSR_IA32_VMX_TRUE_VMENTRY_CTLS MSR_IA32_VMX_BASE+16
745 #define MSR_IA32_VMX_VMFUNC MSR_IA32_VMX_BASE+17
746
747 #define MSR_IA32_DS_AREA 0x600
748
749 #define MSR_IA32_PKG_POWER_SKU_UNIT 0x606
750 #define MSR_IA32_PKG_C2_RESIDENCY 0x60D
751 #define MSR_IA32_PKG_ENERGY_STATUS 0x611
752 #define MSR_IA32_DDR_ENERGY_STATUS 0x619
753 #define MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER 0x61D
754 #define MSR_IA32_RING_PERF_STATUS 0x621
755
756 #define MSR_IA32_PKG_C8_RESIDENCY 0x630
757 #define MSR_IA32_PKG_C9_RESIDENCY 0x631
758 #define MSR_IA32_PKG_C10_RESIDENCY 0x632
759
760 #define MSR_IA32_PP0_ENERGY_STATUS 0x639
761 #define MSR_IA32_PP1_ENERGY_STATUS 0x641
762 #define MSR_IA32_IA_PERF_LIMIT_REASONS_SKL 0x64F
763
764 #define MSR_IA32_IA_PERF_LIMIT_REASONS 0x690
765 #define MSR_IA32_GT_PERF_LIMIT_REASONS 0x6B0
766
767 #define MSR_IA32_TSC_DEADLINE 0x6e0
768
769 #define MSR_IA32_EFER 0xC0000080
770 #define MSR_IA32_EFER_SCE 0x00000001
771 #define MSR_IA32_EFER_LME 0x00000100
772 #define MSR_IA32_EFER_LMA 0x00000400
773 #define MSR_IA32_EFER_NXE 0x00000800
774
775 #define MSR_IA32_STAR 0xC0000081
776 #define MSR_IA32_LSTAR 0xC0000082
777 #define MSR_IA32_CSTAR 0xC0000083
778 #define MSR_IA32_FMASK 0xC0000084
779
780 #define MSR_IA32_FS_BASE 0xC0000100
781 #define MSR_IA32_GS_BASE 0xC0000101
782 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
783 #define MSR_IA32_TSC_AUX 0xC0000103
784
785 #define HV_VMX_EPTP_MEMORY_TYPE_UC 0x0
786 #define HV_VMX_EPTP_MEMORY_TYPE_WB 0x6
787 #define HV_VMX_EPTP_WALK_LENGTH(wl) (0ULL | ((((wl) - 1) & 0x7) << 3))
788 #define HV_VMX_EPTP_ENABLE_AD_FLAGS (1ULL << 6)
789
790 #endif /* _I386_PROC_REG_H_ */
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