osfmk/chud/ppc/chud_cpu_asm.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22
  23 #define ASSEMBLER
  24 #include <chud/ppc/chud_spr.h>
  25 #include <ppc/asm.h>
  26 #include <mach/kern_return.h>
  27
  28 /*
  29  * kern_return_t mfspr64(uint64_t *val, int spr);
  30  *
  31  * r3: address to store value in
  32  * r4: spr to read from
  33  *
  34  */
  35
  36 ;           Force a line boundry here
  37             .align  5
  38             .globl  EXT(mfspr64)
  39
  40 EXT(mfspr64):
  41             ;; generic PPC 64-bit wide SPRs
  42             cmpwi       r4,chud_ppc_srr0
  43             beq         mfspr64_srr0
  44             cmpwi       r4,chud_ppc_srr1
  45             beq         mfspr64_srr1
  46             cmpwi       r4,chud_ppc_dar
  47             beq         mfspr64_dar
  48             cmpwi       r4,chud_ppc_sdr1
  49             beq         mfspr64_sdr1
  50             cmpwi       r4,chud_ppc_sprg0
  51             beq         mfspr64_sprg0
  52             cmpwi       r4,chud_ppc_sprg1
  53             beq         mfspr64_sprg1
  54             cmpwi       r4,chud_ppc_sprg2
  55             beq         mfspr64_sprg2
  56             cmpwi       r4,chud_ppc_sprg3
  57             beq         mfspr64_sprg3
  58             cmpwi       r4,chud_ppc64_asr
  59             beq         mfspr64_asr
  60             cmpwi       r4,chud_ppc_dabr
  61             beq         mfspr64_dabr
  62
  63             ;; GPUL specific 64-bit wide SPRs
  64             cmpwi       r4,chud_970_hid0
  65             beq         mfspr64_hid0
  66             cmpwi       r4,chud_970_hid1
  67             beq         mfspr64_hid1
  68             cmpwi       r4,chud_970_hid4
  69             beq         mfspr64_hid4
  70             cmpwi       r4,chud_970_hid5
  71             beq         mfspr64_hid5
  72             cmpwi       r4,chud_970_mmcr0
  73             beq         mfspr64_mmcr0
  74             cmpwi       r4,chud_970_mmcr1
  75             beq         mfspr64_mmcr1
  76             cmpwi       r4,chud_970_mmcra
  77             beq         mfspr64_mmcra
  78             cmpwi       r4,chud_970_siar
  79             beq         mfspr64_siar
  80             cmpwi       r4,chud_970_sdar
  81             beq         mfspr64_sdar
  82             cmpwi       r4,chud_970_imc
  83             beq         mfspr64_imc
  84             cmpwi       r4,chud_970_rmor
  85             beq         mfspr64_rmor
  86             cmpwi       r4,chud_970_hrmor
  87             beq         mfspr64_hrmor
  88             cmpwi       r4,chud_970_hior
  89             beq         mfspr64_hior
  90             cmpwi       r4,chud_970_lpidr
  91             beq         mfspr64_lpidr
  92             cmpwi       r4,chud_970_lpcr
  93             beq         mfspr64_lpcr
  94             cmpwi       r4,chud_970_dabrx
  95             beq         mfspr64_dabrx
  96             cmpwi       r4,chud_970_hsprg0
  97             beq         mfspr64_hsprg0
  98             cmpwi       r4,chud_970_hsprg1
  99             beq         mfspr64_hsprg1
 100             cmpwi       r4,chud_970_hsrr0
 101             beq         mfspr64_hsrr0
 102             cmpwi       r4,chud_970_hsrr1
 103             beq         mfspr64_hsrr1
 104             cmpwi       r4,chud_970_hdec
 105             beq         mfspr64_hdec
 106             cmpwi       r4,chud_970_trig0
 107             beq         mfspr64_trig0
 108             cmpwi       r4,chud_970_trig1
 109             beq         mfspr64_trig1
 110             cmpwi       r4,chud_970_trig2
 111             beq         mfspr64_trig2
 112             cmpwi       r4,chud_ppc64_accr
 113             beq         mfspr64_accr
 114             cmpwi       r4,chud_970_scomc
 115             beq         mfspr64_scomc
 116             cmpwi       r4,chud_970_scomd
 117             beq         mfspr64_scomd
 118
 119             b           mfspr64_failure
 120
 121 mfspr64_srr0:
 122             mfspr       r5,chud_ppc_srr0
 123             std         r5,0(r3)
 124             b           mfspr64_success
 125 mfspr64_srr1:
 126             mfspr       r5,chud_ppc_srr1
 127             std         r5,0(r3)
 128             b           mfspr64_success
 129 mfspr64_dar:
 130             mfspr       r5,chud_ppc_dar
 131             std         r5,0(r3)
 132             b           mfspr64_success
 133 mfspr64_sdr1:
 134             mfspr       r5,chud_ppc_sdr1
 135             std         r5,0(r3)
 136             b           mfspr64_success
 137 mfspr64_sprg0:
 138             mfspr       r5,chud_ppc_sprg0
 139             std         r5,0(r3)
 140             b           mfspr64_success
 141 mfspr64_sprg1:
 142             mfspr       r5,chud_ppc_sprg1
 143             std         r5,0(r3)
 144             b           mfspr64_success
 145 mfspr64_sprg2:
 146             mfspr       r5,chud_ppc_sprg2
 147             std         r5,0(r3)
 148             b           mfspr64_success
 149 mfspr64_sprg3:
 150             mfspr       r5,chud_ppc_sprg3
 151             std         r5,0(r3)
 152             b           mfspr64_success
 153 mfspr64_asr:
 154             mfspr       r5,chud_ppc64_asr
 155             std         r5,0(r3)
 156             b           mfspr64_success
 157 mfspr64_dabr:
 158             mfspr       r5,chud_ppc_dabr
 159             std         r5,0(r3)
 160             b           mfspr64_success
 161 mfspr64_hid0:
 162             mfspr       r5,chud_970_hid0
 163             std         r5,0(r3)
 164             b           mfspr64_success
 165 mfspr64_hid1:
 166             mfspr       r5,chud_970_hid1
 167             std         r5,0(r3)
 168             b           mfspr64_success
 169 mfspr64_hid4:
 170             mfspr       r5,chud_970_hid4
 171             std         r5,0(r3)
 172             b           mfspr64_success
 173 mfspr64_hid5:
 174             mfspr       r5,chud_970_hid5
 175             std         r5,0(r3)
 176             b           mfspr64_success
 177 mfspr64_mmcr0:
 178             mfspr       r5,chud_970_mmcr0
 179             std         r5,0(r3)
 180             b           mfspr64_success
 181 mfspr64_mmcr1:
 182             mfspr       r5,chud_970_mmcr1
 183             std         r5,0(r3)
 184             b           mfspr64_success
 185 mfspr64_mmcra:
 186             mfspr       r5,chud_970_mmcra
 187             std         r5,0(r3)
 188             b           mfspr64_success
 189 mfspr64_siar:
 190             mfspr       r5,chud_970_siar
 191             std         r5,0(r3)
 192             b           mfspr64_success
 193 mfspr64_sdar:
 194             mfspr       r5,chud_970_sdar
 195             std         r5,0(r3)
 196             b           mfspr64_success
 197 mfspr64_imc:
 198             mfspr       r5,chud_970_imc
 199             std         r5,0(r3)
 200             b           mfspr64_success
 201 mfspr64_rmor:
 202             mfspr       r5,chud_970_rmor
 203             std         r5,0(r3)
 204             b           mfspr64_success
 205 mfspr64_hrmor:
 206             mfspr       r5,chud_970_hrmor
 207             std         r5,0(r3)
 208             b           mfspr64_success
 209 mfspr64_hior:
 210             mfspr       r5,chud_970_hior
 211             std         r5,0(r3)
 212             b           mfspr64_success
 213 mfspr64_lpidr:
 214             mfspr       r5,chud_970_lpidr
 215             std         r5,0(r3)
 216             b           mfspr64_success
 217 mfspr64_lpcr:
 218             mfspr       r5,chud_970_lpcr
 219             std         r5,0(r3)
 220             b           mfspr64_success
 221 mfspr64_dabrx:
 222             mfspr       r5,chud_970_dabrx
 223             std         r5,0(r3)
 224             b           mfspr64_success
 225 mfspr64_hsprg0:
 226             mfspr       r5,chud_970_hsprg0
 227             std         r5,0(r3)
 228             b           mfspr64_success
 229 mfspr64_hsprg1:
 230             mfspr       r5,chud_970_hsprg1
 231             std         r5,0(r3)
 232             b           mfspr64_success
 233 mfspr64_hsrr0:
 234             mfspr       r5,chud_970_hsrr0
 235             std         r5,0(r3)
 236             b           mfspr64_success
 237 mfspr64_hsrr1:
 238             mfspr       r5,chud_970_hsrr1
 239             std         r5,0(r3)
 240             b           mfspr64_success
 241 mfspr64_hdec:
 242             mfspr       r5,chud_970_hdec
 243             std         r5,0(r3)
 244             b           mfspr64_success
 245 mfspr64_trig0:
 246             mfspr       r5,chud_970_trig0
 247             std         r5,0(r3)
 248             b           mfspr64_success
 249 mfspr64_trig1:
 250             mfspr       r5,chud_970_trig1
 251             std         r5,0(r3)
 252             b           mfspr64_success
 253 mfspr64_trig2:
 254             mfspr       r5,chud_970_trig2
 255             std         r5,0(r3)
 256             b           mfspr64_success
 257 mfspr64_accr:
 258             mfspr       r5,chud_ppc64_accr
 259             std         r5,0(r3)
 260             b           mfspr64_success
 261 mfspr64_scomc:
 262             mfspr       r5,chud_970_scomc
 263             std         r5,0(r3)
 264             b           mfspr64_success
 265 mfspr64_scomd:
 266             mfspr       r5,chud_970_scomd
 267             std         r5,0(r3)
 268             b           mfspr64_success
 269
 270 mfspr64_failure:
 271             li          r3,KERN_FAILURE
 272             blr
 273
 274 mfspr64_success:
 275             li          r3,KERN_SUCCESS
 276             blr
 277
 278
 279 /*
 280  * kern_return_t mtspr64(int spr, uint64_t *val);
 281  *
 282  * r3: spr to write to
 283  * r4: address to get value from
 284  *
 285  */
 286
 287 ;           Force a line boundry here
 288             .align  5
 289             .globl  EXT(mtspr64)
 290
 291 EXT(mtspr64):
 292             ;; generic PPC 64-bit wide SPRs
 293             cmpwi       r3,chud_ppc_srr0
 294             beq         mtspr64_srr0
 295             cmpwi       r3,chud_ppc_srr1
 296             beq         mtspr64_srr1
 297             cmpwi       r3,chud_ppc_dar
 298             beq         mtspr64_dar
 299             cmpwi       r3,chud_ppc_sdr1
 300             beq         mtspr64_sdr1
 301             cmpwi       r3,chud_ppc_sprg0
 302             beq         mtspr64_sprg0
 303             cmpwi       r3,chud_ppc_sprg1
 304             beq         mtspr64_sprg1
 305             cmpwi       r3,chud_ppc_sprg2
 306             beq         mtspr64_sprg2
 307             cmpwi       r3,chud_ppc_sprg3
 308             beq         mtspr64_sprg3
 309             cmpwi       r3,chud_ppc64_asr
 310             beq         mtspr64_asr
 311             cmpwi       r3,chud_ppc_dabr
 312             beq         mtspr64_dabr
 313
 314             ;; GPUL specific 64-bit wide SPRs
 315             cmpwi       r3,chud_970_hid0
 316             beq         mtspr64_hid0
 317             cmpwi       r3,chud_970_hid1
 318             beq         mtspr64_hid1
 319             cmpwi       r3,chud_970_hid4
 320             beq         mtspr64_hid4
 321             cmpwi       r3,chud_970_hid5
 322             beq         mtspr64_hid5
 323             cmpwi       r3,chud_970_mmcr0
 324             beq         mtspr64_mmcr0
 325             cmpwi       r3,chud_970_mmcr1
 326             beq         mtspr64_mmcr1
 327             cmpwi       r3,chud_970_mmcra
 328             beq         mtspr64_mmcra
 329             cmpwi       r3,chud_970_siar
 330             beq         mtspr64_siar
 331             cmpwi       r3,chud_970_sdar
 332             beq         mtspr64_sdar
 333             cmpwi       r3,chud_970_imc
 334             beq         mtspr64_imc
 335             cmpwi       r3,chud_970_rmor
 336             beq         mtspr64_rmor
 337             cmpwi       r3,chud_970_hrmor
 338             beq         mtspr64_hrmor
 339             cmpwi       r3,chud_970_hior
 340             beq         mtspr64_hior
 341             cmpwi       r3,chud_970_lpidr
 342             beq         mtspr64_lpidr
 343             cmpwi       r3,chud_970_lpcr
 344             beq         mtspr64_lpcr
 345             cmpwi       r3,chud_970_dabrx
 346             beq         mtspr64_dabrx
 347             cmpwi       r3,chud_970_hsprg0
 348             beq         mtspr64_hsprg0
 349             cmpwi       r3,chud_970_hsprg1
 350             beq         mtspr64_hsprg1
 351             cmpwi       r3,chud_970_hsrr0
 352             beq         mtspr64_hsrr0
 353             cmpwi       r3,chud_970_hsrr1
 354             beq         mtspr64_hsrr1
 355             cmpwi       r3,chud_970_hdec
 356             beq         mtspr64_hdec
 357             cmpwi       r3,chud_970_trig0
 358             beq         mtspr64_trig0
 359             cmpwi       r3,chud_970_trig1
 360             beq         mtspr64_trig1
 361             cmpwi       r3,chud_970_trig2
 362             beq         mtspr64_trig2
 363             cmpwi       r3,chud_ppc64_accr
 364             beq         mtspr64_accr
 365             cmpwi       r3,chud_970_scomc
 366             beq         mtspr64_scomc
 367             cmpwi       r3,chud_970_scomd
 368             beq         mtspr64_scomd
 369
 370             b           mtspr64_failure
 371
 372 mtspr64_srr0:
 373             ld          r5,0(r4)
 374             mtspr       chud_ppc_srr0,r5
 375             b           mtspr64_success
 376 mtspr64_srr1:
 377             ld          r5,0(r4)
 378             mtspr       chud_ppc_srr1,r5
 379             b           mtspr64_success
 380 mtspr64_dar:
 381             ld          r5,0(r4)
 382             mtspr       chud_ppc_dar,r5
 383             b           mtspr64_success
 384 mtspr64_sdr1:
 385             ld          r5,0(r4)
 386             mtspr       chud_ppc_sdr1,r5
 387             b           mtspr64_success
 388 mtspr64_sprg0:
 389             ld          r5,0(r4)
 390             mtspr       chud_ppc_sprg0,r5
 391             b           mtspr64_success
 392 mtspr64_sprg1:
 393             ld          r5,0(r4)
 394             mtspr       chud_ppc_sprg1,r5
 395             b           mtspr64_success
 396 mtspr64_sprg2:
 397             ld          r5,0(r4)
 398             mtspr       chud_ppc_sprg2,r5
 399             b           mtspr64_success
 400 mtspr64_sprg3:
 401             ld          r5,0(r4)
 402             mtspr       chud_ppc_sprg3,r5
 403             b           mtspr64_success
 404 mtspr64_asr:
 405             ld          r5,0(r4)
 406             mtspr       chud_ppc64_asr,r5
 407             b           mtspr64_success
 408 mtspr64_dabr:
 409             ld          r5,0(r4)
 410             mtspr       chud_ppc_dabr,r5
 411             b           mtspr64_success
 412 mtspr64_hid0:
 413             ld          r5,0(r4)
 414             sync
 415             mtspr       chud_970_hid0,r5
 416             mfspr       r5,chud_970_hid0        /* syncronization requirements */
 417             mfspr       r5,chud_970_hid0
 418             mfspr       r5,chud_970_hid0
 419             mfspr       r5,chud_970_hid0
 420             mfspr       r5,chud_970_hid0
 421             mfspr       r5,chud_970_hid0
 422             b           mtspr64_success
 423 mtspr64_hid1:
 424             ld          r5,0(r4)
 425             mtspr       chud_970_hid1,r5        /* tell you twice */
 426             mtspr       chud_970_hid1,r5
 427             isync
 428             b           mtspr64_success
 429 mtspr64_hid4:
 430             ld          r5,0(r4)
 431             sync                                /* syncronization requirements */
 432             mtspr       chud_970_hid4,r5
 433             isync
 434             b           mtspr64_success
 435 mtspr64_hid5:
 436             ld          r5,0(r4)
 437             mtspr       chud_970_hid5,r5
 438             b           mtspr64_success
 439 mtspr64_mmcr0:
 440             ld          r5,0(r4)
 441             mtspr       chud_970_mmcr0,r5
 442             b           mtspr64_success
 443 mtspr64_mmcr1:
 444             ld          r5,0(r4)
 445             mtspr       chud_970_mmcr1,r5
 446             b           mtspr64_success
 447 mtspr64_mmcra:
 448             ld          r5,0(r4)
 449             mtspr       chud_970_mmcra,r5
 450             b           mtspr64_success
 451 mtspr64_siar:
 452             ld          r5,0(r4)
 453             mtspr       chud_970_siar,r5
 454             b           mtspr64_success
 455 mtspr64_sdar:
 456             ld          r5,0(r4)
 457             mtspr       chud_970_sdar,r5
 458             b           mtspr64_success
 459 mtspr64_imc:
 460             ld          r5,0(r4)
 461             mtspr       chud_970_imc,r5
 462             b           mtspr64_success
 463 mtspr64_rmor:
 464             ld          r5,0(r4)
 465             mtspr       chud_970_rmor,r5
 466             b           mtspr64_success
 467 mtspr64_hrmor:
 468             ld          r5,0(r4)
 469             mtspr       chud_970_hrmor,r5
 470             b           mtspr64_success
 471 mtspr64_hior:
 472             ld          r5,0(r4)
 473             mtspr       chud_970_hior,r5
 474             b           mtspr64_success
 475 mtspr64_lpidr:
 476             ld          r5,0(r4)
 477             mtspr       chud_970_lpidr,r5
 478             b           mtspr64_success
 479 mtspr64_lpcr:
 480             ld          r5,0(r4)
 481             mtspr       chud_970_lpcr,r5
 482             b           mtspr64_success
 483 mtspr64_dabrx:
 484             ld          r5,0(r4)
 485             mtspr       chud_970_dabrx,r5
 486             b           mtspr64_success
 487 mtspr64_hsprg0:
 488             ld          r5,0(r4)
 489             mtspr       chud_970_hsprg0,r5
 490             b           mtspr64_success
 491 mtspr64_hsprg1:
 492             ld          r5,0(r4)
 493             mtspr       chud_970_hsprg1,r5
 494             b           mtspr64_success
 495 mtspr64_hsrr0:
 496             ld          r5,0(r4)
 497             mtspr       chud_970_hsrr0,r5
 498             b           mtspr64_success
 499 mtspr64_hsrr1:
 500             ld          r5,0(r4)
 501             mtspr       chud_970_hsrr1,r5
 502             b           mtspr64_success
 503 mtspr64_hdec:
 504             ld          r5,0(r4)
 505             mtspr       chud_970_hdec,r5
 506             b           mtspr64_success
 507 mtspr64_trig0:
 508             ld          r5,0(r4)
 509             mtspr       chud_970_trig0,r5
 510             b           mtspr64_success
 511 mtspr64_trig1:
 512             ld          r5,0(r4)
 513             mtspr       chud_970_trig1,r5
 514             b           mtspr64_success
 515 mtspr64_trig2:
 516             ld          r5,0(r4)
 517             mtspr       chud_970_trig2,r5
 518             b           mtspr64_success
 519 mtspr64_accr:
 520             ld          r5,0(r4)
 521             mtspr       chud_ppc64_accr,r5
 522             b           mtspr64_success
 523 mtspr64_scomc:
 524             ld          r5,0(r4)
 525             mtspr       chud_970_scomc,r5
 526             b           mtspr64_success
 527 mtspr64_scomd:
 528             ld          r5,0(r4)
 529             mtspr       chud_970_scomd,r5
 530             b           mtspr64_success
 531
 532 mtspr64_failure:
 533             li          r3,KERN_FAILURE
 534             blr
 535
 536 mtspr64_success:
 537             li          r3,KERN_SUCCESS
 538             blr
 539
 540
 541 /*
 542  * kern_return_t mfmsr64(uint64_t *val);
 543  *
 544  * r3: address to store value in
 545  *
 546  */
 547
 548 ;           Force a line boundry here
 549             .align  5
 550             .globl  EXT(mfmsr64)
 551
 552 EXT(mfmsr64):
 553             mfmsr       r5
 554             std         r5,0(r3)
 555 mfmsr64_success:
 556             li          r3,KERN_SUCCESS
 557             blr
 558
 559 mfmsr64_failure:
 560             li          r3,KERN_FAILURE
 561             blr
 562
 563
 564 /*
 565  * kern_return_t mtmsr64(uint64_t *val);
 566  *
 567  * r3: address to load value from
 568  *
 569  */
 570
 571 ;           Force a line boundry here
 572             .align  5
 573             .globl  EXT(mtmsr64)
 574
 575 EXT(mtmsr64):
 576             ld          r5,0(r3)
 577             mtmsrd      r5
 578             b           mtmsr64_success
 579
 580 mtmsr64_success:
 581             li          r3,KERN_SUCCESS
 582             blr
 583
 584 mtmsr64_failure:
 585             li          r3,KERN_FAILURE
 586             blr
 587
 588 .L_end: