EXTERNAL_HEADERS/architecture/ppc/fp_regs.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License.  The rights granted to you under the
  10  * License may not be used to create, or enable the creation or
  11  * redistribution of, unlawful or unlicensed copies of an Apple operating
  12  * system, or to circumvent, violate, or enable the circumvention or
  13  * violation of, any terms of an Apple operating system software license
  14  * agreement.
  15  *
  16  * Please obtain a copy of the License at
  17  * http://www.opensource.apple.com/apsl/ and read it before using this
  18  * file.
  19  *
  20  * The Original Code and all software distributed under the License are
  21  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  22  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  23  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  25  * Please see the License for the specific language governing rights and
  26  * limitations under the License.
  27  *
  28  * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
  29  */
  30 /* Copyright (c) 1996 NeXT Software, Inc.  All rights reserved.
  31  *
  32  *      File:   architecture/ppc/fp_regs.h
  33  *      Author: Doug Mitchell, NeXT Software, Inc.
  34  *
  35  *      ppc floating point registers.
  36  *
  37  * HISTORY
  38  * 29-Dec-96  Umesh Vaishampayan  (umeshv@NeXT.com)
  39  *      Ported from m98k.
  40  * 05-Nov-92  Doug Mitchell at NeXT
  41  *      Created.
  42  */
  43
  44 #ifndef _ARCH_PPC_FP_REGS_H_
  45 #define _ARCH_PPC_FP_REGS_H_
  46
  47 #include <architecture/ppc/reg_help.h>
  48
  49 #if !defined(__ASSEMBLER__)
  50 /*
  51  * Floating point status and control register.
  52  *
  53  * This struct is aligned to an 8-byte boundary because 64-bit
  54  * load/store instructions (lfd/stfd) are used to access it. The
  55  * FPSCR can only be read/written through other FP registers.
  56  */
  57 typedef struct {
  58         unsigned        unused[1] __attribute__(( aligned(8) ));
  59         unsigned        fx:BIT_WIDTH(31),       // exception summary
  60                         fex:BIT_WIDTH(30),      // enabled exception summary
  61                         vx:BIT_WIDTH(29),       // invalid op exception
  62                                                 //    summary
  63                         ox:BIT_WIDTH(28),       // overflow exception
  64                         ux:BIT_WIDTH(27),       // underflow exception
  65                         zx:BIT_WIDTH(26),       // divide by zero exception
  66                         xx:BIT_WIDTH(25),       // inexact exception
  67                         vx_snan:BIT_WIDTH(24),  // not a number exception
  68                         vx_isi:BIT_WIDTH(23),   // exception
  69                         vx_idi:BIT_WIDTH(22),   // exception
  70                         vx_zdz:BIT_WIDTH(21),   // exception
  71                         vx_imz:BIT_WIDTH(20),   // exception
  72                         vx_xvc:BIT_WIDTH(19),   // exception
  73                         fr:BIT_WIDTH(18),       // fraction rounded
  74                         fi:BIT_WIDTH(17),       // fraction inexact
  75                         class:BIT_WIDTH(16),    // class descriptor
  76                         fl:BIT_WIDTH(15),       // negative
  77                         fg:BIT_WIDTH(14),       // positive
  78                         fe:BIT_WIDTH(13),       // equal or zero
  79                         fu:BIT_WIDTH(12),       // not a number
  80                         rsvd1:BIT_WIDTH(11),    // reserved
  81                         vx_soft:BIT_WIDTH(10),  // software request exception
  82                         rsvd2:BIT_WIDTH(9),     // reserved
  83                         vx_cvi:BIT_WIDTH(8),    // invalid integer convert
  84                                                 //    exception
  85                         ve:BIT_WIDTH(7),        // invalid op exception enable
  86                         oe:BIT_WIDTH(6),        // overflow exception enable
  87                         ue:BIT_WIDTH(5),        // underflow exception enable
  88                         ze:BIT_WIDTH(4),        // divide by zero exception
  89                                                 //    enable
  90                         xe:BIT_WIDTH(3),        // inexact exception enable
  91                         ni:BIT_WIDTH(2),        // non-IEEE exception enable
  92                         rn:BITS_WIDTH(1,0);     // rounding control
  93 } ppc_fp_scr_t;
  94
  95 /*
  96  * Values for fp_scr_t.rn (rounding control).
  97  */
  98 typedef enum {
  99         RN_NEAREST = 0,
 100         RN_TOWARD_ZERO = 1,
 101         RN_TOWARD_PLUS = 2,
 102         RN_TOWARD_MINUS = 3
 103 } ppc_fp_rn_t;
 104
 105 /*
 106  * ppc_fpf_t -- data types that MAY be in floating point register file
 107  * Actual data types supported is implementation dependent
 108  */
 109 typedef union {
 110         float           f;              // 32 bit IEEE single
 111         double          d;              // 64 bit IEEE double
 112
 113         /*
 114          * Insure compiler aligns struct appropriately
 115          */
 116         unsigned        x[2] __attribute__(( aligned(8) ));
 117 } ppc_fpf_t;
 118
 119 /*
 120  * Number of FP registers.
 121  */
 122 #define PPC_NFP_REGS    32
 123
 124 /*
 125  * Read/write FPSCR.
 126  * FIXME - these don't work, you need to go thru a fp register.
 127  */
 128 typedef union {
 129         double          __dbl;
 130         ppc_fp_scr_t    __scr;
 131 } __fp_un_t;
 132
 133 static __inline__ ppc_fp_scr_t
 134 get_fp_scr()
 135 {
 136         __fp_un_t       __fp_un;
 137
 138         __asm__ volatile ("mffs. %0           /* mffs */"       \
 139                 : "=f" (__fp_un.__dbl));
 140         return (__fp_un.__scr);
 141 }
 142
 143 static __inline__ void
 144 set_fp_scr(ppc_fp_scr_t fp_scr)
 145 {
 146         __fp_un_t       __fp_un;
 147
 148         __fp_un.__scr = fp_scr;
 149         __asm__ volatile ("mtfsf 0xff, %0;    /* mtfsf */ "     \
 150           : : "f" (__fp_un.__dbl));
 151 }
 152
 153 #endif /* ! __ASSEMBLER__ */
 154
 155 #endif /* _ARCH_PPC_FP_REGS_H_ */