osfmk/arm64/tunables/tunables_h10.s

   1 /*
   2  * Copyright (c) 2019 Apple Inc. All rights reserved.
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   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
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   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
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  13  * terms of an Apple operating system software license agreement.
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  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
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  27  */
  28 .macro APPLY_TUNABLES
  29         /***** Tunables that apply to all cores, all revisions *****/
  30
  31         // <rdar://problem/28512310> SW WAR/eval: WKdm write ack lost when bif_wke_colorWrAck_XXaH asserts concurrently for both colors
  32         HID_SET_BITS ARM64_REG_HID8, ARM64_REG_HID8_WkeForceStrictOrder, $1
  33
  34         /***** Tunables that apply to all P cores, all revisions *****/
  35         /* N/A */
  36
  37         /***** Tunables that apply to all E cores, all revisions *****/
  38         /* N/A */
  39
  40         /***** Tunables that apply to specific cores, all revisions *****/
  41         EXEC_COREEQ_REVALL MIDR_SKYE_MISTRAL, $0, $1
  42         // <rdar://problem/30423928>: Atomic launch eligibility is erroneously taken away when a store at SMB gets invalidated
  43         HID_CLEAR_BITS ARM64_REG_EHID11, ARM64_REG_EHID11_SmbDrainThresh_mask, $1
  44         EXEC_END
  45
  46         /***** Tunables that apply to specific cores and revisions *****/
  47         EXEC_COREEQ_REVLO MIDR_SKYE_MISTRAL, CPU_VERSION_B0, $0, $1
  48
  49         // Disable downstream fill bypass logic
  50         // <rdar://problem/28545159> [Tunable] Skye - L2E fill bypass collision from both pipes to ecore
  51         HID_SET_BITS ARM64_REG_EHID5, ARM64_REG_EHID5_DisFillByp, $1
  52
  53         // Disable forwarding of return addresses to the NFP
  54         // <rdar://problem/30387067> Skye: FED incorrectly taking illegal va exception
  55         HID_SET_BITS ARM64_REG_EHID0, ARM64_REG_EHID0_nfpRetFwdDisb, $1
  56
  57         EXEC_END
  58
  59         EXEC_COREALL_REVLO CPU_VERSION_B0, $0, $1
  60
  61         // Disable clock divider gating
  62         // <rdar://problem/30854420> [Tunable/Errata][cpu_1p_1e] [CPGV2] ACC power down issue when link FSM switches from GO_DN to CANCEL and at the same time upStreamDrain request is set.
  63         HID_SET_BITS ARM64_REG_HID6, ARM64_REG_HID6_DisClkDivGating, $1
  64
  65         // Disable clock dithering
  66         // <rdar://problem/29022199> [Tunable] Skye A0: Linux: LLC PIO Errors
  67         HID_SET_BITS ARM64_REG_ACC_OVRD, ARM64_REG_ACC_OVRD_dsblClkDtr, $1
  68         HID_SET_BITS ARM64_REG_ACC_EBLK_OVRD, ARM64_REG_ACC_OVRD_dsblClkDtr, $1
  69
  70         EXEC_END
  71
  72         EXEC_COREALL_REVHS CPU_VERSION_B0, $0, $1
  73         // <rdar://problem/32512836>: Disable refcount syncing between E and P
  74         HID_INSERT_BITS ARM64_REG_CYC_OVRD, ARM64_REG_CYC_OVRD_dsblSnoopTime_mask, ARM64_REG_CYC_OVRD_dsblSnoopPTime, $1
  75         EXEC_END
  76 .endmacro