]> git.saurik.com Git - apple/xnu.git/blob - osfmk/i386/trap.c
projects / apple / xnu.git / blob
? search:


d7b4608786c2fd46b5168fe650dad279bc198ae2
[apple/xnu.git] / osfmk / i386 / trap.c
1 /*
2 * Copyright (c) 2000-2010 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58
59 /*
60 * Hardware trap/fault handler.
61 */
62
63 #include <mach_kdp.h>
64 #include <mach_ldebug.h>
65
66 #include <types.h>
67 #include <i386/eflags.h>
68 #include <i386/trap.h>
69 #include <i386/pmap.h>
70 #include <i386/fpu.h>
71 #include <i386/misc_protos.h> /* panic_io_port_read() */
72 #include <i386/lapic.h>
73
74 #include <mach/exception.h>
75 #include <mach/kern_return.h>
76 #include <mach/vm_param.h>
77 #include <mach/i386/thread_status.h>
78
79 #include <vm/vm_kern.h>
80 #include <vm/vm_fault.h>
81
82 #include <kern/kern_types.h>
83 #include <kern/processor.h>
84 #include <kern/thread.h>
85 #include <kern/task.h>
86 #include <kern/sched.h>
87 #include <kern/sched_prim.h>
88 #include <kern/exception.h>
89 #include <kern/spl.h>
90 #include <kern/misc_protos.h>
91 #include <kern/debug.h>
92
93 #include <sys/kdebug.h>
94
95 #include <string.h>
96
97 #include <i386/postcode.h>
98 #include <i386/mp_desc.h>
99 #include <i386/proc_reg.h>
100 #if CONFIG_MCA
101 #include <i386/machine_check.h>
102 #endif
103 #include <mach/i386/syscall_sw.h>
104
105 #include <libkern/OSDebug.h>
106
107 #include <machine/pal_routines.h>
108
109 extern void throttle_lowpri_io(int);
110 extern void kprint_state(x86_saved_state64_t *saved_state);
111
112 /*
113 * Forward declarations
114 */
115 static void user_page_fault_continue(kern_return_t kret);
116 #ifdef __i386__
117 static void panic_trap(x86_saved_state32_t *saved_state);
118 static void set_recovery_ip(x86_saved_state32_t *saved_state, vm_offset_t ip);
119 extern void panic_64(x86_saved_state_t *, int, const char *, boolean_t);
120 #else
121 static void panic_trap(x86_saved_state64_t *saved_state);
122 static void set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip);
123 #endif
124
125 volatile perfCallback perfTrapHook = NULL; /* Pointer to CHUD trap hook routine */
126
127 #if CONFIG_DTRACE
128 /* See <rdar://problem/4613924> */
129 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
130
131 extern boolean_t dtrace_tally_fault(user_addr_t);
132 #endif
133
134 extern boolean_t pmap_smep_enabled;
135
136 void
137 thread_syscall_return(
138 kern_return_t ret)
139 {
140 thread_t thr_act = current_thread();
141 boolean_t is_mach;
142 int code;
143
144 pal_register_cache_state(thr_act, DIRTY);
145
146 if (thread_is_64bit(thr_act)) {
147 x86_saved_state64_t *regs;
148
149 regs = USER_REGS64(thr_act);
150
151 code = (int) (regs->rax & SYSCALL_NUMBER_MASK);
152 is_mach = (regs->rax & SYSCALL_CLASS_MASK)
153 == (SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT);
154 if (kdebug_enable && is_mach) {
155 /* Mach trap */
156 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
157 MACHDBG_CODE(DBG_MACH_EXCP_SC,code)|DBG_FUNC_END,
158 ret, 0, 0, 0, 0);
159 }
160 regs->rax = ret;
161 #if DEBUG
162 if (is_mach)
163 DEBUG_KPRINT_SYSCALL_MACH(
164 "thread_syscall_return: 64-bit mach ret=%u\n",
165 ret);
166 else
167 DEBUG_KPRINT_SYSCALL_UNIX(
168 "thread_syscall_return: 64-bit unix ret=%u\n",
169 ret);
170 #endif
171 } else {
172 x86_saved_state32_t *regs;
173
174 regs = USER_REGS32(thr_act);
175
176 code = ((int) regs->eax);
177 is_mach = (code < 0);
178 if (kdebug_enable && is_mach) {
179 /* Mach trap */
180 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
181 MACHDBG_CODE(DBG_MACH_EXCP_SC,-code)|DBG_FUNC_END,
182 ret, 0, 0, 0, 0);
183 }
184 regs->eax = ret;
185 #if DEBUG
186 if (is_mach)
187 DEBUG_KPRINT_SYSCALL_MACH(
188 "thread_syscall_return: 32-bit mach ret=%u\n",
189 ret);
190 else
191 DEBUG_KPRINT_SYSCALL_UNIX(
192 "thread_syscall_return: 32-bit unix ret=%u\n",
193 ret);
194 #endif
195 }
196 throttle_lowpri_io(TRUE);
197
198 thread_exception_return();
199 /*NOTREACHED*/
200 }
201
202
203 static inline void
204 user_page_fault_continue(
205 kern_return_t kr)
206 {
207 thread_t thread = current_thread();
208 user_addr_t vaddr;
209
210 if (thread_is_64bit(thread)) {
211 x86_saved_state64_t *uregs;
212
213 uregs = USER_REGS64(thread);
214
215 vaddr = (user_addr_t)uregs->cr2;
216 } else {
217 x86_saved_state32_t *uregs;
218
219 uregs = USER_REGS32(thread);
220
221 vaddr = uregs->cr2;
222 }
223
224
225 /* PAL debug hook */
226 pal_dbg_page_fault( thread, vaddr, kr );
227
228 i386_exception(EXC_BAD_ACCESS, kr, vaddr);
229 /*NOTREACHED*/
230 }
231
232 /*
233 * Fault recovery in copyin/copyout routines.
234 */
235 struct recovery {
236 uintptr_t fault_addr;
237 uintptr_t recover_addr;
238 };
239
240 extern struct recovery recover_table[];
241 extern struct recovery recover_table_end[];
242
243 const char * trap_type[] = {TRAP_NAMES};
244 unsigned TRAP_TYPES = sizeof(trap_type)/sizeof(trap_type[0]);
245
246 extern void PE_incoming_interrupt(int interrupt);
247
248 #if defined(__x86_64__) && DEBUG
249 void
250 kprint_state(x86_saved_state64_t *saved_state)
251 {
252 kprintf("current_cpu_datap() 0x%lx\n", (uintptr_t)current_cpu_datap());
253 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
254 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
255 kprintf("state at 0x%lx:\n", (uintptr_t) saved_state);
256
257 kprintf(" rdi 0x%llx\n", saved_state->rdi);
258 kprintf(" rsi 0x%llx\n", saved_state->rsi);
259 kprintf(" rdx 0x%llx\n", saved_state->rdx);
260 kprintf(" r10 0x%llx\n", saved_state->r10);
261 kprintf(" r8 0x%llx\n", saved_state->r8);
262 kprintf(" r9 0x%llx\n", saved_state->r9);
263 kprintf(" v_arg6 0x%llx\n", saved_state->v_arg6);
264 kprintf(" v_arg7 0x%llx\n", saved_state->v_arg7);
265 kprintf(" v_arg8 0x%llx\n", saved_state->v_arg8);
266
267 kprintf(" cr2 0x%llx\n", saved_state->cr2);
268 kprintf("real cr2 0x%lx\n", get_cr2());
269 kprintf(" r15 0x%llx\n", saved_state->r15);
270 kprintf(" r14 0x%llx\n", saved_state->r14);
271 kprintf(" r13 0x%llx\n", saved_state->r13);
272 kprintf(" r12 0x%llx\n", saved_state->r12);
273 kprintf(" r11 0x%llx\n", saved_state->r11);
274 kprintf(" rbp 0x%llx\n", saved_state->rbp);
275 kprintf(" rbx 0x%llx\n", saved_state->rbx);
276 kprintf(" rcx 0x%llx\n", saved_state->rcx);
277 kprintf(" rax 0x%llx\n", saved_state->rax);
278
279 kprintf(" gs 0x%x\n", saved_state->gs);
280 kprintf(" fs 0x%x\n", saved_state->fs);
281
282 kprintf(" isf.trapno 0x%x\n", saved_state->isf.trapno);
283 kprintf(" isf._pad 0x%x\n", saved_state->isf._pad);
284 kprintf(" isf.trapfn 0x%llx\n", saved_state->isf.trapfn);
285 kprintf(" isf.err 0x%llx\n", saved_state->isf.err);
286 kprintf(" isf.rip 0x%llx\n", saved_state->isf.rip);
287 kprintf(" isf.cs 0x%llx\n", saved_state->isf.cs);
288 kprintf(" isf.rflags 0x%llx\n", saved_state->isf.rflags);
289 kprintf(" isf.rsp 0x%llx\n", saved_state->isf.rsp);
290 kprintf(" isf.ss 0x%llx\n", saved_state->isf.ss);
291 }
292 #endif
293
294
295 /*
296 * Non-zero indicates latency assert is enabled and capped at valued
297 * absolute time units.
298 */
299
300 uint64_t interrupt_latency_cap = 0;
301 boolean_t ilat_assert = FALSE;
302
303 void
304 interrupt_latency_tracker_setup(void) {
305 uint32_t ilat_cap_us;
306 if (PE_parse_boot_argn("interrupt_latency_cap_us", &ilat_cap_us, sizeof(ilat_cap_us))) {
307 interrupt_latency_cap = ilat_cap_us * NSEC_PER_USEC;
308 nanoseconds_to_absolutetime(interrupt_latency_cap, &interrupt_latency_cap);
309 } else {
310 interrupt_latency_cap = LockTimeOut;
311 }
312 PE_parse_boot_argn("-interrupt_latency_assert_enable", &ilat_assert, sizeof(ilat_assert));
313 }
314
315 void interrupt_reset_latency_stats(void) {
316 uint32_t i;
317 for (i = 0; i < real_ncpus; i++) {
318 cpu_data_ptr[i]->cpu_max_observed_int_latency =
319 cpu_data_ptr[i]->cpu_max_observed_int_latency_vector = 0;
320 }
321 }
322
323 void interrupt_populate_latency_stats(char *buf, unsigned bufsize) {
324 uint32_t i, tcpu = ~0;
325 uint64_t cur_max = 0;
326
327 for (i = 0; i < real_ncpus; i++) {
328 if (cur_max < cpu_data_ptr[i]->cpu_max_observed_int_latency) {
329 cur_max = cpu_data_ptr[i]->cpu_max_observed_int_latency;
330 tcpu = i;
331 }
332 }
333
334 if (tcpu < real_ncpus)
335 snprintf(buf, bufsize, "0x%x 0x%x 0x%llx", tcpu, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency_vector, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency);
336 }
337
338 /*
339 * Handle interrupts:
340 * - local APIC interrupts (IPIs, timers, etc) are handled by the kernel,
341 * - device interrupts go to the platform expert.
342 */
343 void
344 interrupt(x86_saved_state_t *state)
345 {
346 uint64_t rip;
347 uint64_t rsp;
348 int interrupt_num;
349 boolean_t user_mode = FALSE;
350 int ipl;
351 int cnum = cpu_number();
352 int itype = 0;
353
354 if (is_saved_state64(state) == TRUE) {
355 x86_saved_state64_t *state64;
356
357 state64 = saved_state64(state);
358 rip = state64->isf.rip;
359 rsp = state64->isf.rsp;
360 interrupt_num = state64->isf.trapno;
361 #ifdef __x86_64__
362 if(state64->isf.cs & 0x03)
363 #endif
364 user_mode = TRUE;
365 } else {
366 x86_saved_state32_t *state32;
367
368 state32 = saved_state32(state);
369 if (state32->cs & 0x03)
370 user_mode = TRUE;
371 rip = state32->eip;
372 rsp = state32->uesp;
373 interrupt_num = state32->trapno;
374 }
375
376 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_INTERPROCESSOR_INTERRUPT))
377 itype = 1;
378 else if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_TIMER_INTERRUPT))
379 itype = 2;
380 else
381 itype = 3;
382
383 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
384 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
385 interrupt_num,
386 (user_mode ? rip : VM_KERNEL_UNSLIDE(rip)),
387 user_mode, itype, 0);
388
389 SCHED_STATS_INTERRUPT(current_processor());
390
391 ipl = get_preemption_level();
392
393 /*
394 * Handle local APIC interrupts
395 * else call platform expert for devices.
396 */
397 if (!lapic_interrupt(interrupt_num, state))
398 PE_incoming_interrupt(interrupt_num);
399
400 if (__improbable(get_preemption_level() != ipl)) {
401 panic("Preemption level altered by interrupt vector 0x%x: initial 0x%x, final: 0x%x\n", interrupt_num, ipl, get_preemption_level());
402 }
403
404
405 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
406 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END,
407 interrupt_num, 0, 0, 0, 0);
408
409 if (cpu_data_ptr[cnum]->cpu_nested_istack) {
410 cpu_data_ptr[cnum]->cpu_nested_istack_events++;
411 }
412 else {
413 uint64_t int_latency = mach_absolute_time() - cpu_data_ptr[cnum]->cpu_int_event_time;
414 if (ilat_assert && (int_latency > interrupt_latency_cap) && !machine_timeout_suspended()) {
415 panic("Interrupt vector 0x%x exceeded interrupt latency threshold, 0x%llx absolute time delta, prior signals: 0x%x, current signals: 0x%x", interrupt_num, int_latency, cpu_data_ptr[cnum]->cpu_prior_signals, cpu_data_ptr[cnum]->cpu_signals);
416 }
417 if (int_latency > cpu_data_ptr[cnum]->cpu_max_observed_int_latency) {
418 cpu_data_ptr[cnum]->cpu_max_observed_int_latency = int_latency;
419 cpu_data_ptr[cnum]->cpu_max_observed_int_latency_vector = interrupt_num;
420 }
421 }
422
423 /*
424 * Having serviced the interrupt first, look at the interrupted stack depth.
425 */
426 if (!user_mode) {
427 uint64_t depth = cpu_data_ptr[cnum]->cpu_kernel_stack
428 + sizeof(struct x86_kernel_state)
429 + sizeof(struct i386_exception_link *)
430 - rsp;
431 if (depth > kernel_stack_depth_max) {
432 kernel_stack_depth_max = (vm_offset_t)depth;
433 KERNEL_DEBUG_CONSTANT(
434 MACHDBG_CODE(DBG_MACH_SCHED, MACH_STACK_DEPTH),
435 (long) depth, (long) VM_KERNEL_UNSLIDE(rip), 0, 0, 0);
436 }
437 }
438 }
439
440 static inline void
441 reset_dr7(void)
442 {
443 long dr7 = 0x400; /* magic dr7 reset value; 32 bit on i386, 64 bit on x86_64 */
444 __asm__ volatile("mov %0,%%dr7" : : "r" (dr7));
445 }
446 #if MACH_KDP
447 unsigned kdp_has_active_watchpoints = 0;
448 #define NO_WATCHPOINTS (!kdp_has_active_watchpoints)
449 #else
450 #define NO_WATCHPOINTS 1
451 #endif
452 /*
453 * Trap from kernel mode. Only page-fault errors are recoverable,
454 * and then only in special circumstances. All other errors are
455 * fatal. Return value indicates if trap was handled.
456 */
457
458 void
459 kernel_trap(
460 x86_saved_state_t *state,
461 uintptr_t *lo_spp)
462 {
463 #ifdef __i386__
464 x86_saved_state32_t *saved_state;
465 #else
466 x86_saved_state64_t *saved_state;
467 #endif
468 int code;
469 user_addr_t vaddr;
470 int type;
471 vm_map_t map = 0; /* protected by T_PAGE_FAULT */
472 kern_return_t result = KERN_FAILURE;
473 thread_t thread;
474 ast_t *myast;
475 boolean_t intr;
476 vm_prot_t prot;
477 struct recovery *rp;
478 vm_offset_t kern_ip;
479 #if NCOPY_WINDOWS > 0
480 int fault_in_copy_window = -1;
481 #endif
482 int is_user = 0;
483
484 thread = current_thread();
485
486 #ifdef __i386__
487 if (__improbable(is_saved_state64(state))) {
488 panic_64(state, 0, "Kernel trap with 64-bit state", FALSE);
489 }
490
491 saved_state = saved_state32(state);
492
493 /* Record cpu where state was captured (trampolines don't set this) */
494 saved_state->cpu = cpu_number();
495
496 vaddr = (user_addr_t)saved_state->cr2;
497 type = saved_state->trapno;
498 code = saved_state->err & 0xffff;
499 intr = (saved_state->efl & EFL_IF) != 0; /* state of ints at trap */
500 kern_ip = (vm_offset_t)saved_state->eip;
501 #else
502 if (__improbable(is_saved_state32(state)))
503 panic("kernel_trap(%p) with 32-bit state", state);
504 saved_state = saved_state64(state);
505
506 /* Record cpu where state was captured */
507 saved_state->isf.cpu = cpu_number();
508
509 vaddr = (user_addr_t)saved_state->cr2;
510 type = saved_state->isf.trapno;
511 code = (int)(saved_state->isf.err & 0xffff);
512 intr = (saved_state->isf.rflags & EFL_IF) != 0; /* state of ints at trap */
513 kern_ip = (vm_offset_t)saved_state->isf.rip;
514 #endif
515
516 myast = ast_pending();
517
518 perfASTCallback astfn = perfASTHook;
519 if (__improbable(astfn != NULL)) {
520 if (*myast & AST_CHUD_ALL)
521 astfn(AST_CHUD_ALL, myast);
522 } else
523 *myast &= ~AST_CHUD_ALL;
524
525 /*
526 * Is there a hook?
527 */
528 perfCallback fn = perfTrapHook;
529 if (__improbable(fn != NULL)) {
530 if (fn(type, NULL, 0, 0) == KERN_SUCCESS) {
531 /*
532 * If it succeeds, we are done...
533 */
534 return;
535 }
536 }
537
538 #if CONFIG_DTRACE
539 if (__improbable(tempDTraceTrapHook != NULL)) {
540 if (tempDTraceTrapHook(type, state, lo_spp, 0) == KERN_SUCCESS) {
541 /*
542 * If it succeeds, we are done...
543 */
544 return;
545 }
546 }
547 #endif /* CONFIG_DTRACE */
548
549 /*
550 * we come here with interrupts off as we don't want to recurse
551 * on preemption below. but we do want to re-enable interrupts
552 * as soon we possibly can to hold latency down
553 */
554 if (__improbable(T_PREEMPT == type)) {
555 ast_taken(AST_PREEMPTION, FALSE);
556
557 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
558 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
559 0, 0, 0, VM_KERNEL_UNSLIDE(kern_ip), 0);
560 return;
561 }
562
563 if (T_PAGE_FAULT == type) {
564 /*
565 * assume we're faulting in the kernel map
566 */
567 map = kernel_map;
568
569 if (__probable(thread != THREAD_NULL && thread->map != kernel_map)) {
570 #if NCOPY_WINDOWS > 0
571 vm_offset_t copy_window_base;
572 vm_offset_t kvaddr;
573 int window_index;
574
575 kvaddr = (vm_offset_t)vaddr;
576 /*
577 * must determine if fault occurred in
578 * the copy window while pre-emption is
579 * disabled for this processor so that
580 * we only need to look at the window
581 * associated with this processor
582 */
583 copy_window_base = current_cpu_datap()->cpu_copywindow_base;
584
585 if (kvaddr >= copy_window_base && kvaddr < (copy_window_base + (NBPDE * NCOPY_WINDOWS)) ) {
586
587 window_index = (int)((kvaddr - copy_window_base) / NBPDE);
588
589 if (thread->machine.copy_window[window_index].user_base != (user_addr_t)-1) {
590
591 kvaddr -= (copy_window_base + (NBPDE * window_index));
592 vaddr = thread->machine.copy_window[window_index].user_base + kvaddr;
593
594 map = thread->map;
595 fault_in_copy_window = window_index;
596 }
597 is_user = -1;
598 }
599 #else
600 if (__probable(vaddr < VM_MAX_USER_PAGE_ADDRESS)) {
601 /* fault occurred in userspace */
602 map = thread->map;
603 is_user = -1;
604
605 /* Intercept a potential Supervisor Mode Execute
606 * Protection fault. These criteria identify
607 * both NX faults and SMEP faults, but both
608 * are fatal. We avoid checking PTEs (racy).
609 * (The VM could just redrive a SMEP fault, hence
610 * the intercept).
611 */
612 if (__improbable((code == (T_PF_PROT | T_PF_EXECUTE)) && (pmap_smep_enabled) && (saved_state->isf.rip == vaddr))) {
613 goto debugger_entry;
614 }
615
616 /*
617 * If we're not sharing cr3 with the user
618 * and we faulted in copyio,
619 * then switch cr3 here and dismiss the fault.
620 */
621 if (no_shared_cr3 &&
622 (thread->machine.specFlags&CopyIOActive) &&
623 map->pmap->pm_cr3 != get_cr3_base()) {
624 pmap_assert(current_cpu_datap()->cpu_pmap_pcid_enabled == FALSE);
625 set_cr3_raw(map->pmap->pm_cr3);
626 return;
627 }
628 }
629 #endif
630 }
631 }
632 user_addr_t kd_vaddr = is_user ? vaddr : VM_KERNEL_UNSLIDE(vaddr);
633 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
634 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
635 (unsigned)(kd_vaddr >> 32), (unsigned)kd_vaddr, is_user,
636 VM_KERNEL_UNSLIDE(kern_ip), 0);
637
638
639 (void) ml_set_interrupts_enabled(intr);
640
641 switch (type) {
642
643 case T_NO_FPU:
644 fpnoextflt();
645 return;
646
647 case T_FPU_FAULT:
648 fpextovrflt();
649 return;
650
651 case T_FLOATING_POINT_ERROR:
652 fpexterrflt();
653 return;
654
655 case T_SSE_FLOAT_ERROR:
656 fpSSEexterrflt();
657 return;
658 case T_DEBUG:
659 #ifdef __i386__
660 if ((saved_state->efl & EFL_TF) == 0 && NO_WATCHPOINTS)
661 #else
662 if ((saved_state->isf.rflags & EFL_TF) == 0 && NO_WATCHPOINTS)
663 #endif
664 {
665 /* We've somehow encountered a debug
666 * register match that does not belong
667 * to the kernel debugger.
668 * This isn't supposed to happen.
669 */
670 reset_dr7();
671 return;
672 }
673 goto debugger_entry;
674 #ifdef __x86_64__
675 case T_INT3:
676 goto debugger_entry;
677 #endif
678 case T_PAGE_FAULT:
679
680 #if CONFIG_DTRACE
681 if (thread != THREAD_NULL && thread->options & TH_OPT_DTRACE) { /* Executing under dtrace_probe? */
682 if (dtrace_tally_fault(vaddr)) { /* Should a fault under dtrace be ignored? */
683 /*
684 * DTrace has "anticipated" the possibility of this fault, and has
685 * established the suitable recovery state. Drop down now into the
686 * recovery handling code in "case T_GENERAL_PROTECTION:".
687 */
688 goto FALL_THROUGH;
689 }
690 }
691 #endif /* CONFIG_DTRACE */
692
693 prot = VM_PROT_READ;
694
695 if (code & T_PF_WRITE)
696 prot |= VM_PROT_WRITE;
697 #if PAE
698 if (code & T_PF_EXECUTE)
699 prot |= VM_PROT_EXECUTE;
700 #endif
701
702 result = vm_fault(map,
703 vm_map_trunc_page(vaddr),
704 prot,
705 FALSE,
706 THREAD_UNINT, NULL, 0);
707
708 if (result == KERN_SUCCESS) {
709 #if NCOPY_WINDOWS > 0
710 if (fault_in_copy_window != -1) {
711 ml_set_interrupts_enabled(FALSE);
712 copy_window_fault(thread, map,
713 fault_in_copy_window);
714 (void) ml_set_interrupts_enabled(intr);
715 }
716 #endif /* NCOPY_WINDOWS > 0 */
717 return;
718 }
719 /*
720 * fall through
721 */
722 #if CONFIG_DTRACE
723 FALL_THROUGH:
724 #endif /* CONFIG_DTRACE */
725
726 case T_GENERAL_PROTECTION:
727 /*
728 * If there is a failure recovery address
729 * for this fault, go there.
730 */
731 for (rp = recover_table; rp < recover_table_end; rp++) {
732 if (kern_ip == rp->fault_addr) {
733 set_recovery_ip(saved_state, rp->recover_addr);
734 return;
735 }
736 }
737
738 /*
739 * Check thread recovery address also.
740 */
741 if (thread != THREAD_NULL && thread->recover) {
742 set_recovery_ip(saved_state, thread->recover);
743 thread->recover = 0;
744 return;
745 }
746 /*
747 * Unanticipated page-fault errors in kernel
748 * should not happen.
749 *
750 * fall through...
751 */
752 default:
753 /*
754 * Exception 15 is reserved but some chips may generate it
755 * spuriously. Seen at startup on AMD Athlon-64.
756 */
757 if (type == 15) {
758 kprintf("kernel_trap() ignoring spurious trap 15\n");
759 return;
760 }
761 debugger_entry:
762 /* Ensure that the i386_kernel_state at the base of the
763 * current thread's stack (if any) is synchronized with the
764 * context at the moment of the trap, to facilitate
765 * access through the debugger.
766 */
767 sync_iss_to_iks(state);
768 #if MACH_KDP
769 if (current_debugger != KDB_CUR_DB) {
770 if (kdp_i386_trap(type, saved_state, result, (vm_offset_t)vaddr))
771 return;
772 }
773 #endif
774 }
775 pal_cli();
776 panic_trap(saved_state);
777 /*
778 * NO RETURN
779 */
780 }
781
782
783 #ifdef __i386__
784 static void
785 set_recovery_ip(x86_saved_state32_t *saved_state, vm_offset_t ip)
786 {
787 saved_state->eip = ip;
788 }
789 #else
790 static void
791 set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip)
792 {
793 saved_state->isf.rip = ip;
794 }
795 #endif
796
797
798 #ifdef __i386__
799 static void
800 panic_trap(x86_saved_state32_t *regs)
801 {
802 const char *trapname = "Unknown";
803 pal_cr_t cr0, cr2, cr3, cr4;
804
805 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
806
807 /*
808 * Issue an I/O port read if one has been requested - this is an
809 * event logic analyzers can use as a trigger point.
810 */
811 panic_io_port_read();
812
813 kprintf("panic trap number 0x%x, eip 0x%x\n", regs->trapno, regs->eip);
814 kprintf("cr0 0x%08x cr2 0x%08x cr3 0x%08x cr4 0x%08x\n",
815 cr0, cr2, cr3, cr4);
816
817 if (regs->trapno < TRAP_TYPES)
818 trapname = trap_type[regs->trapno];
819 #undef panic
820 panic("Kernel trap at 0x%08x, type %d=%s, registers:\n"
821 "CR0: 0x%08x, CR2: 0x%08x, CR3: 0x%08x, CR4: 0x%08x\n"
822 "EAX: 0x%08x, EBX: 0x%08x, ECX: 0x%08x, EDX: 0x%08x\n"
823 "CR2: 0x%08x, EBP: 0x%08x, ESI: 0x%08x, EDI: 0x%08x\n"
824 "EFL: 0x%08x, EIP: 0x%08x, CS: 0x%08x, DS: 0x%08x\n"
825 "Error code: 0x%08x%s\n",
826 regs->eip, regs->trapno, trapname, cr0, cr2, cr3, cr4,
827 regs->eax,regs->ebx,regs->ecx,regs->edx,
828 regs->cr2,regs->ebp,regs->esi,regs->edi,
829 regs->efl,regs->eip,regs->cs & 0xFFFF, regs->ds & 0xFFFF, regs->err,
830 virtualized ? " VMM" : "");
831 /*
832 * This next statement is not executed,
833 * but it's needed to stop the compiler using tail call optimization
834 * for the panic call - which confuses the subsequent backtrace.
835 */
836 cr0 = 0;
837 }
838 #else
839
840
841 static void
842 panic_trap(x86_saved_state64_t *regs)
843 {
844 const char *trapname = "Unknown";
845 pal_cr_t cr0, cr2, cr3, cr4;
846 boolean_t potential_smep_fault = FALSE, potential_kernel_NX_fault = FALSE;
847
848 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
849 assert(ml_get_interrupts_enabled() == FALSE);
850 current_cpu_datap()->cpu_fatal_trap_state = regs;
851 /*
852 * Issue an I/O port read if one has been requested - this is an
853 * event logic analyzers can use as a trigger point.
854 */
855 panic_io_port_read();
856
857 kprintf("panic trap number 0x%x, rip 0x%016llx\n",
858 regs->isf.trapno, regs->isf.rip);
859 kprintf("cr0 0x%016llx cr2 0x%016llx cr3 0x%016llx cr4 0x%016llx\n",
860 cr0, cr2, cr3, cr4);
861
862 if (regs->isf.trapno < TRAP_TYPES)
863 trapname = trap_type[regs->isf.trapno];
864
865 if ((regs->isf.trapno == T_PAGE_FAULT) && (regs->isf.err == (T_PF_PROT | T_PF_EXECUTE)) && (regs->isf.rip == regs->cr2)) {
866 if (pmap_smep_enabled && (regs->isf.rip < VM_MAX_USER_PAGE_ADDRESS)) {
867 potential_smep_fault = TRUE;
868 } else if (regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
869 potential_kernel_NX_fault = TRUE;
870 }
871 }
872
873 #undef panic
874 panic("Kernel trap at 0x%016llx, type %d=%s, registers:\n"
875 "CR0: 0x%016llx, CR2: 0x%016llx, CR3: 0x%016llx, CR4: 0x%016llx\n"
876 "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
877 "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
878 "R8: 0x%016llx, R9: 0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
879 "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
880 "RFL: 0x%016llx, RIP: 0x%016llx, CS: 0x%016llx, SS: 0x%016llx\n"
881 "Fault CR2: 0x%016llx, Error code: 0x%016llx, Fault CPU: 0x%x%s%s%s\n",
882 regs->isf.rip, regs->isf.trapno, trapname,
883 cr0, cr2, cr3, cr4,
884 regs->rax, regs->rbx, regs->rcx, regs->rdx,
885 regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
886 regs->r8, regs->r9, regs->r10, regs->r11,
887 regs->r12, regs->r13, regs->r14, regs->r15,
888 regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,
889 regs->isf.ss & 0xFFFF,regs->cr2, regs->isf.err, regs->isf.cpu,
890 virtualized ? " VMM" : "",
891 potential_kernel_NX_fault ? " Kernel NX fault" : "",
892 potential_smep_fault ? " SMEP/User NX fault" : "");
893 /*
894 * This next statement is not executed,
895 * but it's needed to stop the compiler using tail call optimization
896 * for the panic call - which confuses the subsequent backtrace.
897 */
898 cr0 = 0;
899 }
900 #endif
901
902 #if CONFIG_DTRACE
903 extern kern_return_t dtrace_user_probe(x86_saved_state_t *);
904 #endif
905
906 /*
907 * Trap from user mode.
908 */
909 void
910 user_trap(
911 x86_saved_state_t *saved_state)
912 {
913 int exc;
914 int err;
915 mach_exception_code_t code;
916 mach_exception_subcode_t subcode;
917 int type;
918 user_addr_t vaddr;
919 vm_prot_t prot;
920 thread_t thread = current_thread();
921 ast_t *myast;
922 kern_return_t kret;
923 user_addr_t rip;
924 unsigned long dr6 = 0; /* 32 bit for i386, 64 bit for x86_64 */
925
926 assert((is_saved_state32(saved_state) && !thread_is_64bit(thread)) ||
927 (is_saved_state64(saved_state) && thread_is_64bit(thread)));
928
929 if (is_saved_state64(saved_state)) {
930 x86_saved_state64_t *regs;
931
932 regs = saved_state64(saved_state);
933
934 /* Record cpu where state was captured */
935 regs->isf.cpu = cpu_number();
936
937 type = regs->isf.trapno;
938 err = (int)regs->isf.err & 0xffff;
939 vaddr = (user_addr_t)regs->cr2;
940 rip = (user_addr_t)regs->isf.rip;
941 } else {
942 x86_saved_state32_t *regs;
943
944 regs = saved_state32(saved_state);
945
946 /* Record cpu where state was captured */
947 regs->cpu = cpu_number();
948
949 type = regs->trapno;
950 err = regs->err & 0xffff;
951 vaddr = (user_addr_t)regs->cr2;
952 rip = (user_addr_t)regs->eip;
953 }
954
955 if ((type == T_DEBUG) && thread->machine.ids) {
956 unsigned long clear = 0;
957 /* Stash and clear this processor's DR6 value, in the event
958 * this was a debug register match
959 */
960 __asm__ volatile ("mov %%db6, %0" : "=r" (dr6));
961 __asm__ volatile ("mov %0, %%db6" : : "r" (clear));
962 }
963
964 pal_sti();
965
966 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
967 (MACHDBG_CODE(DBG_MACH_EXCP_UTRAP_x86, type)) | DBG_FUNC_NONE,
968 (unsigned)(vaddr>>32), (unsigned)vaddr,
969 (unsigned)(rip>>32), (unsigned)rip, 0);
970
971 code = 0;
972 subcode = 0;
973 exc = 0;
974
975 #if DEBUG_TRACE
976 kprintf("user_trap(0x%08x) type=%d vaddr=0x%016llx\n",
977 saved_state, type, vaddr);
978 #endif
979
980 perfASTCallback astfn = perfASTHook;
981 if (__improbable(astfn != NULL)) {
982 myast = ast_pending();
983 if (*myast & AST_CHUD_ALL) {
984 astfn(AST_CHUD_ALL, myast);
985 }
986 }
987
988 /* Is there a hook? */
989 perfCallback fn = perfTrapHook;
990 if (__improbable(fn != NULL)) {
991 if (fn(type, saved_state, 0, 0) == KERN_SUCCESS)
992 return; /* If it succeeds, we are done... */
993 }
994
995 /*
996 * DTrace does not consume all user traps, only INT_3's for now.
997 * Avoid needlessly calling tempDTraceTrapHook here, and let the
998 * INT_3 case handle them.
999 */
1000 DEBUG_KPRINT_SYSCALL_MASK(1,
1001 "user_trap: type=0x%x(%s) err=0x%x cr2=%p rip=%p\n",
1002 type, trap_type[type], err, (void *)(long) vaddr, (void *)(long) rip);
1003
1004 switch (type) {
1005
1006 case T_DIVIDE_ERROR:
1007 exc = EXC_ARITHMETIC;
1008 code = EXC_I386_DIV;
1009 break;
1010
1011 case T_DEBUG:
1012 {
1013 pcb_t pcb;
1014 /*
1015 * Update the PCB with this processor's DR6 value
1016 * in the event this was a debug register match.
1017 */
1018 pcb = THREAD_TO_PCB(thread);
1019 if (pcb->ids) {
1020 /*
1021 * We can get and set the status register
1022 * in 32-bit mode even on a 64-bit thread
1023 * because the high order bits are not
1024 * used on x86_64
1025 */
1026 if (thread_is_64bit(thread)) {
1027 x86_debug_state64_t *ids = pcb->ids;
1028 ids->dr6 = dr6;
1029 } else { /* 32 bit thread */
1030 x86_debug_state32_t *ids = pcb->ids;
1031 ids->dr6 = (uint32_t) dr6;
1032 }
1033 }
1034 exc = EXC_BREAKPOINT;
1035 code = EXC_I386_SGL;
1036 break;
1037 }
1038 case T_INT3:
1039 #if CONFIG_DTRACE
1040 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
1041 return; /* If it succeeds, we are done... */
1042 #endif
1043 exc = EXC_BREAKPOINT;
1044 code = EXC_I386_BPT;
1045 break;
1046
1047 case T_OVERFLOW:
1048 exc = EXC_ARITHMETIC;
1049 code = EXC_I386_INTO;
1050 break;
1051
1052 case T_OUT_OF_BOUNDS:
1053 exc = EXC_SOFTWARE;
1054 code = EXC_I386_BOUND;
1055 break;
1056
1057 case T_INVALID_OPCODE:
1058 exc = EXC_BAD_INSTRUCTION;
1059 code = EXC_I386_INVOP;
1060 break;
1061
1062 case T_NO_FPU:
1063 fpnoextflt();
1064 return;
1065
1066 case T_FPU_FAULT:
1067 fpextovrflt(); /* Propagates exception directly, doesn't return */
1068 return;
1069
1070 case T_INVALID_TSS: /* invalid TSS == iret with NT flag set */
1071 exc = EXC_BAD_INSTRUCTION;
1072 code = EXC_I386_INVTSSFLT;
1073 subcode = err;
1074 break;
1075
1076 case T_SEGMENT_NOT_PRESENT:
1077 exc = EXC_BAD_INSTRUCTION;
1078 code = EXC_I386_SEGNPFLT;
1079 subcode = err;
1080 break;
1081
1082 case T_STACK_FAULT:
1083 exc = EXC_BAD_INSTRUCTION;
1084 code = EXC_I386_STKFLT;
1085 subcode = err;
1086 break;
1087
1088 case T_GENERAL_PROTECTION:
1089 /*
1090 * There's a wide range of circumstances which generate this
1091 * class of exception. From user-space, many involve bad
1092 * addresses (such as a non-canonical 64-bit address).
1093 * So we map this to EXC_BAD_ACCESS (and thereby SIGSEGV).
1094 * The trouble is cr2 doesn't contain the faulting address;
1095 * we'd need to decode the faulting instruction to really
1096 * determine this. We'll leave that to debuggers.
1097 * However, attempted execution of privileged instructions
1098 * (e.g. cli) also generate GP faults and so we map these to
1099 * to EXC_BAD_ACCESS (and thence SIGSEGV) also - rather than
1100 * EXC_BAD_INSTRUCTION which is more accurate. We just can't
1101 * win!
1102 */
1103 exc = EXC_BAD_ACCESS;
1104 code = EXC_I386_GPFLT;
1105 subcode = err;
1106 break;
1107
1108 case T_PAGE_FAULT:
1109 {
1110 prot = VM_PROT_READ;
1111
1112 if (err & T_PF_WRITE)
1113 prot |= VM_PROT_WRITE;
1114 #if PAE
1115 if (__improbable(err & T_PF_EXECUTE))
1116 prot |= VM_PROT_EXECUTE;
1117 #endif
1118 kret = vm_fault(thread->map, vm_map_trunc_page(vaddr),
1119 prot, FALSE,
1120 THREAD_ABORTSAFE, NULL, 0);
1121
1122 if (__probable((kret == KERN_SUCCESS) || (kret == KERN_ABORTED))) {
1123 thread_exception_return();
1124 /* NOTREACHED */
1125 }
1126
1127 user_page_fault_continue(kret);
1128 } /* NOTREACHED */
1129 break;
1130
1131 case T_SSE_FLOAT_ERROR:
1132 fpSSEexterrflt(); /* Propagates exception directly, doesn't return */
1133 return;
1134
1135
1136 case T_FLOATING_POINT_ERROR:
1137 fpexterrflt(); /* Propagates exception directly, doesn't return */
1138 return;
1139
1140 case T_DTRACE_RET:
1141 #if CONFIG_DTRACE
1142 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
1143 return; /* If it succeeds, we are done... */
1144 #endif
1145 /*
1146 * If we get an INT 0x7f when we do not expect to,
1147 * treat it as an illegal instruction
1148 */
1149 exc = EXC_BAD_INSTRUCTION;
1150 code = EXC_I386_INVOP;
1151 break;
1152
1153 default:
1154 panic("Unexpected user trap, type %d", type);
1155 return;
1156 }
1157 /* Note: Codepaths that directly return from user_trap() have pending
1158 * ASTs processed in locore
1159 */
1160 i386_exception(exc, code, subcode);
1161 /* NOTREACHED */
1162 }
1163
1164
1165 /*
1166 * Handle AST traps for i386.
1167 */
1168
1169 extern void log_thread_action (thread_t, char *);
1170
1171 void
1172 i386_astintr(int preemption)
1173 {
1174 ast_t mask = AST_ALL;
1175 spl_t s;
1176
1177 if (preemption)
1178 mask = AST_PREEMPTION;
1179
1180 s = splsched();
1181
1182 ast_taken(mask, s);
1183
1184 splx(s);
1185 }
1186
1187 /*
1188 * Handle exceptions for i386.
1189 *
1190 * If we are an AT bus machine, we must turn off the AST for a
1191 * delayed floating-point exception.
1192 *
1193 * If we are providing floating-point emulation, we may have
1194 * to retrieve the real register values from the floating point
1195 * emulator.
1196 */
1197 void
1198 i386_exception(
1199 int exc,
1200 mach_exception_code_t code,
1201 mach_exception_subcode_t subcode)
1202 {
1203 mach_exception_data_type_t codes[EXCEPTION_CODE_MAX];
1204
1205 DEBUG_KPRINT_SYSCALL_MACH("i386_exception: exc=%d code=0x%llx subcode=0x%llx\n",
1206 exc, code, subcode);
1207 codes[0] = code; /* new exception interface */
1208 codes[1] = subcode;
1209 exception_triage(exc, codes, 2);
1210 /*NOTREACHED*/
1211 }
1212
1213
1214 /* Synchronize a thread's i386_kernel_state (if any) with the given
1215 * i386_saved_state_t obtained from the trap/IPI handler; called in
1216 * kernel_trap() prior to entering the debugger, and when receiving
1217 * an "MP_KDP" IPI.
1218 */
1219
1220 void
1221 sync_iss_to_iks(x86_saved_state_t *saved_state)
1222 {
1223 struct x86_kernel_state *iks;
1224 vm_offset_t kstack;
1225 boolean_t record_active_regs = FALSE;
1226
1227 /* The PAL may have a special way to sync registers */
1228 if( saved_state->flavor == THREAD_STATE_NONE )
1229 pal_get_kern_regs( saved_state );
1230
1231 if ((kstack = current_thread()->kernel_stack) != 0) {
1232 #ifdef __i386__
1233 x86_saved_state32_t *regs = saved_state32(saved_state);
1234 #else
1235 x86_saved_state64_t *regs = saved_state64(saved_state);
1236 #endif
1237
1238 iks = STACK_IKS(kstack);
1239
1240 /* Did we take the trap/interrupt in kernel mode? */
1241 #ifdef __i386__
1242 if (regs == USER_REGS32(current_thread()))
1243 record_active_regs = TRUE;
1244 else {
1245 iks->k_ebx = regs->ebx;
1246 iks->k_esp = (int)regs;
1247 iks->k_ebp = regs->ebp;
1248 iks->k_edi = regs->edi;
1249 iks->k_esi = regs->esi;
1250 iks->k_eip = regs->eip;
1251 }
1252 #else
1253 if (regs == USER_REGS64(current_thread()))
1254 record_active_regs = TRUE;
1255 else {
1256 iks->k_rbx = regs->rbx;
1257 iks->k_rsp = regs->isf.rsp;
1258 iks->k_rbp = regs->rbp;
1259 iks->k_r12 = regs->r12;
1260 iks->k_r13 = regs->r13;
1261 iks->k_r14 = regs->r14;
1262 iks->k_r15 = regs->r15;
1263 iks->k_rip = regs->isf.rip;
1264 }
1265 #endif
1266 }
1267
1268 if (record_active_regs == TRUE) {
1269 #ifdef __i386__
1270 /* Show the trap handler path */
1271 __asm__ volatile("movl %%ebx, %0" : "=m" (iks->k_ebx));
1272 __asm__ volatile("movl %%esp, %0" : "=m" (iks->k_esp));
1273 __asm__ volatile("movl %%ebp, %0" : "=m" (iks->k_ebp));
1274 __asm__ volatile("movl %%edi, %0" : "=m" (iks->k_edi));
1275 __asm__ volatile("movl %%esi, %0" : "=m" (iks->k_esi));
1276 /* "Current" instruction pointer */
1277 __asm__ volatile("movl $1f, %0\n1:" : "=m" (iks->k_eip));
1278 #else
1279 /* Show the trap handler path */
1280 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1281 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1282 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1283 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1284 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1285 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1286 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1287 /* "Current" instruction pointer */
1288 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
1289 : "=m" (iks->k_rip)
1290 :
1291 : "rax");
1292 #endif
1293 }
1294 }
1295
1296 /*
1297 * This is used by the NMI interrupt handler (from mp.c) to
1298 * uncondtionally sync the trap handler context to the IKS
1299 * irrespective of whether the NMI was fielded in kernel
1300 * or user space.
1301 */
1302 void
1303 sync_iss_to_iks_unconditionally(__unused x86_saved_state_t *saved_state) {
1304 struct x86_kernel_state *iks;
1305 vm_offset_t kstack;
1306
1307 if ((kstack = current_thread()->kernel_stack) != 0) {
1308 iks = STACK_IKS(kstack);
1309 #ifdef __i386__
1310 /* Display the trap handler path */
1311 __asm__ volatile("movl %%ebx, %0" : "=m" (iks->k_ebx));
1312 __asm__ volatile("movl %%esp, %0" : "=m" (iks->k_esp));
1313 __asm__ volatile("movl %%ebp, %0" : "=m" (iks->k_ebp));
1314 __asm__ volatile("movl %%edi, %0" : "=m" (iks->k_edi));
1315 __asm__ volatile("movl %%esi, %0" : "=m" (iks->k_esi));
1316 /* "Current" instruction pointer */
1317 __asm__ volatile("movl $1f, %0\n1:" : "=m" (iks->k_eip));
1318 #else
1319 /* Display the trap handler path */
1320 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1321 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1322 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1323 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1324 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1325 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1326 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1327 /* "Current" instruction pointer */
1328 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:" : "=m" (iks->k_rip)::"rax");
1329 #endif
1330 }
1331 }
mirror of XNU