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1 /*
2 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23 /*
24 * @OSF_COPYRIGHT@
25 */
26 /* CMU_ENDHIST */
27 /*
28 * Mach Operating System
29 * Copyright (c) 1991,1990 Carnegie Mellon University
30 * All Rights Reserved.
31 *
32 * Permission to use, copy, modify and distribute this software and its
33 * documentation is hereby granted, provided that both the copyright
34 * notice and this permission notice appear in all copies of the
35 * software, derivative works or modified versions, and any portions
36 * thereof, and that both notices appear in supporting documentation.
37 *
38 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
39 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
40 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
41 *
42 * Carnegie Mellon requests users of this software to return to
43 *
44 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
45 * School of Computer Science
46 * Carnegie Mellon University
47 * Pittsburgh PA 15213-3890
48 *
49 * any improvements or extensions that they make and grant Carnegie Mellon
50 * the rights to redistribute these changes.
51 */
52
53 /*
54 */
55
56 /*
57 * Processor registers for i386 and i486.
58 */
59 #ifndef _I386_PROC_REG_H_
60 #define _I386_PROC_REG_H_
61
62 /*
63 * Model Specific Registers
64 */
65 #define MSR_P5_TSC 0x10 /* Time Stamp Register */
66 #define MSR_P5_CESR 0x11 /* Control and Event Select Register */
67 #define MSR_P5_CTR0 0x12 /* Counter #0 */
68 #define MSR_P5_CTR1 0x13 /* Counter #1 */
69
70 #define MSR_P5_CESR_PC 0x0200 /* Pin Control */
71 #define MSR_P5_CESR_CC 0x01C0 /* Counter Control mask */
72 #define MSR_P5_CESR_ES 0x003F /* Event Control mask */
73
74 #define MSR_P5_CESR_SHIFT 16 /* Shift to get Counter 1 */
75 #define MSR_P5_CESR_MASK (MSR_P5_CESR_PC|\
76 MSR_P5_CESR_CC|\
77 MSR_P5_CESR_ES) /* Mask Counter */
78
79 #define MSR_P5_CESR_CC_CLOCK 0x0100 /* Clock Counting (otherwise Event) */
80 #define MSR_P5_CESR_CC_DISABLE 0x0000 /* Disable counter */
81 #define MSR_P5_CESR_CC_CPL012 0x0040 /* Count if the CPL == 0, 1, 2 */
82 #define MSR_P5_CESR_CC_CPL3 0x0080 /* Count if the CPL == 3 */
83 #define MSR_P5_CESR_CC_CPL 0x00C0 /* Count regardless of the CPL */
84
85 #define MSR_P5_CESR_ES_DATA_READ 0x000000 /* Data Read */
86 #define MSR_P5_CESR_ES_DATA_WRITE 0x000001 /* Data Write */
87 #define MSR_P5_CESR_ES_DATA_RW 0x101000 /* Data Read or Write */
88 #define MSR_P5_CESR_ES_DATA_TLB_MISS 0x000010 /* Data TLB Miss */
89 #define MSR_P5_CESR_ES_DATA_READ_MISS 0x000011 /* Data Read Miss */
90 #define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100 /* Data Write Miss */
91 #define MSR_P5_CESR_ES_DATA_RW_MISS 0x101001 /* Data Read or Write Miss */
92 #define MSR_P5_CESR_ES_HIT_EM 0x000101 /* Write (hit) to M|E state */
93 #define MSR_P5_CESR_ES_DATA_CACHE_WB 0x000110 /* Cache lines written back */
94 #define MSR_P5_CESR_ES_EXTERNAL_SNOOP 0x000111 /* External Snoop */
95 #define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000 /* Data cache snoop hits */
96 #define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001 /* Mem. access in both pipes */
97 #define MSR_P5_CESR_ES_BANK_CONFLICTS 0x001010 /* Bank conflicts */
98 #define MSR_P5_CESR_ES_MISALIGNED 0x001011 /* Misaligned Memory or I/O */
99 #define MSR_P5_CESR_ES_CODE_READ 0x001100 /* Code Read */
100 #define MSR_P5_CESR_ES_CODE_TLB_MISS 0x001101 /* Code TLB miss */
101 #define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110 /* Code Cache miss */
102 #define MSR_P5_CESR_ES_SEGMENT_LOADED 0x001111 /* Any segment reg. loaded */
103 #define MSR_P5_CESR_ES_BRANCHE 0x010010 /* Branches */
104 #define MSR_P5_CESR_ES_BTB_HIT 0x010011 /* BTB Hits */
105 #define MSR_P5_CESR_ES_BRANCHE_BTB 0x010100 /* Taken branch or BTB Hit */
106 #define MSR_P5_CESR_ES_PIPELINE_FLUSH 0x010101 /* Pipeline Flushes */
107 #define MSR_P5_CESR_ES_INSTRUCTION 0x010110 /* Instruction executed */
108 #define MSR_P5_CESR_ES_INSTRUCTION_V 0x010111 /* Inst. executed (v-pipe) */
109 #define MSR_P5_CESR_ES_BUS_CYCLE 0x011000 /* Clocks while bus cycle */
110 #define MSR_P5_CESR_ES_FULL_WRITE_BUF 0x011001 /* Clocks while full wrt buf. */
111 #define MSR_P5_CESR_ES_DATA_MEM_READ 0x011010 /* Pipeline waiting for read */
112 #define MSR_P5_CESR_ES_WRITE_EM 0x011011 /* Stall on write E|M state */
113 #define MSR_P5_CESR_ES_LOCKED_CYCLE 0x011100 /* Locked bus cycles */
114 #define MSR_P5_CESR_ES_IO_CYCLE 0x011101 /* I/O Read or Write cycles */
115 #define MSR_P5_CESR_ES_NON_CACHEABLE 0x011110 /* Non-cacheable Mem. read */
116 #define MSR_P5_CESR_ES_AGI 0x011111 /* Stall because of AGI */
117 #define MSR_P5_CESR_ES_FLOP 0x100010 /* Floating Point operations */
118 #define MSR_P5_CESR_ES_BREAK_DR0 0x100011 /* Breakpoint matches on DR0 */
119 #define MSR_P5_CESR_ES_BREAK_DR1 0x100100 /* Breakpoint matches on DR1 */
120 #define MSR_P5_CESR_ES_BREAK_DR2 0x100101 /* Breakpoint matches on DR2 */
121 #define MSR_P5_CESR_ES_BREAK_DR3 0x100110 /* Breakpoint matches on DR3 */
122 #define MSR_P5_CESR_ES_HARDWARE_IT 0x100111 /* Hardware interrupts */
123
124 /*
125 * CR0
126 */
127 #define CR0_PG 0x80000000 /* Enable paging */
128 #define CR0_CD 0x40000000 /* i486: Cache disable */
129 #define CR0_NW 0x20000000 /* i486: No write-through */
130 #define CR0_AM 0x00040000 /* i486: Alignment check mask */
131 #define CR0_WP 0x00010000 /* i486: Write-protect kernel access */
132 #define CR0_NE 0x00000020 /* i486: Handle numeric exceptions */
133 #define CR0_ET 0x00000010 /* Extension type is 80387 */
134 /* (not official) */
135 #define CR0_TS 0x00000008 /* Task switch */
136 #define CR0_EM 0x00000004 /* Emulate coprocessor */
137 #define CR0_MP 0x00000002 /* Monitor coprocessor */
138 #define CR0_PE 0x00000001 /* Enable protected mode */
139
140 /*
141 * CR4
142 */
143 #define CR4_FXS 0x00000200 /* SSE/SSE2 OS supports FXSave */
144 #define CR4_XMM 0x00000400 /* SSE/SSE2 instructions supported in OS */
145 #define CR4_PGE 0x00000080 /* p6: Page Global Enable */
146 #define CR4_MCE 0x00000040 /* p5: Machine Check Exceptions */
147 #define CR4_PAE 0x00000020 /* p5: Physical Address Extensions */
148 #define CR4_PSE 0x00000010 /* p5: Page Size Extensions */
149 #define CR4_DE 0x00000008 /* p5: Debugging Extensions */
150 #define CR4_TSD 0x00000004 /* p5: Time Stamp Disable */
151 #define CR4_PVI 0x00000002 /* p5: Protected-mode Virtual Interrupts */
152 #define CR4_VME 0x00000001 /* p5: Virtual-8086 Mode Extensions */
153
154 #ifndef ASSEMBLER
155
156 #include <sys/cdefs.h>
157 __BEGIN_DECLS
158
159 #define set_ts() \
160 set_cr0(get_cr0() | CR0_TS)
161
162 static inline unsigned int get_cr0(void)
163 {
164 register unsigned int cr0;
165 __asm__ volatile("mov %%cr0, %0" : "=r" (cr0));
166 return(cr0);
167 }
168
169 static inline void set_cr0(unsigned int value)
170 {
171 __asm__ volatile("mov %0, %%cr0" : : "r" (value));
172 }
173
174 static inline unsigned int get_cr2(void)
175 {
176 register unsigned int cr2;
177 __asm__ volatile("mov %%cr2, %0" : "=r" (cr2));
178 return(cr2);
179 }
180
181 static inline unsigned int get_cr3(void)
182 {
183 register unsigned int cr3;
184 __asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
185 return(cr3);
186 }
187
188 static inline void set_cr3(unsigned int value)
189 {
190 __asm__ volatile("mov %0, %%cr3" : : "r" (value));
191 }
192
193 /* Implemented in locore: */
194 extern uint32_t get_cr4(void);
195 extern void set_cr4(uint32_t);
196
197 static inline void clear_ts(void)
198 {
199 __asm__ volatile("clts");
200 }
201
202 static inline unsigned short get_tr(void)
203 {
204 unsigned short seg;
205 __asm__ volatile("str %0" : "=rm" (seg));
206 return(seg);
207 }
208
209 static inline void set_tr(unsigned int seg)
210 {
211 __asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg)));
212 }
213
214 static inline unsigned short get_ldt(void)
215 {
216 unsigned short seg;
217 __asm__ volatile("sldt %0" : "=rm" (seg));
218 return(seg);
219 }
220
221 static inline void set_ldt(unsigned int seg)
222 {
223 __asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg)));
224 }
225
226 static inline void flush_tlb(void)
227 {
228 unsigned long cr3_temp;
229 __asm__ volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (cr3_temp) :: "memory");
230 }
231
232 static inline void wbinvd(void)
233 {
234 __asm__ volatile("wbinvd");
235 }
236
237 static inline void invlpg(unsigned long addr)
238 {
239 __asm__ volatile("invlpg (%0)" :: "r" (addr) : "memory");
240 }
241
242 /*
243 * Access to machine-specific registers (available on 586 and better only)
244 * Note: the rd* operations modify the parameters directly (without using
245 * pointer indirection), this allows gcc to optimize better
246 */
247
248 #define rdmsr(msr,lo,hi) \
249 __asm__ volatile("rdmsr" : "=a" (lo), "=d" (hi) : "c" (msr))
250
251 #define wrmsr(msr,lo,hi) \
252 __asm__ volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi))
253
254 #define rdtsc(lo,hi) \
255 __asm__ volatile("rdtsc" : "=a" (lo), "=d" (hi))
256
257 #define write_tsc(lo,hi) wrmsr(0x10, lo, hi)
258
259 #define rdpmc(counter,lo,hi) \
260 __asm__ volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (counter))
261
262 static inline uint64_t rdmsr64(uint32_t msr)
263 {
264 uint64_t ret;
265 __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));
266 return ret;
267 }
268
269 static inline void wrmsr64(uint32_t msr, uint64_t val)
270 {
271 __asm__ volatile("wrmsr" : : "c" (msr), "A" (val));
272 }
273
274 static inline uint64_t rdtsc64(void)
275 {
276 uint64_t ret;
277 __asm__ volatile("rdtsc" : "=A" (ret));
278 return ret;
279 }
280
281 /*
282 * rdmsr_carefully() returns 0 when the MSR has been read successfully,
283 * or non-zero (1) if the MSR does not exist.
284 * The implementation is in locore.s.
285 */
286 extern int rdmsr_carefully(uint32_t msr, uint32_t *lo, uint32_t *hi);
287
288 __END_DECLS
289
290 #endif /* ASSEMBLER */
291
292 #define MSR_IA32_P5_MC_ADDR 0
293 #define MSR_IA32_P5_MC_TYPE 1
294 #define MSR_IA32_PLATFORM_ID 0x17
295 #define MSR_IA32_EBL_CR_POWERON 0x2a
296
297 #define MSR_IA32_APIC_BASE 0x1b
298 #define MSR_IA32_APIC_BASE_BSP (1<<8)
299 #define MSR_IA32_APIC_BASE_ENABLE (1<<11)
300 #define MSR_IA32_APIC_BASE_BASE (0xfffff<<12)
301
302 #define MSR_IA32_UCODE_WRITE 0x79
303 #define MSR_IA32_UCODE_REV 0x8b
304
305 #define MSR_IA32_PERFCTR0 0xc1
306 #define MSR_IA32_PERFCTR1 0xc2
307
308 #define MSR_IA32_BBL_CR_CTL 0x119
309
310 #define MSR_IA32_MCG_CAP 0x179
311 #define MSR_IA32_MCG_STATUS 0x17a
312 #define MSR_IA32_MCG_CTL 0x17b
313
314 #define MSR_IA32_EVNTSEL0 0x186
315 #define MSR_IA32_EVNTSEL1 0x187
316
317 #define MSR_IA32_MISC_ENABLE 0x1a0
318
319 #define MSR_IA32_DEBUGCTLMSR 0x1d9
320 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
321 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
322 #define MSR_IA32_LASTINTFROMIP 0x1dd
323 #define MSR_IA32_LASTINTTOIP 0x1de
324
325 #define MSR_IA32_CR_PAT 0x277
326
327 #define MSR_IA32_MC0_CTL 0x400
328 #define MSR_IA32_MC0_STATUS 0x401
329 #define MSR_IA32_MC0_ADDR 0x402
330 #define MSR_IA32_MC0_MISC 0x403
331
332 #define MSR_IA32_MTRRCAP 0xfe
333 #define MSR_IA32_MTRR_DEF_TYPE 0x2ff
334 #define MSR_IA32_MTRR_PHYSBASE(n) (0x200 + 2*(n))
335 #define MSR_IA32_MTRR_PHYSMASK(n) (0x200 + 2*(n) + 1)
336 #define MSR_IA32_MTRR_FIX64K_00000 0x250
337 #define MSR_IA32_MTRR_FIX16K_80000 0x258
338 #define MSR_IA32_MTRR_FIX16K_A0000 0x259
339 #define MSR_IA32_MTRR_FIX4K_C0000 0x268
340 #define MSR_IA32_MTRR_FIX4K_C8000 0x269
341 #define MSR_IA32_MTRR_FIX4K_D0000 0x26a
342 #define MSR_IA32_MTRR_FIX4K_D8000 0x26b
343 #define MSR_IA32_MTRR_FIX4K_E0000 0x26c
344 #define MSR_IA32_MTRR_FIX4K_E8000 0x26d
345 #define MSR_IA32_MTRR_FIX4K_F0000 0x26e
346 #define MSR_IA32_MTRR_FIX4K_F8000 0x26f
347
348 #endif /* _I386_PROC_REG_H_ */