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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_FREE_COPYRIGHT@
24 */
25 /*
26 * @APPLE_FREE_COPYRIGHT@
27 */
28
29 /*
30 Firmware.s
31
32 Handle things that should be treated as an extension of the hardware
33
34 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials.
35 No animal products are used other than rendered otter bile and deep fried pork lard.
36
37 */
38
39 #include <cpus.h>
40 #include <ppc/asm.h>
41 #include <ppc/proc_reg.h>
42 #include <ppc/spec_reg.h>
43 #include <ppc/exception.h>
44 #include <mach/machine/vm_param.h>
45 #include <assym.s>
46
47
48 /*
49 * Here we generate the table of supported firmware calls
50 */
51
52
53
54 .data
55 .align 5 /* Line up on cache line */
56
57 .globl EXT(FWtable)
58
59 EXT(FWtable):
60
61 .globl CutTrace /* Let everyone know 'bout it */
62 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */
63 .long callUnimp /* This was already handled in lowmem_vectors */
64
65 #include <ppc/FirmwareCalls.h>
66
67 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */
68
69 .text
70
71 #define SIMPLESCC 1
72 #define NOTQUITEASSIMPLE 1
73 /*
74 * This routine handles the firmware call routine. It must be entered with IR and DR off,
75 * interruptions disabled, and in supervisor state.
76 *
77 * When we enter, we expect R0 to have call number, and LR
78 * to point to the return. Also, all registers saved in savearea in R13.
79 * R3 is as passed in by the user. All others must be gotten from the save area
80 */
81
82
83 .align 5
84 .globl EXT(FirmwareCall)
85
86 LEXT(FirmwareCall)
87
88 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
89 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */
90 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */
91 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */
92 ble+ goodCall /* Yeah, it is... */
93
94 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
95 b EXT(FCReturn) ; Bye dudes...
96
97 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */
98 lwzx r1,r1,r12 /* Pick up the address of the routine */
99 lwz r4,saver4+4(r13) /* Pass in caller's R4 */
100 lwz r5,saver5+4(r13) /* Pass in caller's R5 */
101 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */
102
103 mtlr r1 /* Put it in the LR */
104 beq- callUnimp /* This one was unimplimented... */
105
106 blrl /* Call the routine... */
107
108 stw r3,saver3+4(r13) /* Pass back the return code to caller */
109 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
110 b EXT(FCReturn) ; Bye dudes...
111
112 callUnimp: li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
113 b EXT(FCReturn) ; Bye dudes...
114
115 /*
116 * This routine is used to store using a real address. It stores parmeter1 at parameter2.
117 */
118
119 .align 5
120 .globl EXT(StoreReal)
121
122 LEXT(StoreReal)
123
124 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */
125 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */
126 sc /* Do it to it */
127 blr /* Bye bye, Birdie... */
128
129 .align 5
130 .globl EXT(StoreRealLL)
131
132 LEXT(StoreRealLL)
133
134 stw r3,0(r4) /* Store the word */
135 blr /* Leave... */
136
137 /*
138 * This routine is used to clear a range of physical pages.
139 */
140
141 .align 5
142 .globl EXT(ClearReal)
143
144 LEXT(ClearReal)
145
146 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */
147 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */
148 sc /* Do it to it */
149 blr /* Bye bye, Birdie... */
150
151
152 .align 5
153 .globl EXT(ClearRealLL)
154
155 LEXT(ClearRealLL)
156
157 /*
158 * We take the first parameter as a physical address. The second is the length in bytes.
159 * Being crazy, I'll round the address down, and the length up. We could end up clearing
160 * an extra page at the start and one at the end, but we don't really care. If someone
161 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough
162 * to take them at their word and to hell with them.
163 */
164
165 neg r5,r3 /* Negate the address */
166 addi r4,r4,4095 /* Round length up */
167 rlwinm r5,r5,0,20,31 /* Save extra length */
168 rlwinm r3,r3,0,0,19 /* Round the page on down */
169 add r4,r4,r5 /* Add up all extra lengths */
170 li r6,32 /* Get a displacement */
171 rlwinm r4,r4,0,0,19 /* Round the length back down */
172
173 clrloop: subi r4,r4,32 /* Back off a cache line */
174 dcbz 0,r3 /* Do the even line */
175 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */
176 dcbz r6,r3 /* Clear the even line */
177 addi r3,r3,64 /* Move up to every other line */
178 bgt+ clrloop /* Go until we've done it all... */
179
180 blr /* Leave... */
181 /*
182 * This routine will read in 32 byte of real storage.
183 */
184
185 .align 5
186 .globl EXT(ReadReal)
187
188 LEXT(ReadReal)
189
190 mfsprg r9,2 ; Get the features
191 mfmsr r0 ; Get the MSR
192 li r8,lo16(MASK(MSR_DR)) ; Get the DR bit
193 rlwinm. r9,r9,0,pf64Bitb,pf64Bitb ; Are we 64-bit?
194 ori r8,r8,lo16(MASK(MSR_EE)) ; Add in the EE bit
195 li r7,1 ; Get set for it
196 andc r8,r0,r8 ; Turn off EE and DR
197 bt-- cr0_eq,rr32a ; Yes, we are...
198
199 rldimi r8,r7,63,MSR_SF_BIT ; Set SF bit (bit 0)
200 sldi r3,r3,32 ; Slide on over for true 64-bit address
201 mtmsrd r8
202 isync
203 or r3,r3,r4 ; Join top and bottom of address
204 mr r4,r5 ; Set destination address
205 b rrJoina ; Join on up...
206
207 rr32a: mr r3,r4 ; Position bottom of long long
208 mr r4,r5 ; Set destination address
209 mtmsr r8 /* Disable EE and DR */
210 isync /* Just make sure about it */
211
212 rrJoina: lwz r5,0(r3) /* Get word 0 */
213 lwz r6,4(r3) /* Get word 1 */
214 lwz r7,8(r3) /* Get word 2 */
215 lwz r8,12(r3) /* Get word 3 */
216 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
217 lwz r9,16(r3) /* Get word 4 */
218 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
219 lwz r10,20(r3) /* Get word 5 */
220 andc r0,r0,r2 ; Clear VEC and FP enables
221 lwz r11,24(r3) /* Get word 6 */
222 lwz r12,28(r3) /* Get word 7 */
223
224 bt-- cr0_eq,rr32b ; We are not 64-bit...
225
226 mtmsrd r0
227 isync
228 b rrJoinb ; Join on up...
229
230 rr32b: mtmsr r0 /* Restore original machine state */
231 isync /* Insure goodness */
232
233 rrJoinb: stw r5,0(r4) /* Set word 0 */
234 stw r6,4(r4) /* Set word 1 */
235 stw r7,8(r4) /* Set word 2 */
236 stw r8,12(r4) /* Set word 3 */
237 stw r9,16(r4) /* Set word 4 */
238 stw r10,20(r4) /* Set word 5 */
239 stw r11,24(r4) /* Set word 6 */
240 stw r12,28(r4) /* Set word 7 */
241
242 blr
243
244
245 /*
246 * This routine is used to load all 4 DBATs.
247 */
248
249 .align 5
250 .globl EXT(LoadDBATs)
251
252 LEXT(LoadDBATs)
253
254
255 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */
256 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */
257 sc /* Do it to it */
258
259 blr /* Bye bye, Birdie... */
260
261
262 .align 5
263 .globl EXT(xLoadDBATsLL)
264
265 LEXT(xLoadDBATsLL)
266
267 lwz r4,0(r3) /* Get DBAT 0 high */
268 lwz r5,4(r3) /* Get DBAT 0 low */
269 lwz r6,8(r3) /* Get DBAT 1 high */
270 lwz r7,12(r3) /* Get DBAT 1 low */
271 lwz r8,16(r3) /* Get DBAT 2 high */
272 lwz r9,20(r3) /* Get DBAT 2 low */
273 lwz r10,24(r3) /* Get DBAT 3 high */
274 lwz r11,28(r3) /* Get DBAT 3 low */
275
276 sync /* Common decency and the state law require that you wash your hands */
277 mtdbatu 0,r4 /* Load DBAT 0 high */
278 mtdbatl 0,r5 /* Load DBAT 0 low */
279 mtdbatu 1,r6 /* Load DBAT 1 high */
280 mtdbatl 1,r7 /* Load DBAT 1 low */
281 mtdbatu 2,r8 /* Load DBAT 2 high */
282 mtdbatl 2,r9 /* Load DBAT 2 low */
283 mtdbatu 3,r10 /* Load DBAT 3 high */
284 mtdbatl 3,r11 /* Load DBAT 3 low */
285 sync /* Make sure it's done */
286 isync /* Toss out anything new */
287
288 blr /* Leave... */
289
290 /*
291 * This routine is used to load all 4 IBATs.
292 */
293
294 .align 5
295 .globl EXT(LoadIBATs)
296
297 LEXT(LoadIBATs)
298
299
300 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of LoadIBATsCall firmware call number */
301 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
302 sc /* Do it to it */
303 blr /* Bye bye, Birdie... */
304
305 .align 5
306 .globl EXT(xLoadIBATsLL)
307
308 LEXT(xLoadIBATsLL)
309
310 lwz r4,0(r3) /* Get IBAT 0 high */
311 lwz r5,4(r3) /* Get IBAT 0 low */
312 lwz r6,8(r3) /* Get IBAT 1 high */
313 lwz r7,12(r3) /* Get IBAT 1 low */
314 lwz r8,16(r3) /* Get IBAT 2 high */
315 lwz r9,20(r3) /* Get IBAT 2 low */
316 lwz r10,24(r3) /* Get IBAT 3 high */
317 lwz r11,28(r3) /* Get IBAT 3 low */
318
319 sync /* Common decency and the state law require that you wash your hands */
320 mtibatu 0,r4 /* Load IBAT 0 high */
321 mtibatl 0,r5 /* Load IBAT 0 low */
322 mtibatu 1,r6 /* Load IBAT 1 high */
323 mtibatl 1,r7 /* Load IBAT 1 low */
324 mtibatu 2,r8 /* Load IBAT 2 high */
325 mtibatl 2,r9 /* Load IBAT 2 low */
326 mtibatu 3,r10 /* Load IBAT 3 high */
327 mtibatl 3,r11 /* Load IBAT 3 low */
328 sync /* Make sure it's done */
329 isync /* Toss out anything new */
330
331 blr /* Leave... */
332
333
334 /*
335 * This is the glue to call the CutTrace firmware call
336 */
337
338 .align 5
339 .globl EXT(dbgTrace)
340
341 LEXT(dbgTrace)
342
343 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */
344 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */
345 sc /* Do it to it */
346 blr /* Bye bye, Birdie... */
347
348 /*
349 * This is the glue to create a fake I/O interruption
350 */
351
352 .align 5
353 .globl EXT(CreateFakeIO)
354
355 LEXT(CreateFakeIO)
356
357 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */
358 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */
359 sc /* Do it to it */
360 blr /* Bye bye, Birdie... */
361
362 /*
363 * This is the glue to create a fake Dec interruption
364 */
365
366 .align 5
367 .globl EXT(CreateFakeDEC)
368
369 LEXT(CreateFakeDEC)
370
371 #if 0
372 mflr r4 ; (TEST/DEBUG)
373 bl EXT(ml_sense_nmi) ; (TEST/DEBUG)
374 mtlr r4 ; (TEST/DEBUG)
375 #endif
376
377 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
378 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
379 sc /* Do it to it */
380 blr /* Bye bye, Birdie... */
381
382
383 /*
384 * This is the glue to create a shutdown context
385 */
386
387 .align 5
388 .globl EXT(CreateShutdownCTX)
389
390 LEXT(CreateShutdownCTX)
391
392 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */
393 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */
394 sc /* Do it to it */
395 blr /* Bye bye, Birdie... */
396
397 /*
398 * This is the glue to choke system
399 */
400
401 .align 5
402 .globl EXT(ChokeSys)
403
404 LEXT(ChokeSys)
405
406 lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */
407 ori r0,r0,LOW_ADDR(Choke) /* Bottom half */
408 sc /* Do it to it */
409 blr /* Bye bye, Birdie... */
410
411 /*
412 * Used to initialize the SCC for debugging output
413 */
414
415
416 .align 5
417 .globl EXT(fwSCCinit)
418
419 LEXT(fwSCCinit)
420
421 mfmsr r8 /* Save the MSR */
422 mr. r3,r3 /* See if printer or modem */
423 rlwinm r12,r8,0,28,25 /* Turn off translation */
424 lis r10,0xF301 /* Set the top part */
425 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
426 #if 0
427 mtmsr r12 /* Smash the MSR */
428 isync /* Make it clean */
429 #endif
430
431 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
432 beq+ fwSCCprnt /* It sure are... */
433 ori r10,r10,0x0002 /* Move it over to the modem port */
434
435 fwSCCprnt: dcbf 0,r10 /* Insure it is out */
436 sync
437 eieio
438 dcbi 0,r10 /* Toss it */
439 sync
440
441
442 li r7,0x09 /* Set the register */
443 stb r7,0(r10) /* Set the register */
444 dcbf 0,r10 /* Force it out */
445 sync /* Make sure it's out there */
446 dcbi 0,r10
447 eieio
448
449 li r7,0x80 /* Reset channel A */
450 stb r7,0(r10) /* Set the register */
451 dcbf 0,r10 /* Force it out */
452 sync /* Make sure it's out there */
453 dcbi 0,r10
454 eieio
455
456 li r7,0x04 /* Set the register */
457 stb r7,0(r10) /* Set the register */
458 dcbf 0,r10 /* Force it out */
459 sync /* Make sure it's out there */
460 dcbi 0,r10
461 eieio
462
463 li r7,0x44 /* x16 clock, 1 stop bit */
464 stb r7,0(r10) /* Set the register */
465 dcbf 0,r10 /* Force it out */
466 sync /* Make sure it's out there */
467 dcbi 0,r10
468 eieio
469
470 li r7,0x03 /* Set the register */
471 stb r7,0(r10) /* Set the register */
472 dcbf 0,r10 /* Force it out */
473 sync /* Make sure it's out there */
474 dcbi 0,r10
475 eieio
476
477 li r7,0xC0 /* 8 bits per char */
478 stb r7,0(r10) /* Set the register */
479 dcbf 0,r10 /* Force it out */
480 sync /* Make sure it's out there */
481 dcbi 0,r10
482 eieio
483
484 li r7,0x05 /* Set the register */
485 stb r7,0(r10) /* Set the register */
486 dcbf 0,r10 /* Force it out */
487 sync /* Make sure it's out there */
488 dcbi 0,r10
489 eieio
490
491 li r7,0xE2 /* DTR mode, 8bit/char */
492 stb r7,0(r10) /* Set the register */
493 dcbf 0,r10 /* Force it out */
494 sync /* Make sure it's out there */
495 dcbi 0,r10
496 eieio
497
498 li r7,0x02 /* Set the register */
499 stb r7,0(r10) /* Set the register */
500 dcbf 0,r10 /* Force it out */
501 sync /* Make sure it's out there */
502 dcbi 0,r10
503 eieio
504
505 li r7,0x00 /* Vector 0 */
506 stb r7,0(r10) /* Set the register */
507 dcbf 0,r10 /* Force it out */
508 sync /* Make sure it's out there */
509 dcbi 0,r10
510 eieio
511
512 li r7,0x0A /* Set the register */
513 stb r7,0(r10) /* Set the register */
514 dcbf 0,r10 /* Force it out */
515 sync /* Make sure it's out there */
516 dcbi 0,r10
517 eieio
518
519 li r7,0x00 /* Clear misc controls */
520 stb r7,0(r10) /* Set the register */
521 dcbf 0,r10 /* Force it out */
522 sync /* Make sure it's out there */
523 dcbi 0,r10
524 eieio
525
526 li r7,0x0B /* Set the register */
527 stb r7,0(r10) /* Set the register */
528 dcbf 0,r10 /* Force it out */
529 sync /* Make sure it's out there */
530 dcbi 0,r10
531 eieio
532
533 li r7,0x50 /* B/R gen T/R */
534 stb r7,0(r10) /* Set the register */
535 dcbf 0,r10 /* Force it out */
536 sync /* Make sure it's out there */
537 dcbi 0,r10
538 eieio
539
540 li r7,0x0C /* Set the register */
541 stb r7,0(r10) /* Set the register */
542 dcbf 0,r10 /* Force it out */
543 sync /* Make sure it's out there */
544 dcbi 0,r10
545 eieio
546
547 li r7,0x0A /* 9600 baud low */
548 stb r7,0(r10) /* Set the register */
549 dcbf 0,r10 /* Force it out */
550 sync /* Make sure it's out there */
551 dcbi 0,r10
552 eieio
553
554 li r7,0x0D /* Set the register */
555 stb r7,0(r10) /* Set the register */
556 dcbf 0,r10 /* Force it out */
557 sync /* Make sure it's out there */
558 dcbi 0,r10
559 eieio
560
561 li r7,0x00 /* 9600 baud high */
562 stb r7,0(r10) /* Set the register */
563 dcbf 0,r10 /* Force it out */
564 sync /* Make sure it's out there */
565 dcbi 0,r10
566 eieio
567
568 li r7,0x03 /* Set the register */
569 stb r7,0(r10) /* Set the register */
570 dcbf 0,r10 /* Force it out */
571 sync /* Make sure it's out there */
572 dcbi 0,r10
573 eieio
574
575 li r7,0xC1 /* 8 bits/char, Rx enable */
576 stb r7,0(r10) /* Set the register */
577 dcbf 0,r10 /* Force it out */
578 sync /* Make sure it's out there */
579 dcbi 0,r10
580 eieio
581
582 li r7,0x05 /* Set the register */
583 stb r7,0(r10) /* Set the register */
584 dcbf 0,r10 /* Force it out */
585 sync /* Make sure it's out there */
586 dcbi 0,r10
587 eieio
588
589 li r7,0xEA /* 8 bits/char, Tx enable */
590 stb r7,0(r10) /* Set the register */
591 dcbf 0,r10 /* Force it out */
592 sync /* Make sure it's out there */
593 dcbi 0,r10
594 eieio
595
596 li r7,0x0E /* Set the register */
597 stb r7,0(r10) /* Set the register */
598 dcbf 0,r10 /* Force it out */
599 sync /* Make sure it's out there */
600 dcbi 0,r10
601 eieio
602
603 li r7,0x01 /* BR rate gen enable */
604 stb r7,0(r10) /* Set the register */
605 dcbf 0,r10 /* Force it out */
606 sync /* Make sure it's out there */
607 dcbi 0,r10
608 eieio
609
610 li r7,0x0F /* Set the register */
611 stb r7,0(r10) /* Set the register */
612 dcbf 0,r10 /* Force it out */
613 sync /* Make sure it's out there */
614 dcbi 0,r10
615 eieio
616
617 li r7,0x00 /* ints off */
618 stb r7,0(r10) /* Set the register */
619 dcbf 0,r10 /* Force it out */
620 sync /* Make sure it's out there */
621 dcbi 0,r10
622 eieio
623
624 li r7,0x10 /* Reset ext/stat ints */
625 stb r7,0(r10) /* Set the register */
626 dcbf 0,r10 /* Force it out */
627 sync /* Make sure it's out there */
628 dcbi 0,r10
629 eieio
630
631 li r7,0x10 /* Reset ext/stat ints */
632 stb r7,0(r10) /* Set the register */
633 dcbf 0,r10 /* Force it out */
634 sync /* Make sure it's out there */
635 dcbi 0,r10
636 eieio
637
638 li r7,0x01 /* Set the register */
639 stb r7,0(r10) /* Set the register */
640 dcbf 0,r10 /* Force it out */
641 sync /* Make sure it's out there */
642 dcbi 0,r10
643 eieio
644
645 li r7,0x10 /* int on Rx, no Tx int enable */
646 stb r7,0(r10) /* Set the register */
647 dcbf 0,r10 /* Force it out */
648 sync /* Make sure it's out there */
649 dcbi 0,r10
650 eieio
651
652 li r7,0x09 /* Set the register */
653 stb r7,0(r10) /* Set the register */
654 dcbf 0,r10 /* Force it out */
655 sync /* Make sure it's out there */
656 dcbi 0,r10
657 eieio
658
659 li r7,0x0A /* int on Rx, Tx int enable */
660 stb r7,0(r10) /* Set the register */
661 dcbf 0,r10 /* Force it out */
662 sync /* Master enable, no vector */
663 dcbi 0,r10
664 eieio
665
666 li r7,0x09 /* Set the register */
667 stb r7,0(r10) /* Set the register */
668 dcbf 0,r10 /* Force it out */
669 sync /* Make sure it's out there */
670 dcbi 0,r10
671 eieio
672
673 li r7,0x02 /* No vector */
674 stb r7,0(r10) /* Set the register */
675 dcbf 0,r10 /* Force it out */
676 sync /* Master enable, no vector */
677 dcbi 0,r10
678 eieio
679
680 lbz r7,0(r10) /* Clear interrupts */
681 sync /* Master enable, no vector */
682 dcbi 0,r10
683 eieio
684
685 wSCCrdy: eieio /* Barricade it */
686 lbz r7,0(r10) /* Get current status */
687 dcbi 0,r10
688 sync
689 andi. r7,r7,0x04 /* Is transmitter empty? */
690 beq wSCCrdy /* Nope... */
691
692 eieio
693
694 #if 0
695 mtmsr r8 /* Restore 'rupts and TR */
696 isync
697 #endif
698 blr /* Leave... */
699
700 /*
701 * This routine is used to write debug output to either the modem or printer port.
702 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex
703 */
704
705 .align 5
706 .globl EXT(dbgDisp)
707
708 LEXT(dbgDisp)
709
710 mr r12,r0 /* Keep R0 pristene */
711 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */
712 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */
713
714 sc /* Go display the stuff */
715
716 mr r0,r12 /* Restore R0 */
717 blr /* Return... */
718
719 /* Here's the low-level part of dbgDisp */
720
721 .align 5
722 .globl EXT(dbgDispLL)
723
724 LEXT(dbgDispLL)
725
726 dbgDispInt: mfmsr r8 /* Save the MSR */
727
728 #if 0
729 lis r10,0xF301 /* (TEST/DEBUG) */
730 ori r10,r10,0x2002 /* (TEST/DEBUG) */
731 dcbf 0,r10 /* (TEST/DEBUG) */
732 sync /* (TEST/DEBUG) */
733 dcbi 0,r10 /* (TEST/DEBUG) */
734 eieio /* (TEST/DEBUG) */
735 li r7,0x35 /* (TEST/DEBUG) */
736 stb r7,4(r10) /* (TEST/DEBUG) */
737
738 lis r7,10 /* (TEST/DEBUG) */
739 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
740 mr. r7,r7 /* (TEST/DEBUG) */
741 bne- spw6 /* (TEST/DEBUG) */
742 dcbf 0,r10 /* (TEST/DEBUG) */
743 sync /* (TEST/DEBUG) */
744 dcbi 0,r10 /* (TEST/DEBUG) */
745 eieio /* (TEST/DEBUG) */
746 #endif
747
748 rlwinm r12,r8,0,28,25 /* Turn off translation */
749 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
750
751 mflr r11 /* Save the link register */
752
753 #if 0
754 mr r7,r12 /* (TEST/DEBUG) */
755 bl dumpr7 /* (TEST/DEBUG) */
756 #endif
757
758 mr. r3,r3 /* See if printer or modem */
759 lis r10,0xF301 /* Set the top part */
760 mr r3,r4 /* Copy the ID parameter */
761
762 #if 0
763 mr r9,r12 /* (TEST/DEBUG) */
764
765 mtmsr r12 /* (TEST/DEBUG) */
766 isync /* (TEST/DEBUG) */
767
768 #if 0
769 mtmsr r8 /* (TEST/DEBUG) */
770 isync /* (TEST/DEBUG) */
771 #endif
772
773 lis r12,0xF301 /* (TEST/DEBUG) */
774 ori r12,r12,0x2002 /* (TEST/DEBUG) */
775 #if 1
776 dcbf 0,r12 /* (TEST/DEBUG) */
777 sync /* (TEST/DEBUG) */
778 dcbi 0,r12 /* (TEST/DEBUG) */
779 #endif
780
781 xqrw1: eieio /* (TEST/DEBUG) */
782 lbz r7,0(r12) /* (TEST/DEBUG) */
783 dcbi 0,r12 /* (TEST/DEBUG) */
784 sync /* (TEST/DEBUG) */
785 andi. r7,r7,0x04 /* (TEST/DEBUG) */
786 beq xqrw1 /* (TEST/DEBUG) */
787
788 eieio /* (TEST/DEBUG) */
789 li r7,0x36 /* (TEST/DEBUG) */
790 stb r7,4(r12) /* (TEST/DEBUG) */
791 eieio
792 dcbf 0,r12 /* (TEST/DEBUG) */
793 sync /* (TEST/DEBUG) */
794 dcbi 0,r12 /* (TEST/DEBUG) */
795 eieio /* (TEST/DEBUG) */
796
797
798 lis r7,10 /* (TEST/DEBUG) */
799 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
800 mr. r7,r7 /* (TEST/DEBUG) */
801 bne- spw7 /* (TEST/DEBUG) */
802 dcbf 0,r12 /* (TEST/DEBUG) */
803 sync /* (TEST/DEBUG) */
804 dcbi 0,r12 /* (TEST/DEBUG) */
805 eieio /* (TEST/DEBUG) */
806 mr r12,r9 /* (TEST/DEBUG) */
807 #endif
808
809 mtmsr r12 /* Smash the MSR */
810 isync /* Make it clean */
811
812
813 #if SIMPLESCC && !NOTQUITEASSIMPLE
814 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */
815 #else
816 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
817 #endif
818 beq+ dbgDprintr /* It sure are... */
819 #if SIMPLESCC && !NOTQUITEASSIMPLE
820 ori r10,r10,0x0020 /* Move it over to the modem port */
821 #else
822 ori r10,r10,0x0002 /* Move it over to the modem port */
823
824 #if !NOTQUITEASSIMPLE
825 lis r7,0xF300 /* Address of SCC rounded to 128k */
826 ori r7,r7,0x0032 /* Make it cache inhibited */
827 mtdbatl 3,r7 /* Load DBAT 3 low */
828 lis r7,0xF300 /* Address of SCC rounded to 128k */
829 ori r7,r7,0x0002 /* Make it supervisor only */
830 mtdbatu 3,r7 /* Load DBAT 3 high */
831 ori r12,r12,0x0010 /* Turn on DR */
832 mtmsr r12 /* Smash the MSR */
833 isync /* Make it clean */
834
835 #endif
836 #endif
837
838 dbgDprintr: sync
839 #if 0
840 mr r7,r10 /* (TEST/DEBUG) */
841 bl dumpr7 /* (TEST/DEBUG) */
842 #endif
843
844 dcbi 0,r10 /* Toss it */
845 eieio
846
847 #if 0
848 lis r12,0xF301 /* (TEST/DEBUG) */
849 ori r12,r12,0x2002 /* (TEST/DEBUG) */
850 dcbf 0,r12 /* (TEST/DEBUG) */
851 sync /* (TEST/DEBUG) */
852 dcbi 0,r12 /* (TEST/DEBUG) */
853 eieio /* (TEST/DEBUG) */
854 li r7,0x37 /* (TEST/DEBUG) */
855 stb r7,4(r12) /* (TEST/DEBUG) */
856
857 lis r7,12 /* (TEST/DEBUG) */
858 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
859 mr. r7,r7 /* (TEST/DEBUG) */
860 bne- spw8 /* (TEST/DEBUG) */
861 dcbf 0,r12 /* (TEST/DEBUG) */
862 sync /* (TEST/DEBUG) */
863 dcbi 0,r12 /* (TEST/DEBUG) */
864 eieio /* (TEST/DEBUG) */
865 #endif
866
867
868 /* Print the ID parameter */
869
870 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
871 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
872
873 lwarx r7,0,r12 ; ?
874
875 ddwait0: lwarx r7,0,r12 /* Get the lock */
876 mr. r7,r7 /* Is it locked? */
877 bne- ddwait0 /* Yup... */
878 stwcx. r12,0,r12 /* Try to get it */
879 bne- ddwait0 /* Nope, start all over... */
880
881 #if 0
882 dcbf 0,r10 /* (TEST/DEBUG) */
883 sync /* (TEST/DEBUG) */
884 dcbi 0,r10 /* (TEST/DEBUG) */
885 eieio /* (TEST/DEBUG) */
886 li r7,0x38 /* (TEST/DEBUG) */
887 stb r7,6(r10) /* (TEST/DEBUG) */
888
889 lis r7,10 /* (TEST/DEBUG) */
890 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
891 mr. r7,r7 /* (TEST/DEBUG) */
892 bne- spwa /* (TEST/DEBUG) */
893 dcbf 0,r10 /* (TEST/DEBUG) */
894 sync /* (TEST/DEBUG) */
895 dcbi 0,r10 /* (TEST/DEBUG) */
896 eieio /* (TEST/DEBUG) */
897 #endif
898
899 rlwinm r3,r3,8,0,31 /* Get the first character */
900 bl dbgDchar /* Print it */
901 rlwinm r3,r3,8,0,31 /* Get the second character */
902 bl dbgDchar /* Print it */
903 rlwinm r3,r3,8,0,31 /* Get the third character */
904 bl dbgDchar /* Print it */
905 rlwinm r3,r3,8,0,31 /* Get the fourth character */
906 bl dbgDchar /* Print it */
907
908 li r3,0x20 /* Get a space for a separator */
909 bl dbgDchar /* Print it */
910 bl dbg4byte /* Print register 5 in hex */
911
912 li r3,0x0A /* Linefeed */
913 bl dbgDchar /* Send it */
914 li r3,0x0D /* Carriage return */
915 bl dbgDchar /* Send it */
916
917 mtlr r11 /* Get back the return */
918 #if !SIMPLESCC && !NOTQUITEASSIMPLE
919 li r7,0 /* Get a zero */
920 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
921 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
922 #endif
923 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
924 li r7,0 /* Get a zero */
925 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
926 dcbi 0,r10 /* ? */
927 stw r7,0(r12) /* Release the display lock */
928 mtmsr r8 /* Restore the MSR */
929 isync /* Wait for it */
930 blr /* Leave... */
931
932
933 dbg4byte: mflr r12 /* Save the return */
934
935 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */
936 li r6,8 /* Set number of hex digits to dump */
937 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */
938
939 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */
940 subi r6,r6,1 /* Back down the count */
941 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */
942 lbzx r3,r4,r3 /* Convert to ascii */
943 bl dbgDchar /* Print it */
944 mr. r6,r6 /* Any more? */
945 bne+ dbgDnext /* Convert 'em all... */
946
947 li r3,0x20 /* Space */
948 bl dbgDchar /* Send it */
949 mtlr r12 /* Restore LR */
950 blr /* Return... */
951
952 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */
953
954 dbgDchar:
955 #if SIMPLESCC && !NOTQUITEASSIMPLE
956 stb r3,0(r10) /* ? */
957 dcbf 0,r10 /* Force it out */
958 sync /* Make sure it's out there */
959
960 lis r7,3 /* Get enough for about 1ms */
961
962 dbgDchar0: addi r7,r7,-1 /* Count down */
963 mr. r7,r7 /* Waited long enough? */
964 bgt+ dbgDchar0 /* Nope... */
965 #endif
966 #if NOTQUITEASSIMPLE
967 #if 0
968 li r7,0x01 /* ? */
969 stb r7,0(r10) /* ? */
970 dcbf 0,r10 /* Force it out */
971 sync /* Make sure it's out there */
972 dcbi 0,r10
973 eieio
974
975 lbz r7,0(r10) /* ? */
976 dcbi 0,r10 /* Force it out */
977 sync /* kill it off */
978 eieio
979
980 li r7,0x00 /* ? */
981 stb r7,0(r10) /* ? */
982 dcbf 0,r10 /* Force it out */
983 sync /* Make sure it's out there */
984 dcbi 0,r10
985 eieio
986
987 lbz r7,0(r10) /* ? */
988 dcbi 0,r10 /* Force it out */
989 sync /* kill it off */
990 eieio
991 #endif
992
993 qrw1: eieio /* Barricade it */
994 lbz r7,0(r10) /* ? */
995 dcbi 0,r10
996 sync
997 andi. r7,r7,0x04 /* ? */
998 beq qrw1 /* Nope... */
999
1000 eieio
1001
1002 stb r3,4(r10) /* ? */
1003 dcbf 0,r10 /* Force it out */
1004 sync /* Make sure it's out there */
1005 dcbi 0,r10
1006 eieio
1007
1008 qrw2: eieio /* Barricade it */
1009 lbz r7,0(r10) /* ? */
1010 dcbi 0,r10
1011 sync
1012 andi. r7,r7,0x04 /* ? */
1013 beq qrw2 /* Nope... */
1014
1015 #if 0
1016 eieio
1017 li r7,0x10 /* ? */
1018 stb r7,0(r10) /* ? */
1019 dcbf 0,r10 /* Force it out */
1020 sync /* Make sure it's out there */
1021 dcbi 0,r10
1022 eieio
1023
1024 lbz r7,0(r10) /* ? */
1025 dcbi 0,r10 /* Force it out */
1026 sync /* kill it off */
1027 eieio
1028 #endif
1029
1030 lis r7,0x0080 /* ? */
1031 lis r9,0xF300 /* ? */
1032 ori r7,r7,0x010F /* ? */
1033 stw r7,0x28(r9) /* ? */
1034 dcbf 0,r10 /* Force it out */
1035 sync /* Make sure it's out there */
1036 dcbi 0,r10
1037 eieio
1038
1039 #endif
1040 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1041 rlwinm r9,r10,0,0,29 /* Get channel a */
1042 eieio /* Barricade it */
1043
1044 li r7,0x03 /* ? */
1045 stb r7,0(r9) /* ? */
1046 eieio /* Barricade it */
1047
1048 lbz r7,0(r9) /* ? */
1049
1050 eieio /* Barricade it */
1051 lbz r7,0(r9) /* ? */
1052
1053 dchrw1: eieio /* Barricade it */
1054 lbz r7,0(r10) /* ? */
1055 andi. r7,r7,0x04 /* ? */
1056 beq dchrw1 /* Nope... */
1057
1058 stb r3,4(r10) /* ? */
1059 sync /* Make sure it's there */
1060 eieio /* Don't get confused */
1061
1062 dchrw2: eieio /* Barricade it */
1063 lbz r7,0(r10) /* ? */
1064 andi. r7,r7,0x04 /* ? */
1065 beq dchrw2 /* Nope... */
1066
1067 eieio /* Avoid confusion */
1068 lbz r7,0(r10) /* ? */
1069 andi. r7,r7,0x40 /* ? */
1070 beq+ nounder /* Nope... */
1071
1072 eieio /* Avoid confusion */
1073 li r7,0xC0 /* ? */
1074 stb r7,0(r10) /* ? */
1075
1076 nounder: eieio /* Avoid confusion */
1077 li r7,0x10 /* ? */
1078 stb r7,0(r10) /* ? */
1079
1080 eieio /* Avoid confusion */
1081 li r7,0x38 /* ? */
1082 stb r7,0(r9) /* ? */
1083
1084 eieio /* Avoid confusion */
1085 li r7,0x30 /* ? */
1086 stb r7,0(r10) /* ? */
1087
1088 eieio /* Avoid confusion */
1089 li r7,0x20 /* ? */
1090 stb r7,0(r10) /* ? */
1091 eieio /* Avoid confusion */
1092 sync
1093
1094 #endif
1095 blr /* Return */
1096
1097 .globl hexTab
1098
1099 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */
1100
1101
1102 /*
1103 * Dumps all the registers in the savearea in R13
1104 */
1105
1106
1107 .align 5
1108 .globl EXT(dbgRegsLL)
1109
1110 LEXT(dbgRegsLL)
1111
1112 b EXT(FCReturn) ; Bye dudes...
1113 #if 0
1114 li r3,0 /* ? */
1115 bl dbgRegsCm /* Join on up... */
1116 b EXT(FCReturn) ; Bye dudes...
1117
1118
1119 .align 5
1120 .globl EXT(dbgRegs)
1121
1122 LEXT(dbgRegs)
1123
1124 dbgRegsCm: mfmsr r8 /* Save the MSR */
1125 mr. r3,r3 /* ? */
1126 rlwinm r12,r8,0,28,25 /* Turn off translation */
1127 lis r10,0xF301 /* Set the top part */
1128 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
1129 mtmsr r12 /* Smash the MSR */
1130 isync /* Make it clean */
1131 #if SIMPLESCC && !NOTQUITEASSIMPLE
1132 ori r10,r10,0x3010 /* ? */
1133 #else
1134 ori r10,r10,0x2000 /* ? */
1135 #endif
1136 mflr r11 /* Save the link register */
1137 beq+ dbgDprints /* It sure are... */
1138 #if SIMPLESCC && !NOTQUITEASSIMPLE
1139 ori r10,r10,0x0020 /* ? */
1140 #else
1141 ori r10,r10,0x0002 /* ? */
1142
1143 dcbf 0,r10 /* Insure it is out */
1144 sync
1145 dcbi 0,r10 /* Toss it */
1146 #if !NOTQUITEASSIMPLE
1147 lis r7,0xF300 /* ? */
1148 ori r7,r7,0x0032 /* ? */
1149 mtdbatl 3,r7 /* ? */
1150 lis r7,0xF300 /* ? */
1151 ori r7,r7,0x0002 /* ? */
1152 mtdbatu 3,r7 /* ? */
1153 ori r12,r12,0x0010 /* ? */
1154 mtmsr r12 /* ? */
1155 isync /* ? */
1156 #endif
1157 #endif
1158
1159 dbgDprints:
1160 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1161 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1162
1163 lwarx r5,0,r3 ; ?
1164 ddwait1: lwarx r5,0,r3 /* Get the lock */
1165 mr. r5,r5 /* Is it locked? */
1166 bne- ddwait1 /* Yup... */
1167 stwcx. r3,0,r3 /* Try to get it */
1168 bne- ddwait1 /* Nope, start all over... */
1169
1170 li r3,0x52 /* Print eyecatcher */
1171 bl dbgDchar /* Send it */
1172 li r3,0x65 /* Print eyecatcher */
1173 bl dbgDchar /* Send it */
1174 li r3,0x67 /* Print eyecatcher */
1175 bl dbgDchar /* Send it */
1176 li r3,0x73 /* Print eyecatcher */
1177 bl dbgDchar /* Send it */
1178 li r3,0x20 /* Print eyecatcher */
1179 bl dbgDchar /* Send it */
1180
1181 lwz r5,saver0(r13) /* Do register */
1182 bl dbg4byte /* Print */
1183 lwz r5,saver1(r13) /* Do register */
1184 bl dbg4byte /* Print */
1185 lwz r5,saver2(r13) /* Do register */
1186 bl dbg4byte /* Print */
1187 lwz r5,saver3(r13) /* Do register */
1188 bl dbg4byte /* Print */
1189 li r3,0x0A /* Linefeed */
1190 bl dbgDchar /* Send it */
1191 li r3,0x0D /* Carriage return */
1192 bl dbgDchar /* Send it */
1193
1194 li r3,0x20 /* Print eyecatcher */
1195 bl dbgDchar /* Send it */
1196 li r3,0x20 /* Print eyecatcher */
1197 bl dbgDchar /* Send it */
1198 li r3,0x20 /* Print eyecatcher */
1199 bl dbgDchar /* Send it */
1200 li r3,0x20 /* Print eyecatcher */
1201 bl dbgDchar /* Send it */
1202 li r3,0x20 /* Print eyecatcher */
1203 bl dbgDchar /* Send it */
1204 lwz r5,saver4(r13) /* Do register */
1205 bl dbg4byte /* Print */
1206 lwz r5,saver5(r13) /* Do register */
1207 bl dbg4byte /* Print */
1208 lwz r5,saver6(r13) /* Do register */
1209 bl dbg4byte /* Print */
1210 lwz r5,saver7(r13) /* Do register */
1211 bl dbg4byte /* Print */
1212 li r3,0x0A /* Linefeed */
1213 bl dbgDchar /* Send it */
1214 li r3,0x0D /* Carriage return */
1215 bl dbgDchar /* Send it */
1216
1217 li r3,0x20 /* Print eyecatcher */
1218 bl dbgDchar /* Send it */
1219 li r3,0x20 /* Print eyecatcher */
1220 bl dbgDchar /* Send it */
1221 li r3,0x20 /* Print eyecatcher */
1222 bl dbgDchar /* Send it */
1223 li r3,0x20 /* Print eyecatcher */
1224 bl dbgDchar /* Send it */
1225 li r3,0x20 /* Print eyecatcher */
1226 bl dbgDchar /* Send it */
1227 lwz r5,saver8(r13) /* Do register */
1228 bl dbg4byte /* Print */
1229 lwz r5,saver9(r13) /* Do register */
1230 bl dbg4byte /* Print */
1231 lwz r5,saver10(r13) /* Do register */
1232 bl dbg4byte /* Print */
1233 lwz r5,saver11(r13) /* Do register */
1234 bl dbg4byte /* Print */
1235 li r3,0x0A /* Linefeed */
1236 bl dbgDchar /* Send it */
1237 li r3,0x0D /* Carriage return */
1238 bl dbgDchar /* Send it */
1239
1240 li r3,0x20 /* Print eyecatcher */
1241 bl dbgDchar /* Send it */
1242 li r3,0x20 /* Print eyecatcher */
1243 bl dbgDchar /* Send it */
1244 li r3,0x20 /* Print eyecatcher */
1245 bl dbgDchar /* Send it */
1246 li r3,0x20 /* Print eyecatcher */
1247 bl dbgDchar /* Send it */
1248 li r3,0x20 /* Print eyecatcher */
1249 bl dbgDchar /* Send it */
1250 lwz r5,saver12(r13) /* Do register */
1251 bl dbg4byte /* Print */
1252 lwz r5,saver13(r13) /* Do register */
1253 bl dbg4byte /* Print */
1254 lwz r5,saver14(r13) /* Do register */
1255 bl dbg4byte /* Print */
1256 lwz r5,saver15(r13) /* Do register */
1257 bl dbg4byte /* Print */
1258 li r3,0x0A /* Linefeed */
1259 bl dbgDchar /* Send it */
1260 li r3,0x0D /* Carriage return */
1261 bl dbgDchar /* Send it */
1262
1263 li r3,0x20 /* Print eyecatcher */
1264 bl dbgDchar /* Send it */
1265 li r3,0x20 /* Print eyecatcher */
1266 bl dbgDchar /* Send it */
1267 li r3,0x20 /* Print eyecatcher */
1268 bl dbgDchar /* Send it */
1269 li r3,0x20 /* Print eyecatcher */
1270 bl dbgDchar /* Send it */
1271 li r3,0x20 /* Print eyecatcher */
1272 bl dbgDchar /* Send it */
1273 lwz r5,saver16(r13) /* Do register */
1274 bl dbg4byte /* Print */
1275 lwz r5,saver17(r13) /* Do register */
1276 bl dbg4byte /* Print */
1277 lwz r5,saver18(r13) /* Do register */
1278 bl dbg4byte /* Print */
1279 lwz r5,saver19(r13) /* Do register */
1280 bl dbg4byte /* Print */
1281 li r3,0x0A /* Linefeed */
1282 bl dbgDchar /* Send it */
1283 li r3,0x0D /* Carriage return */
1284 bl dbgDchar /* Send it */
1285
1286 li r3,0x20 /* Print eyecatcher */
1287 bl dbgDchar /* Send it */
1288 li r3,0x20 /* Print eyecatcher */
1289 bl dbgDchar /* Send it */
1290 li r3,0x20 /* Print eyecatcher */
1291 bl dbgDchar /* Send it */
1292 li r3,0x20 /* Print eyecatcher */
1293 bl dbgDchar /* Send it */
1294 li r3,0x20 /* Print eyecatcher */
1295 bl dbgDchar /* Send it */
1296 lwz r5,saver20(r13) /* Do register */
1297 bl dbg4byte /* Print */
1298 lwz r5,saver21(r13) /* Do register */
1299 bl dbg4byte /* Print */
1300 lwz r5,saver22(r13) /* Do register */
1301 bl dbg4byte /* Print */
1302 lwz r5,saver23(r13) /* Do register */
1303 bl dbg4byte /* Print */
1304 li r3,0x0A /* Linefeed */
1305 bl dbgDchar /* Send it */
1306 li r3,0x0D /* Carriage return */
1307 bl dbgDchar /* Send it */
1308
1309 li r3,0x20 /* Print eyecatcher */
1310 bl dbgDchar /* Send it */
1311 li r3,0x20 /* Print eyecatcher */
1312 bl dbgDchar /* Send it */
1313 li r3,0x20 /* Print eyecatcher */
1314 bl dbgDchar /* Send it */
1315 li r3,0x20 /* Print eyecatcher */
1316 bl dbgDchar /* Send it */
1317 li r3,0x20 /* Print eyecatcher */
1318 bl dbgDchar /* Send it */
1319 lwz r5,saver24(r13) /* Do register */
1320 bl dbg4byte /* Print */
1321 lwz r5,saver25(r13) /* Do register */
1322 bl dbg4byte /* Print */
1323 lwz r5,saver26(r13) /* Do register */
1324 bl dbg4byte /* Print */
1325 lwz r5,saver27(r13) /* Do register */
1326 bl dbg4byte /* Print */
1327 li r3,0x0A /* Linefeed */
1328 bl dbgDchar /* Send it */
1329 li r3,0x0D /* Carriage return */
1330 bl dbgDchar /* Send it */
1331
1332 li r3,0x20 /* Print eyecatcher */
1333 bl dbgDchar /* Send it */
1334 li r3,0x20 /* Print eyecatcher */
1335 bl dbgDchar /* Send it */
1336 li r3,0x20 /* Print eyecatcher */
1337 bl dbgDchar /* Send it */
1338 li r3,0x20 /* Print eyecatcher */
1339 bl dbgDchar /* Send it */
1340 li r3,0x20 /* Print eyecatcher */
1341 bl dbgDchar /* Send it */
1342 lwz r5,saver28(r13) /* Do register */
1343 bl dbg4byte /* Print */
1344 lwz r5,saver29(r13) /* Do register */
1345 bl dbg4byte /* Print */
1346 lwz r5,saver30(r13) /* Do register */
1347 bl dbg4byte /* Print */
1348 lwz r5,saver31(r13) /* Do register */
1349 bl dbg4byte /* Print */
1350 li r3,0x0A /* Linefeed */
1351 bl dbgDchar /* Send it */
1352 li r3,0x0D /* Carriage return */
1353 bl dbgDchar /* Send it */
1354
1355 /* Segment registers */
1356
1357 li r3,0x53 /* Print eyecatcher */
1358 bl dbgDchar /* Send it */
1359 li r3,0x65 /* Print eyecatcher */
1360 bl dbgDchar /* Send it */
1361 li r3,0x67 /* Print eyecatcher */
1362 bl dbgDchar /* Send it */
1363 li r3,0x73 /* Print eyecatcher */
1364 bl dbgDchar /* Send it */
1365 li r3,0x20 /* Print eyecatcher */
1366 bl dbgDchar /* Send it */
1367
1368 lwz r5,savesr0(r13) /* Do register */
1369 bl dbg4byte /* Print */
1370 lwz r5,savesr1(r13) /* Do register */
1371 bl dbg4byte /* Print */
1372 lwz r5,savesr2(r13) /* Do register */
1373 bl dbg4byte /* Print */
1374 lwz r5,savesr3(r13) /* Do register */
1375 bl dbg4byte /* Print */
1376 li r3,0x0A /* Linefeed */
1377 bl dbgDchar /* Send it */
1378 li r3,0x0D /* Carriage return */
1379 bl dbgDchar /* Send it */
1380
1381 li r3,0x20 /* Print eyecatcher */
1382 bl dbgDchar /* Send it */
1383 li r3,0x20 /* Print eyecatcher */
1384 bl dbgDchar /* Send it */
1385 li r3,0x20 /* Print eyecatcher */
1386 bl dbgDchar /* Send it */
1387 li r3,0x20 /* Print eyecatcher */
1388 bl dbgDchar /* Send it */
1389 li r3,0x20 /* Print eyecatcher */
1390 bl dbgDchar /* Send it */
1391 lwz r5,savesr4(r13) /* Do register */
1392 bl dbg4byte /* Print */
1393 lwz r5,savesr5(r13) /* Do register */
1394 bl dbg4byte /* Print */
1395 lwz r5,savesr6(r13) /* Do register */
1396 bl dbg4byte /* Print */
1397 lwz r5,savesr7(r13) /* Do register */
1398 bl dbg4byte /* Print */
1399 li r3,0x0A /* Linefeed */
1400 bl dbgDchar /* Send it */
1401 li r3,0x0D /* Carriage return */
1402 bl dbgDchar /* Send it */
1403
1404 li r3,0x20 /* Print eyecatcher */
1405 bl dbgDchar /* Send it */
1406 li r3,0x20 /* Print eyecatcher */
1407 bl dbgDchar /* Send it */
1408 li r3,0x20 /* Print eyecatcher */
1409 bl dbgDchar /* Send it */
1410 li r3,0x20 /* Print eyecatcher */
1411 bl dbgDchar /* Send it */
1412 li r3,0x20 /* Print eyecatcher */
1413 bl dbgDchar /* Send it */
1414 lwz r5,savesr8(r13) /* Do register */
1415 bl dbg4byte /* Print */
1416 lwz r5,savesr9(r13) /* Do register */
1417 bl dbg4byte /* Print */
1418 lwz r5,savesr10(r13) /* Do register */
1419 bl dbg4byte /* Print */
1420 lwz r5,savesr11(r13) /* Do register */
1421 bl dbg4byte /* Print */
1422 li r3,0x0A /* Linefeed */
1423 bl dbgDchar /* Send it */
1424 li r3,0x0D /* Carriage return */
1425 bl dbgDchar /* Send it */
1426
1427 li r3,0x20 /* Print eyecatcher */
1428 bl dbgDchar /* Send it */
1429 li r3,0x20 /* Print eyecatcher */
1430 bl dbgDchar /* Send it */
1431 li r3,0x20 /* Print eyecatcher */
1432 bl dbgDchar /* Send it */
1433 li r3,0x20 /* Print eyecatcher */
1434 bl dbgDchar /* Send it */
1435 li r3,0x20 /* Print eyecatcher */
1436 bl dbgDchar /* Send it */
1437 lwz r5,savesr12(r13) /* Do register */
1438 bl dbg4byte /* Print */
1439 lwz r5,savesr13(r13) /* Do register */
1440 bl dbg4byte /* Print */
1441 lwz r5,savesr14(r13) /* Do register */
1442 bl dbg4byte /* Print */
1443 lwz r5,savesr15(r13) /* Do register */
1444 bl dbg4byte /* Print */
1445 li r3,0x0A /* Linefeed */
1446 bl dbgDchar /* Send it */
1447 li r3,0x0D /* Carriage return */
1448 bl dbgDchar /* Send it */
1449
1450 li r3,0x30 /* Print eyecatcher */
1451 bl dbgDchar /* Send it */
1452 li r3,0x31 /* Print eyecatcher */
1453 bl dbgDchar /* Send it */
1454 li r3,0x64 /* Print eyecatcher */
1455 bl dbgDchar /* Send it */
1456 li r3,0x64 /* Print eyecatcher */
1457 bl dbgDchar /* Send it */
1458 li r3,0x20 /* Print eyecatcher */
1459 bl dbgDchar /* Send it */
1460 lwz r5,savesrr0(r13) /* Do register */
1461 bl dbg4byte /* Print */
1462 lwz r5,savesrr1(r13) /* Do register */
1463 bl dbg4byte /* Print */
1464 lwz r5,savedar(r13) /* Do register */
1465 bl dbg4byte /* Print */
1466 lwz r5,savedsisr(r13) /* Do register */
1467 bl dbg4byte /* Print */
1468 li r3,0x0A /* Linefeed */
1469 bl dbgDchar /* Send it */
1470 li r3,0x0D /* Carriage return */
1471 bl dbgDchar /* Send it */
1472
1473 li r3,0x20 /* Print eyecatcher */
1474 bl dbgDchar /* Send it */
1475 li r3,0x6C /* Print eyecatcher */
1476 bl dbgDchar /* Send it */
1477 li r3,0x63 /* Print eyecatcher */
1478 bl dbgDchar /* Send it */
1479 li r3,0x63 /* Print eyecatcher */
1480 bl dbgDchar /* Send it */
1481 li r3,0x20 /* Print eyecatcher */
1482 bl dbgDchar /* Send it */
1483 lwz r5,savelr(r13) /* Do register */
1484 bl dbg4byte /* Print */
1485 lwz r5,savecr(r13) /* Do register */
1486 bl dbg4byte /* Print */
1487 lwz r5,savectr(r13) /* Do register */
1488 bl dbg4byte /* Print */
1489 li r3,0x0A /* Linefeed */
1490 bl dbgDchar /* Send it */
1491 li r3,0x0D /* Carriage return */
1492 bl dbgDchar /* Send it */
1493 mtlr r11 /* Get back the return */
1494 dcbi 0,r10 /* ? */
1495 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1496 li r7,0 /* Get a zero */
1497 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1498 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1499 #endif
1500 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1501 li r7,0 /* Get a zero */
1502 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1503 stw r7,0(r3) /* Clear display lock */
1504 mtmsr r8 /* Restore the MSR */
1505 isync /* Wait for it */
1506 blr /* Leave... */
1507 #endif
1508
1509 /*
1510 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes).
1511 * Mapping is V=R. Stores and loads are real.
1512 */
1513
1514 .align 5
1515 .globl EXT(dbgCkpt)
1516
1517 LEXT(dbgCkpt)
1518
1519 mr r12,r0 /* Keep R0 pristene */
1520 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */
1521 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */
1522
1523 sc /* Go stash the stuff */
1524
1525 mr r0,r12 /* Restore R0 */
1526 blr /* Return... */
1527
1528 /* Here's the low-level part of dbgCkpt */
1529
1530 .align 5
1531 .globl EXT(dbgCkptLL)
1532
1533 LEXT(dbgCkptLL)
1534
1535
1536 li r12,0x380 /* Point to output area */
1537 li r1,32 /* Get line size */
1538 dcbz 0,r12 /* Make sure we don't fetch a cache line */
1539
1540 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1541
1542 dcbt r1,r3 /* Start in the next line */
1543
1544 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1545 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1546 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1547 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1548 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1549 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1550 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1551
1552 add r3,r3,r1 /* Bump input */
1553
1554 stw r4,0x00(r12) /* Store it */
1555 stw r5,0x04(r12) /* Store it */
1556 stw r6,0x08(r12) /* Store it */
1557 stw r7,0x0C(r12) /* Store it */
1558 stw r8,0x10(r12) /* Store it */
1559 stw r9,0x14(r12) /* Store it */
1560 stw r10,0x18(r12) /* Store it */
1561 stw r11,0x1C(r12) /* Store it */
1562
1563 dcbz r1,r12 /* Clear the next line */
1564 add r12,r12,r1 /* Point to next output line */
1565
1566 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1567 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1568 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1569 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1570 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1571 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1572 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1573 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1574
1575 dcbt r1,r3 /* Touch the next line */
1576 add r3,r3,r1 /* Point to next input line */
1577
1578 stw r4,0x00(r12) /* Store it */
1579 stw r5,0x04(r12) /* Store it */
1580 stw r6,0x08(r12) /* Store it */
1581 stw r7,0x0C(r12) /* Store it */
1582 stw r8,0x10(r12) /* Store it */
1583 stw r9,0x14(r12) /* Store it */
1584 stw r10,0x18(r12) /* Store it */
1585 stw r11,0x1C(r12) /* Store it */
1586
1587 dcbz r1,r12 /* Clear the next line */
1588 add r12,r12,r1 /* Point to next output line */
1589
1590 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1591 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1592 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1593 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1594 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1595 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1596 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1597 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1598
1599 dcbt r1,r3 /* Touch the next line */
1600 add r3,r3,r1 /* Point to next input line */
1601
1602 stw r4,0x00(r12) /* Store it */
1603 stw r5,0x04(r12) /* Store it */
1604 stw r6,0x08(r12) /* Store it */
1605 stw r7,0x0C(r12) /* Store it */
1606 stw r8,0x10(r12) /* Store it */
1607 stw r9,0x14(r12) /* Store it */
1608 stw r10,0x18(r12) /* Store it */
1609 stw r11,0x1C(r12) /* Store it */
1610
1611 dcbz r1,r12 /* Clear the next line */
1612 add r12,r12,r1 /* Point to next output line */
1613
1614 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1615 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1616 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1617 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1618 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1619 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1620 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1621 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1622
1623 stw r4,0x00(r12) /* Store it */
1624 stw r5,0x04(r12) /* Store it */
1625 stw r6,0x08(r12) /* Store it */
1626 stw r7,0x0C(r12) /* Store it */
1627 stw r8,0x10(r12) /* Store it */
1628 stw r9,0x14(r12) /* Store it */
1629 stw r10,0x18(r12) /* Store it */
1630 stw r11,0x1C(r12) /* Store it */
1631
1632 blr
1633
1634
1635 /*
1636 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur.
1637 */
1638
1639 .align 5
1640 .globl EXT(DoPreemptLL)
1641
1642 LEXT(DoPreemptLL)
1643
1644 li r3,T_PREEMPT /* Set preemption interrupt value */
1645 stw r3,saveexception(r13) /* Modify the exception type to preemption */
1646 b EXT(FCReturn) ; Bye dudes...
1647
1648
1649 /*
1650 * Force 'rupt handler to dispatch with new context
1651 * R3 at the call contains the new savearea.
1652 * R4 at the call contains a return code to pass back in R3.
1653 * Forces a T_CSWITCH
1654 */
1655
1656 .align 5
1657 .globl EXT(SwitchContextLL)
1658
1659 LEXT(SwitchContextLL)
1660
1661 li r3,T_CSWITCH /* Set context switch value */
1662 stw r3,saveexception(r13) /* Modify the exception type to switch context */
1663 b EXT(FCReturn) ; Bye dudes...
1664
1665
1666 /*
1667 * Create a fake I/O 'rupt.
1668 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred.
1669 */
1670
1671 .align 5
1672 .globl EXT(CreateFakeIOLL)
1673
1674 LEXT(CreateFakeIOLL)
1675
1676 li r3,T_INTERRUPT /* Set external interrupt value */
1677 stw r3,saveexception(r13) /* Modify the exception type to external */
1678 b EXT(FCReturn) ; Bye dudes...
1679
1680 /*
1681 * Create a shutdown context
1682 * Forces a T_SHUTDOWN trap.
1683 */
1684
1685 .align 5
1686 .globl EXT(CreateShutdownCTXLL)
1687
1688 LEXT(CreateShutdownCTXLL)
1689
1690 li r3,T_SHUTDOWN /* Set external interrupt value */
1691 stw r3,saveexception(r13) /* Modify the exception type to external */
1692 b EXT(FCReturn) ; Bye dudes...
1693
1694 /*
1695 * Create a fake decrementer 'rupt.
1696 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred.
1697 */
1698
1699 .align 5
1700 .globl EXT(CreateFakeDECLL)
1701
1702 LEXT(CreateFakeDECLL)
1703
1704 li r3,T_DECREMENTER /* Set decrementer interrupt value */
1705 stw r3,saveexception(r13) /* Modify the exception type to external */
1706 b EXT(FCReturn) ; Bye dudes...
1707
1708 /*
1709 * Choke the system.
1710 */
1711
1712 .align 5
1713 .globl EXT(DoChokeLL)
1714
1715 LEXT(DoChokeLL)
1716
1717 li r3,T_CHOKE ; Set external interrupt value
1718 stw r3,saveexception(r13) ; Modify the exception type to external
1719 b EXT(FCReturn) ; Bye dudes...
1720
1721 /*
1722 * Null firmware call
1723 */
1724
1725 .align 5
1726 .globl EXT(NullLL)
1727
1728 LEXT(NullLL)
1729
1730 li r3,T_IN_VAIN ; Set to just ignore this one
1731 b EXT(FCReturn) ; Bye dudes...
1732
1733 ;
1734 ; Null firmware call
1735 ;
1736
1737 .align 5
1738 .globl EXT(iNullLL)
1739
1740 LEXT(iNullLL)
1741
1742 mfspr r4,pmc1 ; Get stamp
1743 stw r4,0x6100+(9*16)+0x0(0) ; Save it
1744 #if 1
1745 mfspr r4,pmc2 ; Get stamp
1746 stw r4,0x6100+(9*16)+0x4(0) ; Save it
1747 mfspr r4,pmc3 ; Get stamp
1748 stw r4,0x6100+(9*16)+0x8(0) ; Save it
1749 mfspr r4,pmc4 ; Get stamp
1750 stw r4,0x6100+(9*16)+0xC(0) ; Save it
1751 #endif
1752 li r3,T_IN_VAIN ; Set to just ignore this one
1753 b EXT(FCReturn) ; Bye dudes...
1754
1755 ;
1756 ; Set the low level trace flags
1757 ;
1758
1759 .align 5
1760 .globl EXT(LLTraceSet)
1761
1762 LEXT(LLTraceSet)
1763
1764 mr r4,r3 ; Save the new value
1765
1766 lwz r3,traceMask(0) ; Get the old trace flags to pass back
1767 stw r4,traceMask(0) ; Replace with the new ones
1768 blr ; Leave...
1769
1770 #if 0
1771
1772 /*
1773 ; ***************************************************************************
1774 ;
1775 ; ----------------- Grateful Deb ----------------
1776 ;
1777 ; Debugging: direct draw into main screen menu bar
1778 ;
1779 ; Takes R4 value, converts it to hex characters and displays it.
1780 ;
1781 ; Gotta make sure the DCBST is done to force the pixels from the cache.
1782 ;
1783 ; Position is taken as column, row (0 based) from R3.
1784 ; Characters are from hexfont, and are 16x16 pixels.
1785 ;
1786 ; Only works with two processors so far
1787 ;
1788 ;
1789 ; ***************************************************************************
1790 */
1791
1792 #define GDfromright 20
1793 #define GDfontsize 16
1794
1795 .align 5
1796 .globl EXT(GratefulDeb)
1797
1798 LEXT(GratefulDeb)
1799
1800 mfspr r6,pir /* Get the PIR */
1801 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */
1802 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */
1803 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */
1804 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */
1805 add r6,r6,r5 /* Point at our CPU's work area */
1806 mfmsr r5 /* Get that MSR */
1807 stmw r0,GDsave(r6) /* Save all registers */
1808 lwz r10,GDready(r6) /* See if we're all ready to go */
1809 ori r0,r5,0x2000 /* Turn on the floating point */
1810 mr r31,r6 /* Get a more sane base register */
1811 mr. r10,r10 /* Are we all set? */
1812 mtmsr r0 /* Enable floating point */
1813 isync
1814
1815 stfd f0,GDfp0(r31) /* Save FP */
1816 stfd f1,GDfp1(r31) /* Save FP */
1817 stfd f2,GDfp2(r31) /* Save FP */
1818 stfd f3,GDfp3(r31) /* Save FP */
1819
1820 beq- GDbailout /* Go and bail... */
1821
1822 rlwinm r25,r3,0,16,31 /* Isolate just the row number */
1823 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */
1824 rlwinm r3,r3,16,16,31 /* Isolate the column number */
1825 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */
1826 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */
1827 lwz r26,GDdepth(r31) /* Get the bit depth */
1828 mullw r25,r25,r9 /* get offset to the row to write in bytes */
1829 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */
1830 add r25,r28,r25 /* Physical address of row */
1831 mullw r3,r3,r24 /* Get byte offset to first output column */
1832
1833 li r9,32 /* Get the initial shift calc */
1834
1835 lis r20,HIGH_ADDR(hexfont) /* Point to the font */
1836
1837 li r18,GDfontsize /* Get the number of rows in the font */
1838 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */
1839 add r21,r25,r3 /* Physical address of top left output pixel */
1840 sub r9,r9,r26 /* Get right shift justifier for pixel size */
1841 li r7,32 /* Number of bits per word */
1842
1843 startNybble:
1844 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1845 li r19,8 /* Get the number of characters in a row */
1846
1847 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */
1848 rlwinm r4,r4,4,0,31 /* Rotate a nybble */
1849 add r10,r20,r10 /* Point to the character in the font */
1850
1851 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */
1852 lhz r15,0(r10) /* Get the next row of the font */
1853
1854 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */
1855 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */
1856 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */
1857
1858 slw r14,r14,r26 /* Make room for our pixel in a register */
1859 srw r17,r17,r9 /* Isolate one pixels worth of black or white */
1860 sub. r7,r7,r26 /* See how may bits are left */
1861 sub r16,r16,r26 /* Count how many bits are left to store for this row */
1862 or r14,r14,r17 /* Put in the pixel */
1863 bne+ notfull /* Finish rendering this word */
1864
1865 not r14,r14 /* Invert to black on white */
1866 stw r14,0(r6) /* Write out the word */
1867 li r7,32 /* Bit per word count */
1868 addi r6,r6,4 /* Point to the next word */
1869
1870 notfull: mr. r16,r16 /* Have we finished the whole character row? */
1871 bne+ rendrow /* Finish rendering the row */
1872
1873 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */
1874 bne+ getNybble /* Not yet... */
1875
1876 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1877 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */
1878 mr r14,r21 /* Get the frame buffer address */
1879
1880 // BREAKPOINT_TRAP
1881
1882 blitrow: lfd f0,0(r6) /* Load a line */
1883 lfd f1,8(r6)
1884 lfd f2,16(r6)
1885 lfd f3,24(r6)
1886
1887 stfd f0,0(r14) /* Blit a line */
1888 stfd f1,8(r14)
1889 stfd f2,16(r14)
1890 stfd f3,24(r14)
1891
1892 addi r6,r6,32 /* Next buffered line */
1893
1894 dcbst 0,r14 /* Force the line to the screen */
1895 sync /* Make sure the line is on it's way */
1896 eieio /* Make sure we beat the invalidate */
1897 dcbi 0,r14 /* Make sure we leave no paradox */
1898
1899 addic. r19,r19,-1 /* Done all lines yet? */
1900 addi r14,r14,32 /* Point to the next output */
1901 bne+ blitrow /* Nope, do it some more... */
1902
1903 addic. r18,r18,-1 /* Have we done all the rows in character yet? */
1904 addi r20,r20,2 /* Offset the font to the next row */
1905 add r21,r21,r27 /* Point to start of next row */
1906 bne+ startNybble /* Nope, go through the word one more time... */
1907
1908 GDbailout: mr r1,r31 /* Move the workarea base */
1909
1910 lfd f0,GDfp0(r31) /* Restore FP */
1911 lfd f1,GDfp1(r31) /* Restore FP */
1912 lfd f2,GDfp2(r31) /* Restore FP */
1913 lfd f3,GDfp3(r31) /* Restore FP */
1914
1915 mtmsr r5 /* Disable floating point */
1916 isync
1917
1918 lmw r3,GDsave+12(r1) /* Restore most registers */
1919 lwz r0,GDsave(r1) /* Restore R0 */
1920 lwz r1,GDsave+4(r1) /* Finally, R1 */
1921 blr /* Leave... */
1922
1923
1924 /*
1925 * void GratefulDebDisp(unsigned int coord, unsigned int data);
1926 */
1927
1928
1929 .align 5
1930 .globl EXT(GratefulDebDisp)
1931
1932 LEXT(GratefulDebDisp)
1933
1934 mfmsr r9 /* Save the current MSR */
1935 mflr r7 /* Save the return */
1936 andi. r8,r9,0x7FCF /* Clear interrupt and translation */
1937 mtmsr r8 /* Turn 'em really off */
1938 isync /* Make sure about the translation part */
1939 bl EXT(GratefulDeb) /* Display it */
1940 mtmsr r9 /* Restore interrupt and translation */
1941 mtlr r7 /* Restore return */
1942 isync /* Make sure */
1943 blr
1944
1945
1946 #endif
1947
1948 /*
1949 * void checkNMI(void);
1950 */
1951
1952
1953 .align 5
1954 .globl EXT(checkNMI)
1955
1956 LEXT(checkNMI)
1957
1958 mfmsr r9 /* Save it */
1959 andi. r8,r9,0x7FCF /* Clear it */
1960 mtmsr r8 /* Disable it */
1961 isync /* Fence it */
1962 lis r7,0xF300 /* Find it */
1963 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
1964 ori r7,r7,0x0020 /* Find it */
1965 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
1966 dcbi 0,r7 /* Toss it */
1967 sync /* Sync it */
1968 andc r9,r9,r2 ; Clear VEC and FP enables
1969 eieio /* Get it */
1970 lwz r6,0x000C(r7) /* Check it */
1971 eieio /* Fence it */
1972 dcbi 0,r7 /* Toss it */
1973 rlwinm. r4,r6,0,19,19 /* Check it */
1974 rlwinm r6,r6,0,20,18 /* Clear it */
1975 sync /* Sync it */
1976 eieio /* Fence it */
1977 beq+ xnonmi /* Branch on it */
1978
1979 stw r6,0x0008(r7) /* Reset it */
1980 sync /* Sync it */
1981 dcbi 0,r6 /* Toss it */
1982 eieio /* Fence it */
1983
1984 mtmsr r9 /* Restore it */
1985 isync /* Hold it */
1986
1987 BREAKPOINT_TRAP /* Kill it */
1988 blr /* Return from it */
1989
1990 xnonmi: /* Label it */
1991 mtmsr r9 /* Restore it */
1992 isync /* Hold it */
1993 blr /* Return from it */
1994
1995 ;
1996 ; Saves floating point registers
1997 ;
1998
1999 .align 5
2000 .globl EXT(stFloat)
2001
2002 LEXT(stFloat)
2003
2004 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2005 li r4,0
2006 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2007 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2008
2009 mfmsr r0 ; Save the MSR
2010
2011 andc r4,r0,r4 ; Clear EE
2012 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
2013 mtmsr r4
2014 isync
2015
2016 andc r0,r0,r2 ; Clear VEC and FP enables
2017
2018 stfd f0,0x00(r3)
2019 stfd f1,0x08(r3)
2020 stfd f2,0x10(r3)
2021 stfd f3,0x18(r3)
2022 stfd f4,0x20(r3)
2023 stfd f5,0x28(r3)
2024 stfd f6,0x30(r3)
2025 stfd f7,0x38(r3)
2026 stfd f8,0x40(r3)
2027 stfd f9,0x48(r3)
2028 stfd f10,0x50(r3)
2029 stfd f11,0x58(r3)
2030 stfd f12,0x60(r3)
2031 stfd f13,0x68(r3)
2032 stfd f14,0x70(r3)
2033 stfd f15,0x78(r3)
2034 stfd f16,0x80(r3)
2035 stfd f17,0x88(r3)
2036 stfd f18,0x90(r3)
2037 stfd f19,0x98(r3)
2038 stfd f20,0xA0(r3)
2039 stfd f21,0xA8(r3)
2040 stfd f22,0xB0(r3)
2041 stfd f23,0xB8(r3)
2042 stfd f24,0xC0(r3)
2043 stfd f25,0xC8(r3)
2044 stfd f26,0xD0(r3)
2045 stfd f27,0xD8(r3)
2046 stfd f28,0xE0(r3)
2047 stfd f29,0xE8(r3)
2048 stfd f30,0xF0(r3)
2049 stfd f31,0xF8(r3)
2050 mffs f0
2051 stfd f0,0x100(r3)
2052 lfd f0,0x00(r3)
2053 mtmsr r0
2054 isync
2055 blr
2056
2057
2058 ;
2059 ; Saves vector registers. Returns 0 if non-Altivec machine.
2060 ;
2061
2062 .align 5
2063 .globl EXT(stVectors)
2064
2065 LEXT(stVectors)
2066
2067 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2068 li r4,0
2069 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2070 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2071
2072 mfsprg r6,2 ; Get features
2073 mr r5,r3 ; Save area address
2074 rlwinm. r6,r6,0,pfAltivecb,pfAltivecb ; Do we have Altivec?
2075 li r3,0 ; Assume failure
2076 beqlr- ; No...
2077
2078 mfmsr r0 ; Save the MSR
2079
2080 andc r4,r0,r4 ; Clear EE
2081
2082 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
2083 mtmsr r4
2084 isync
2085
2086 andc r0,r0,r2 ; Clear FP and VEC
2087
2088 stvxl v0,0,r5
2089 addi r5,r5,16
2090 stvxl v1,0,r5
2091 addi r5,r5,16
2092 stvxl v2,0,r5
2093 addi r5,r5,16
2094 stvxl v3,0,r5
2095 addi r5,r5,16
2096 stvxl v4,0,r5
2097 addi r5,r5,16
2098 stvxl v5,0,r5
2099 addi r5,r5,16
2100 stvxl v6,0,r5
2101 addi r5,r5,16
2102 stvxl v7,0,r5
2103 addi r5,r5,16
2104 stvxl v8,0,r5
2105 addi r5,r5,16
2106 stvxl v9,0,r5
2107 addi r5,r5,16
2108 stvxl v10,0,r5
2109 addi r5,r5,16
2110 stvxl v11,0,r5
2111 addi r5,r5,16
2112 stvxl v12,0,r5
2113 addi r5,r5,16
2114 stvxl v13,0,r5
2115 addi r5,r5,16
2116 stvxl v14,0,r5
2117 addi r5,r5,16
2118 stvxl v15,0,r5
2119 addi r5,r5,16
2120 stvxl v16,0,r5
2121 addi r5,r5,16
2122 stvxl v17,0,r5
2123 addi r5,r5,16
2124 stvxl v18,0,r5
2125 addi r5,r5,16
2126 stvxl v19,0,r5
2127 addi r5,r5,16
2128 stvxl v20,0,r5
2129 addi r5,r5,16
2130 stvxl v21,0,r5
2131 addi r5,r5,16
2132 stvxl v22,0,r5
2133 addi r5,r5,16
2134 stvxl v23,0,r5
2135 addi r5,r5,16
2136 stvxl v24,0,r5
2137 addi r5,r5,16
2138 stvxl v25,0,r5
2139 addi r5,r5,16
2140 stvxl v26,0,r5
2141 addi r5,r5,16
2142 stvxl v27,0,r5
2143 addi r5,r5,16
2144 stvxl v28,0,r5
2145 addi r5,r5,16
2146 stvxl v29,0,r5
2147 addi r5,r5,16
2148 stvxl v30,0,r5
2149 addi r5,r5,16
2150 stvxl v31,0,r5
2151 mfvscr v31
2152 addi r6,r5,16
2153 stvxl v31,0,r6
2154 li r3,1
2155 lvxl v31,0,r5
2156 mtmsr r0
2157 isync
2158
2159 blr
2160
2161
2162 ;
2163 ; Saves yet more registers
2164 ;
2165
2166 .align 5
2167 .globl EXT(stSpecrs)
2168
2169 LEXT(stSpecrs)
2170
2171
2172 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
2173 li r4,0
2174 ori r2,r2,lo16(MASK(MSR_FP)) ; Get the FP enable
2175 ori r4,r4,lo16(MASK(MSR_EE)) ; Get the EE bit
2176
2177
2178 mfmsr r0 ; Save the MSR
2179 andc r0,r0,r2 ; Turn of VEC and FP
2180 andc r4,r0,r4 ; And EE
2181 mtmsr r4
2182 isync
2183
2184 mfpvr r12
2185 stw r12,4(r3)
2186 rlwinm r12,r12,16,16,31
2187
2188 mfdbatu r4,0
2189 mfdbatl r5,0
2190 mfdbatu r6,1
2191 mfdbatl r7,1
2192 mfdbatu r8,2
2193 mfdbatl r9,2
2194 mfdbatu r10,3
2195 mfdbatl r11,3
2196 stw r4,8(r3)
2197 stw r5,12(r3)
2198 stw r6,16(r3)
2199 stw r7,20(r3)
2200 stw r8,24(r3)
2201 stw r9,28(r3)
2202 stw r10,32(r3)
2203 stw r11,36(r3)
2204
2205 mfibatu r4,0
2206 mfibatl r5,0
2207 mfibatu r6,1
2208 mfibatl r7,1
2209 mfibatu r8,2
2210 mfibatl r9,2
2211 mfibatu r10,3
2212 mfibatl r11,3
2213 stw r4,40(r3)
2214 stw r5,44(r3)
2215 stw r6,48(r3)
2216 stw r7,52(r3)
2217 stw r8,56(r3)
2218 stw r9,60(r3)
2219 stw r10,64(r3)
2220 stw r11,68(r3)
2221
2222 mfsprg r4,0
2223 mfsprg r5,1
2224 mfsprg r6,2
2225 mfsprg r7,3
2226 stw r4,72(r3)
2227 stw r5,76(r3)
2228 stw r6,80(r3)
2229 stw r7,84(r3)
2230
2231 mfsdr1 r4
2232 stw r4,88(r3)
2233
2234 la r4,92(r3)
2235 li r5,0
2236
2237 stSnsr: mfsrin r6,r5
2238 addis r5,r5,0x1000
2239 stw r6,0(r4)
2240 mr. r5,r5
2241 addi r4,r4,4
2242 bne+ stSnsr
2243
2244 cmplwi r12,PROCESSOR_VERSION_750
2245 mfspr r4,hid0
2246 stw r4,(39*4)(r3)
2247
2248 li r4,0
2249 li r5,0
2250 li r6,0
2251 li r7,0
2252
2253 mfspr r4,hid1
2254 mfspr r5,l2cr
2255 mfspr r6,msscr0
2256 mfspr r7,msscr1
2257
2258 stw r4,(40*4)(r3)
2259 stw r6,(42*4)(r3)
2260 stw r5,(41*4)(r3)
2261 stw r7,(43*4)(r3)
2262
2263 li r4,0
2264 beq isis750
2265
2266 mfspr r4,pir
2267 isis750: stw r4,0(r3)
2268
2269 li r4,0
2270 li r5,0
2271 li r6,0
2272 li r7,0
2273 blt- b4750
2274
2275 mfspr r4,thrm1
2276 mfspr r5,thrm2
2277 mfspr r6,thrm3
2278 mfspr r7,ictc
2279
2280 b4750: stw r4,(44*4)(r3)
2281 stw r5,(45*4)(r3)
2282 stw r6,(46*4)(r3)
2283 stw r7,(47*4)(r3)
2284
2285 li r4,0
2286 li r6,0
2287 cmplwi r12,PROCESSOR_VERSION_7400
2288 bne nnmax
2289
2290 mfspr r6,dabr
2291 mfpvr r5
2292 rlwinm r5,r5,0,16,31
2293 cmplwi r5,0x1101
2294 beq gnmax
2295 cmplwi r5,0x1102
2296 bne nnmax
2297
2298 gnmax: mfspr r4,1016
2299
2300 nnmax: stw r4,(48*4)(r3)
2301 stw r6,(49*4)(r3)
2302
2303 mtmsr r0
2304 isync
2305
2306 blr
2307
2308
2309 ;
2310 ; fwEmMck - this forces the hardware to emulate machine checks
2311 ; Only valid on 64-bit machines
2312 ; Note: we want interruptions disabled here
2313 ;
2314
2315 .globl EXT(fwEmMck)
2316
2317 .align 5
2318
2319 LEXT(fwEmMck)
2320
2321
2322 rlwinm r3,r3,0,1,0 ; Copy low of high high - scomd
2323 rlwinm r5,r5,0,1,0 ; Copy low of high high - hid1
2324 rlwinm r7,r7,0,1,0 ; Copy low of high high - hid4
2325 rlwimi r3,r4,0,0,31 ; Copy low of low low
2326 rlwimi r5,r6,0,0,31 ; Copy low of low low
2327 rlwimi r7,r8,0,0,31 ; Copy low of low low
2328
2329 lis r9,3 ; Start forming hid1 error inject mask
2330 lis r10,hi16(0x01084083) ; Start formaing hid4 error inject mask
2331 ori r9,r9,0xC000 ; Next bit
2332 ori r10,r10,lo16(0x01084083) ; Next part
2333 sldi r9,r9,32 ; Shift up high
2334 sldi r10,r10,8 ; Shift into position
2335
2336 mfspr r0,hid1 ; Get hid1
2337 mfspr r2,hid4 ; and hid4
2338
2339 and r5,r5,r9 ; Keep only error inject controls - hid1
2340 and r7,r7,r10 ; Keep only error inject controls - hid4
2341
2342 andc r0,r0,r9 ; Clear error inject controls hid1
2343 andc r2,r2,r10 ; Clear error inject controls hid4
2344
2345 or r0,r0,r5 ; Add in the new controls hid1
2346 or r2,r2,r7 ; Add in the new controls hid4
2347
2348 /* ? */
2349 #if 0
2350 lis r12,CoreErrI ; Get the error inject controls
2351 sync
2352
2353 mtspr scomd,r3 ; Set the error inject controls
2354 mtspr scomc,r12 ; Request error inject
2355 mfspr r11,scomc ; Get back the status (we just ignore it)
2356 #endif
2357 sync
2358 isync
2359
2360 mtspr hid1,r0 ; Move in hid1 controls
2361 mtspr hid1,r0 ; We need to do it twice
2362 isync
2363
2364 sync
2365 mtspr hid4,r2 ; Move in hid4 controls
2366 isync
2367
2368 blr ; Leave...
2369
2370 ;
2371 ; fwSCOMrd - read/write SCOM
2372 ;
2373 .align 5
2374 .globl EXT(fwSCOM)
2375
2376 LEXT(fwSCOM)
2377
2378 lhz r12,scomfunc(r3) ; Get the function
2379 lwz r4,scomreg(r3) ; Get the register
2380 rldicr r4,r4,8,47 ; Position for SCOM
2381
2382 mr. r12,r12 ; See if read or write
2383 bne fwSCwrite ; Go do a write
2384
2385 mfsprg r0,2 ; Get the feature flags
2386 ori r4,r4,0x8000 ; Set to read data
2387 rlwinm. r0,r0,pfSCOMFixUpb+1,31,31 ; Set shift if we need a fix me up
2388 sync
2389
2390 mtspr scomc,r4 ; Request the register
2391 mfspr r11,scomd ; Get the register contents
2392 mfspr r10,scomc ; Get back the status
2393 sync
2394 isync
2395
2396 sld r11,r11,r0 ; Fix up if needed
2397
2398 std r11,scomdata(r3) ; Save result
2399 eieio
2400 std r10,scomstat(r3) ; Save status
2401
2402 blr
2403
2404 fwSCwrite: ld r5,scomdata(r3) ; Get the data
2405
2406 sync
2407
2408 mtspr scomd,r5 ; Set the data
2409 mtspr scomc,r4 ; Set it
2410 mfspr r10,scomc ; Get back the status
2411 sync
2412 isync
2413
2414 std r10,scomstat(r3) ; Save status
2415
2416 blr
2417
2418 ;
2419 ; diagTrap - this is used to trigger checks from user space
2420 ; any "twi 31,r31,0xFFFx" will come here (x = 0 to F).
2421 ; On entry R3 points to savearea.
2422 ; R4 is the "x" from instruction;
2423 ; Pass back 1 to no-op twi and return to user
2424 ; Pass back 0 to treat as normal twi.
2425 ;
2426
2427 .globl EXT(diagTrap)
2428
2429 .align 5
2430
2431 LEXT(diagTrap)
2432
2433 li r3,1 ; Ignore TWI
2434 blr ; Leave...
2435
2436
2437
2438
2439 ;
2440 ; setPmon - this is used to manipulate MMCR0 and MMCR1
2441
2442 .globl EXT(setPmon)
2443
2444 .align 5
2445
2446 LEXT(setPmon)
2447
2448 li r0,0
2449 isync
2450 mtspr mmcr0,r0 ; Clear MMCR0
2451 mtspr mmcr1,r0 ; Clear MMCR1
2452 mtspr pmc1,r0
2453 mtspr pmc2,r0
2454 mtspr pmc3,r0
2455 mtspr pmc4,r0
2456
2457 isync
2458
2459 mtspr mmcr0,r3 ; Set MMCR0
2460 mtspr mmcr1,r4 ; Set MMCR1
2461 isync
2462 blr ; Leave...
2463
2464
mirror of XNU