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1 /*
2 * Copyright (c) 2007-2016 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /* CMU_ENDHIST */
32 /*
33 * Mach Operating System
34 * Copyright (c) 1991,1990 Carnegie Mellon University
35 * All Rights Reserved.
36 *
37 * Permission to use, copy, modify and distribute this software and its
38 * documentation is hereby granted, provided that both the copyright
39 * notice and this permission notice appear in all copies of the
40 * software, derivative works or modified versions, and any portions
41 * thereof, and that both notices appear in supporting documentation.
42 *
43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
46 *
47 * Carnegie Mellon requests users of this software to return to
48 *
49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
50 * School of Computer Science
51 * Carnegie Mellon University
52 * Pittsburgh PA 15213-3890
53 *
54 * any improvements or extensions that they make and grant Carnegie Mellon
55 * the rights to redistribute these changes.
56 */
57
58 /*
59 */
60
61 /*
62 * Processor registers for ARM
63 */
64 #ifndef _ARM_PROC_REG_H_
65 #define _ARM_PROC_REG_H_
66
67 #if defined (__arm64__)
68 #include <pexpert/arm64/board_config.h>
69 #elif defined (__arm__)
70 #include <pexpert/arm/board_config.h>
71 #endif
72
73 #if defined (ARMA7)
74 #define __ARM_ARCH__ 7
75 #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k
76 #define __ARM_VMSA__ 7
77 #define __ARM_VFP__ 3
78 #if defined(__XNU_UP__)
79 #define __ARM_SMP__ 0
80 #else
81 #define __ARM_SMP__ 1
82 /* For SMP kernels, force physical aperture to be mapped at PTE level so that its mappings
83 * can be updated to reflect cache attribute changes on alias mappings. This prevents
84 * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to
85 * an uncached alias mapping on the same core. Subsequent uncached writes from another
86 * core may not snoop this line, and the dirty line may end up being evicted later to
87 * effectively overwrite the uncached writes from other cores. */
88 #define __ARM_PTE_PHYSMAP__ 1
89 #endif
90 /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than
91 * the xnu-managed processors may need to snoop our cache operations.
92 */
93 #define __ARMA7_SMP__ 1
94 #define __ARM_COHERENT_CACHE__ 1
95 #define __ARM_L1_PTW__ 1
96 #define __ARM_DEBUG__ 7
97 #define __ARM_USER_PROTECT__ 1
98 #define __ARM_TIME_TIMEBASE_ONLY__ 1
99
100 #elif defined (APPLECYCLONE)
101 #define __ARM_ARCH__ 8
102 #define __ARM_VMSA__ 8
103 #define __ARM_SMP__ 1
104 #define __ARM_VFP__ 4
105 #define __ARM_COHERENT_CACHE__ 1
106 #define __ARM_COHERENT_IO__ 1
107 #define __ARM_IC_NOALIAS_ICACHE__ 1
108 #define __ARM_L1_PTW__ 1
109 #define __ARM_DEBUG__ 7
110 #define __ARM_ENABLE_SWAP__ 1
111 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
112 #define __ARM64_PMAP_SUBPAGE_L1__ 1
113
114 #elif defined (APPLETYPHOON)
115 #define __ARM_ARCH__ 8
116 #define __ARM_VMSA__ 8
117 #define __ARM_SMP__ 1
118 #define __ARM_VFP__ 4
119 #define __ARM_COHERENT_CACHE__ 1
120 #define __ARM_COHERENT_IO__ 1
121 #define __ARM_IC_NOALIAS_ICACHE__ 1
122 #define __ARM_L1_PTW__ 1
123 #define __ARM_DEBUG__ 7
124 #define __ARM_ENABLE_SWAP__ 1
125 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
126 #define __ARM64_PMAP_SUBPAGE_L1__ 1
127
128 #elif defined (APPLETWISTER)
129 #define __ARM_ARCH__ 8
130 #define __ARM_VMSA__ 8
131 #define __ARM_SMP__ 1
132 #define __ARM_VFP__ 4
133 #define __ARM_COHERENT_CACHE__ 1
134 #define __ARM_COHERENT_IO__ 1
135 #define __ARM_IC_NOALIAS_ICACHE__ 1
136 #define __ARM_L1_PTW__ 1
137 #define __ARM_DEBUG__ 7
138 #define __ARM_ENABLE_SWAP__ 1
139 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
140 #define __ARM_16K_PG__ 1
141 #define __ARM64_TWO_LEVEL_PMAP__ 1
142
143 #elif defined (APPLEHURRICANE)
144 #define __ARM_ARCH__ 8
145 #define __ARM_VMSA__ 8
146 #define __ARM_SMP__ 1
147 #define __ARM_VFP__ 4
148 #define __ARM_COHERENT_CACHE__ 1
149 #define __ARM_COHERENT_IO__ 1
150 #define __ARM_IC_NOALIAS_ICACHE__ 1
151 #define __ARM_L1_PTW__ 1
152 #define __ARM_DEBUG__ 7
153 #define __ARM_ENABLE_SWAP__ 1
154 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
155 #define __ARM_16K_PG__ 1
156 #define __ARM64_PMAP_SUBPAGE_L1__ 1
157 #define __ARM_GLOBAL_SLEEP_BIT__ 1
158 #define __ARM_PAN_AVAILABLE__ 1
159
160 #else
161 #error processor not supported
162 #endif
163
164 #if defined(ARM_BOARD_WFE_TIMEOUT_NS)
165 #define __ARM_ENABLE_WFE_ 1
166 #else
167 #define __ARM_ENABLE_WFE_ 0
168 #endif
169
170 #define CONFIG_THREAD_GROUPS 0
171
172
173 #ifdef XNU_KERNEL_PRIVATE
174
175 #if __ARM_VFP__
176 #define ARM_VFP_DEBUG 0
177 #endif
178
179 #endif
180
181
182
183 /*
184 * FSR registers
185 *
186 * CPSR: Current Program Status Register
187 * SPSR: Saved Program Status Registers
188 *
189 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0
190 * +-----------------------------------------------------------+
191 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE |
192 * +-----------------------------------------------------------+
193 */
194
195 /*
196 * Flags
197 */
198 #define PSR_NF 0x80000000 /* Negative/Less than */
199 #define PSR_ZF 0x40000000 /* Zero */
200 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */
201 #define PSR_VF 0x10000000 /* Overflow */
202 #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */
203
204 /*
205 * Modified execution mode flags
206 */
207 #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */
208 #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */
209 #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */
210 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */
211 #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */
212
213 /*
214 * Interrupts
215 */
216 #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */
217 #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */
218 #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */
219
220 /*
221 * CPU mode
222 */
223 #define PSR_USER_MODE 0x00000010 /* User mode */
224 #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */
225 #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */
226 #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */
227 #define PSR_ABT_MODE 0x00000017 /* Abort mode */
228 #define PSR_UND_MODE 0x0000001B /* Undefined mode */
229
230 #define PSR_MODE_MASK 0x0000001F
231 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE)
232 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE)
233
234 #define PSR_USERDFLT PSR_USER_MODE
235 #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK)
236 #define PSR_USER_SET PSR_USER_MODE
237
238 #define PSR_INTMASK PSR_IRQF /* Interrupt disable */
239
240 /*
241 * FPEXC: Floating-Point Exception Register
242 */
243
244 #define FPEXC_EX 0x80000000 /* Exception status */
245 #define FPEXC_EX_BIT 31
246 #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */
247 #define FPEXC_EN_BIT 30
248
249
250 /*
251 * FPSCR: Floating-point Status and Control Register
252 */
253
254 #define FPSCR_DN 0x02000000 /* Default NaN */
255 #define FPSCR_FZ 0x01000000 /* Flush to zero */
256
257 #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ
258
259
260 /*
261 * FSR registers
262 *
263 * IFSR: Instruction Fault Status Register
264 * DFSR: Data Fault Status Register
265 */
266 #define FSR_ALIGN 0x00000001 /* Alignment */
267 #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */
268 #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */
269 #define FSR_SFAULT 0x00000005 /* Translation Section */
270 #define FSR_PFAULT 0x00000007 /* Translation Page */
271 #define FSR_SACCESS 0x00000003 /* Section access */
272 #define FSR_PACCESS 0x00000006 /* Page Access */
273 #define FSR_SDOM 0x00000009 /* Domain Section */
274 #define FSR_PDOM 0x0000000B /* Domain Page */
275 #define FSR_SPERM 0x0000000D /* Permission Section */
276 #define FSR_PPERM 0x0000000F /* Permission Page */
277 #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */
278
279 #define FSR_MASK 0x0000040F /* Valid bits */
280 #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */
281
282 #define DFSR_WRITE 0x00000800 /* write data abort fault */
283
284 #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY)
285
286 #define TEST_FSR_VMFAULT(status) \
287 (((status) == FSR_PFAULT) \
288 || ((status) == FSR_PPERM) \
289 || ((status) == FSR_SFAULT) \
290 || ((status) == FSR_SPERM) \
291 || ((status) == FSR_ICFAULT) \
292 || ((status) == FSR_SACCESS) \
293 || ((status) == FSR_PACCESS))
294
295 #else
296
297 #error Incompatible CPU type configured
298
299 #endif
300
301 /*
302 * Cache configuration
303 */
304
305 #if defined (ARMA7)
306
307 /* I-Cache */
308 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */
309
310 /* D-Cache */
311 #define MMU_CSIZE 15 /* cache size as 1<<MMU_CSIZE (32K) */
312 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
313 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
314 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
315 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
316
317 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
318 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
319
320 #define __ARM_L2CACHE__ 1
321
322 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<MMU_CSIZE */
323 #define L2_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
324 #define L2_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */
325 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
326 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
327 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
328
329 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<MMU_SWAY */
330 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<MMU_NSET */
331
332 #elif defined (APPLECYCLONE)
333
334 /* I-Cache */
335 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
336
337 /* D-Cache */
338 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
339 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
340 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
341 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
342 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
343 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
344
345 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
346 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
347
348 #define __ARM_L2CACHE__ 1
349
350 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
351 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
352 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
353 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
354 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
355 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
356
357 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
358 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
359
360 #elif defined (APPLETYPHOON)
361
362 /* I-Cache */
363 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
364
365 /* D-Cache */
366 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
367 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
368 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
369 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
370 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
371 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
372
373 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
374 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
375
376 #define __ARM_L2CACHE__ 1
377
378 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
379 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
380 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
381 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
382 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
383 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
384
385 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
386 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
387
388 #elif defined (APPLETWISTER)
389
390 /* I-Cache */
391 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
392
393 /* D-Cache */
394 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
395 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
396 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
397 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
398 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
399 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
400
401 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
402 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
403
404 /* L2-Cache */
405 #define __ARM_L2CACHE__ 1
406
407 /*
408 * For reasons discussed in the platform expert code, we round the reported
409 * L2 size to 4MB, and adjust the other parameters accordingly.
410 */
411 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
412 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
413 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
414 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
415 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
416 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
417
418 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
419 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
420
421 #elif defined (APPLEHURRICANE)
422
423 /* I-Cache */
424 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
425
426 /* D-Cache */
427 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
428 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
429 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
430 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
431 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
432 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
433
434 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
435 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
436
437 /* L2-Cache */
438 #define __ARM_L2CACHE__ 1
439
440 /*
441 * For reasons discussed in the platform expert code, we round the reported
442 * L2 size to 4MB, and adjust the other parameters accordingly.
443 */
444 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
445 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
446 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
447 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
448 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
449 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
450
451 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
452 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
453
454 #else
455 #error processor not supported
456 #endif
457
458
459 #if (__ARM_VMSA__ <= 7)
460
461 /*
462 * SCTLR: System Control Register
463 */
464 /*
465 * System Control Register (SCTLR)
466 *
467 * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0
468 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
469 * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M|
470 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
471 *
472 * TE Thumb Exception enable
473 * AFE Access flag enable
474 * TRE TEX remap enable
475 * NMFI Non-maskable FIQ (NMFI) support
476 * EE Exception Endianness
477 * VE Interrupt Vectors Enable
478 * FI Fast interrupts configuration enable
479 * ITD IT Disable
480 * UWXN Unprivileged write permission implies PL1 XN
481 * WXN Write permission implies XN
482 * HA Hardware Access flag enable
483 * RR Round Robin select
484 * V High exception vectors
485 * I Instruction cache enable
486 * Z Branch prediction enable
487 * SW SWP/SWPB enable
488 * C15BEN CP15 barrier enable
489 * C Cache enable
490 * A Alignment check enable
491 * M MMU enable
492 */
493
494 #define SCTLR_RESERVED 0x82DD8394
495
496 #define SCTLR_ENABLE 0x00000001 /* MMU enable */
497 #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */
498 #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */
499 #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */
500 #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */
501 #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */
502 #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */
503 #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */
504 #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */
505 #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */
506 #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */
507 #define SCTLR_TRE 0x10000000 /* TEX remap enable */
508 #define SCTLR_AFE 0x20000000 /* Access flag enable */
509 #define SCTLR_TE 0x40000000 /* Thumb Exception enable */
510
511 #define SCTLR_DEFAULT (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE)
512
513
514 /*
515 * PRRR: Primary Region Remap Register
516 *
517 * 31 24 20 19 18 17 16 0
518 * +---------------------------------------------------------------+
519 * | NOSn | Res |NS1|NS0|DS1|DS0| TRn |
520 * +---------------------------------------------------------------+
521 */
522
523 #define PRRR_NS1 0x00080000
524 #define PRRR_NS0 0x00040000
525 #define PRRR_DS1 0x00020000
526 #define PRRR_DS0 0x00010000
527 #define PRRR_NOSn_ISH(region) (0x1<<((region)+24))
528
529 #if defined (ARMA7)
530 #define PRRR_SETUP (0x1F08022A)
531 #else
532 #error processor not supported
533 #endif
534
535 /*
536 * NMRR, Normal Memory Remap Register
537 *
538 * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
539 * +---------------------------------------------------------------+
540 * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0|
541 * +---------------------------------------------------------------+
542 */
543
544 #define NMRR_DISABLED 0x0 /* Non-cacheable */
545 #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */
546 #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */
547 #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */
548
549 #if defined (ARMA7)
550 #define NMRR_SETUP (0x01210121)
551 #else
552 #error processor not supported
553 #endif
554
555 /*
556 * TTBR: Translation Table Base Register
557 *
558 */
559
560 #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */
561 #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */
562 #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */
563 #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */
564
565 #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */
566 #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */
567 #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */
568 #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */
569
570 #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */
571 #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */
572
573 #if defined (ARMA7)
574 #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED)
575 #else
576 #error processor not supported
577 #endif
578
579 /*
580 * TTBCR: Translation Table Base Control register
581 *
582 * 31 3 2 0
583 * +----------+
584 * | zero | N |
585 * +----------+
586 *
587 * If N=0, always use translation table base register 0. Otherwise, if
588 * bits [31:32-N] of the address are all zero use base register 0. Otherwise,
589 * use base register 1.
590 *
591 * Reading from this register also returns the page table boundary for TTB0.
592 * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...)
593 */
594
595 #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */
596 #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */
597 #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */
598 #define TTBCR_N_MASK 0x3
599
600
601
602 /*
603 * ARM Page Granule
604 */
605 #define ARM_PGSHIFT 12
606 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
607 #define ARM_PGMASK (ARM_PGBYTES-1)
608
609 /*
610 * DACR: Domain Access Control register
611 */
612
613 #define DAC_FAULT 0x0 /* invalid domain - everyone loses */
614 #define DAC_CLIENT 0x1 /* client domain - use AP bits */
615 #define DAC_RESERVE 0x2 /* reserved domain - undefined */
616 #define DAC_MANAGER 0x3 /* manager domain - all access */
617 #define DACR_SET(dom, x) ((x)<<((dom)<<1))
618
619
620 #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */
621 #define ARM_DAC_SETUP 0x1
622
623 /*
624 * ARM 2-level Page Table support
625 */
626
627 /*
628 * Memory Attribute Index
629 */
630 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */
631 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */
632 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */
633 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */
634 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */
635 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE
636 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK
637
638
639 /*
640 * Access protection bit values
641 */
642 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
643 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
644 #define AP_RONA 0x2 /* priv=read-only , user=no-access */
645 #define AP_RORO 0x3 /* priv=read-only , user=read-only */
646
647 /*
648 * L1 Translation table
649 *
650 * Each translation table is up to 16KB
651 * 4096 32-bit entries of 1MB of address space.
652 */
653
654 #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */
655 #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */
656 #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */
657 #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */
658 #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */
659 #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */
660 #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */
661
662 #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */
663 #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1)
664
665 /*
666 * L2 Translation table
667 *
668 * Each translation table is up to 1KB
669 * 4096 32-bit entries of 1MB (2^30) of address space.
670 */
671
672 #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */
673 #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */
674 #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */
675 #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */
676
677 /*
678 * Convenience definitions for:
679 * ARM_TT_LEAF: The last level of the configured page table format.
680 * ARM_TT_TWIG: The second to last level of the configured page table format.
681 *
682 * My apologies to any botanists who may be reading this.
683 */
684 #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE
685 #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK
686 #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT
687 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK
688
689 #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE
690 #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK
691 #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT
692 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK
693
694 /*
695 * Level 1 Translation Table Entry
696 *
697 * page table entry
698 *
699 * 31 10 9 8 5 4 2 0
700 * +----------------------+-+----+--+--+--+
701 * | page table base addr | |dom |XN|00|01|
702 * +----------------------+-+----+--+--+--+
703 *
704 * direct (1MB) section entry
705 *
706 * 31 20 18 15 12 10 9 8 5 4 2 0
707 * +------------+--+-+-+-+---+--+-+----+--+--+--+
708 * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10|
709 * +------------+--+-+-+-+---+--+-+----+--+--+--+
710 *
711 * super (16MB) section entry
712 *
713 * 31 24 23 18 15 12 10 9 8 5 4 2 0
714 * +---------+------+-+-+-+---+--+-+----+--+--+--+
715 * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10|
716 * +---------+------+-+-+-+---+--+-+----+--+--+--+
717 *
718 * where:
719 * 'G' is the notGlobal bit
720 * 'S' is the shared bit
721 * 'A' in the access permission extension (APX) bit
722 * 'TEX' remap register control bits
723 * 'AP' is the access protection
724 * 'dom' is the domain for the translation
725 * 'XN' is the eXecute Never bit
726 * 'CB' is the cache/buffer attribute
727 */
728
729 #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */
730
731 #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */
732 #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */
733 #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */
734 #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */
735
736 #define ARM_TTE_BLOCK_NGSHIFT 17
737 #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */
738 #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */
739
740 #define ARM_TTE_BLOCK_SHSHIFT 16
741 #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */
742 #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */
743
744 #define ARM_TTE_BLOCK_CBSHIFT 2
745 #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT)
746 #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT)
747
748 #define ARM_TTE_BLOCK_AP0SHIFT 10
749 #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT)
750 #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT)
751
752 #define ARM_TTE_BLOCK_AP1SHIFT 11
753 #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT)
754 #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT)
755
756 #define ARM_TTE_BLOCK_AP2SHIFT 15
757 #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT)
758 #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT)
759
760
761 /* access protections */
762 #define ARM_TTE_BLOCK_AP(ap) ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) \
763 | ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT))
764
765 /* mask access protections */
766 #define ARM_TTE_BLOCK_APMASK (ARM_TTE_BLOCK_AP1_MASK \
767 | ARM_TTE_BLOCK_AP2_MASK)
768
769 #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */
770 #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */
771
772 #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */
773 #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */
774
775 #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */
776 #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */
777
778 #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */
779 #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */
780
781 #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */
782 #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */
783
784 #define ARM_TTE_BLOCK_NXSHIFT 4
785 #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */
786 #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */
787 #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX
788
789 #define ARM_TTE_BLOCK_TEX0SHIFT 12
790 #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT)
791 #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT)
792
793 #define ARM_TTE_BLOCK_TEX1SHIFT 13
794 #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT)
795 #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT)
796
797 #define ARM_TTE_BLOCK_TEX2SHIFT 14
798 #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT)
799 #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT)
800
801
802 /* mask memory attributes index */
803 #define ARM_TTE_BLOCK_ATTRINDX(i) ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) \
804 | ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT))
805
806 /* mask memory attributes index */
807 #define ARM_TTE_BLOCK_ATTRINDXMASK (ARM_TTE_BLOCK_CB_MASK \
808 | ARM_TTE_BLOCK_TEX0_MASK)
809
810
811 /*
812 * Level 2 Page table entries
813 *
814 * The following page table entry types are possible:
815 *
816 * fault page entry
817 * 31 2 0
818 * +----------------------------------------+--+
819 * | ignored |00|
820 * +----------------------------------------+--+
821 *
822 * large (64KB) page entry
823 * 31 16 15 12 9 6 4 3 2 0
824 * +----------------+--+---+-+-+-+---+--+-+-+--+
825 * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01|
826 * +----------------+--+---+-+-+-+---+--+-+-+--+
827 *
828 * small (4KB) page entry
829 * 31 12 9 6 4 3 2 1 0
830 * +-----------------------+-+-+-+---+--+-+-+-+--+
831 * | base phys addr |G|S|A|TEX|AP|C|B|1|XN|
832 * +-----------------------+-+-+-+---+--+-+-+-+--+
833 *
834 * also where:
835 * 'XN' is the eXecute Never bit
836 * 'G' is the notGlobal (process-specific) bit
837 * 'S' is the shared bit
838 * 'A' in the access permission extension (ATX) bit
839 * 'TEX' remap register control bits
840 * 'AP' is the access protection
841 * 'dom' is the domain for the translation
842 * 'C' is the cache attribute
843 * 'B' is the write buffer attribute
844 */
845
846 #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
847 #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */
848
849 #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */
850
851 /* markers for (invalid) PTE for a page sent to compressor */
852 #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
853 #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
854 #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
855 #define ARM_PTE_IS_COMPRESSED(x) \
856 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
857 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
858 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
859 (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
860 &(x), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
861
862 #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
863 #define ARM_PTE_TYPE 0x00000002 /* small page entry type */
864 #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
865
866 #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
867 #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
868
869 #define ARM_PTE_SHSHIFT 10
870 #define ARM_PTE_SH_MASK 0x00000400 /* shared (SMP) mapping mask */
871 #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
872
873 #define ARM_PTE_CBSHIFT 2
874 #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
875 #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
876
877 #define ARM_PTE_AP0SHIFT 4
878 #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
879 #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
880
881 #define ARM_PTE_AP1SHIFT 5
882 #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
883 #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
884
885 #define ARM_PTE_AP2SHIFT 9
886 #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
887 #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
888
889 /* access protections */
890 #define ARM_PTE_AP(ap) ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) \
891 | ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
892
893 /* mask access protections */
894 #define ARM_PTE_APMASK (ARM_PTE_AP1_MASK \
895 | ARM_PTE_AP2_MASK)
896
897 #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
898 #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
899
900 #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
901 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
902
903 #define ARM_PTE_NXSHIFT 0
904 #define ARM_PTE_NX 0x00000001 /* small page no execute */
905 #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
906
907 #define ARM_PTE_PNXSHIFT 0
908 #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
909 #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
910
911 #define ARM_PTE_TEX0SHIFT 6
912 #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
913 #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
914
915 #define ARM_PTE_TEX1SHIFT 7
916 #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
917 #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
918
919 #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
920 #define ARM_PTE_WRITEABLE ARM_PTE_TEX1
921 #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
922
923 #define ARM_PTE_TEX2SHIFT 8
924 #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
925 #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
926
927 #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
928 #define ARM_PTE_WIRED ARM_PTE_TEX2
929 #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
930
931 /* mask memory attributes index */
932 #define ARM_PTE_ATTRINDX(indx) ((((indx)&0x3)<<ARM_PTE_CBSHIFT) \
933 | ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
934
935 /* mask memory attributes index */
936 #define ARM_PTE_ATTRINDXMASK (ARM_PTE_CB_MASK \
937 | ARM_PTE_TEX0_MASK)
938
939 #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
940 #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
941 #define ARM_SECTION_SIZE (1024*1024) /* 1MB */
942 #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
943
944 #endif
945
946 /*
947 * Format of the Debug Status and Control Register (DBGDSCR)
948 */
949 #define ARM_DBGDSCR_RXFULL (1 << 30)
950 #define ARM_DBGDSCR_TXFULL (1 << 29)
951 #define ARM_DBGDSCR_RXFULL_1 (1 << 27)
952 #define ARM_DBGDSCR_TXFULL_1 (1 << 26)
953 #define ARM_DBGDSCR_PIPEADV (1 << 25)
954 #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24)
955 #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20)
956 #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20)
957 #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20)
958 #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20)
959 #define ARM_DBGDSCR_ADADISCARD (1 << 19)
960 #define ARM_DBGDSCR_NS (1 << 18)
961 #define ARM_DBGDSCR_SPNIDDIS (1 << 17)
962 #define ARM_DBGDSCR_SPIDDIS (1 << 16)
963 #define ARM_DBGDSCR_MDBGEN (1 << 15)
964 #define ARM_DBGDSCR_HDBGEN (1 << 14)
965 #define ARM_DBGDSCR_ITREN (1 << 13)
966 #define ARM_DBGDSCR_UDCCDIS (1 << 12)
967 #define ARM_DBGDSCR_INTDIS (1 << 11)
968 #define ARM_DBGDSCR_DBGACK (1 << 10)
969 #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9)
970 #define ARM_DBGDSCR_UND_1 (1 << 8)
971 #define ARM_DBGDSCR_ADABORT_1 (1 << 7)
972 #define ARM_DBGDSCR_SDABORT_1 (1 << 6)
973 #define ARM_DBGDSCR_MOE_MASK (15 << 2)
974 #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2)
975 #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2)
976 #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2)
977 #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2)
978 #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2)
979 #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2)
980 #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2)
981 #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2)
982 #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2)
983 #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2)
984
985 #define ARM_DBGDSCR_RESTARTED (1 << 1)
986 #define ARM_DBGDSCR_HALTED (1 << 0)
987
988 /*
989 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers
990 * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible
991 */
992 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */
993 #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */
994
995 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */
996 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */
997 #define ARM_DBGBCR_MATCH_MATCH (0 << 22)
998 #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22)
999 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */
1000 #define ARM_DBGBCR_TYPE_IVA (0 << 21)
1001 #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21)
1002 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */
1003 #define ARM_DBG_CR_LINKED_LINKED (1 << 20)
1004 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20)
1005 #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */
1006 #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */
1007 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14)
1008 #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14)
1009 #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14)
1010 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */
1011 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */
1012 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */
1013 #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3)
1014 #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3)
1015 #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3)
1016 #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */
1017 #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */
1018 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEDGED (1 << 1) /* BCR & WCR */
1019 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */
1020 #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */
1021 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */
1022 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0)
1023 #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0)
1024
1025 /*
1026 * Format of the Device Power-down and Reset Status Register (DBGPRSR)
1027 */
1028 #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3)
1029 #define ARM_DBGPRSR_RESET_STATUS (1 << 2)
1030 #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1)
1031 #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0)
1032
1033 /*
1034 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR)
1035 */
1036 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55
1037
1038 /* ARMv7 Debug register map */
1039 #define ARM_DEBUG_OFFSET_DBGDIDR (0x000)
1040 #define ARM_DEBUG_OFFSET_DBGWFAR (0x018)
1041 #define ARM_DEBUG_OFFSET_DBGVCR (0x01C)
1042 #define ARM_DEBUG_OFFSET_DBGECR (0x024)
1043 #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028)
1044 #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C)
1045 #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080)
1046 #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */
1047 #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */
1048 #define ARM_DEBUG_OFFSET_DBGDSCR (0x088)
1049 #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C)
1050 #define ARM_DEBUG_OFFSET_DBGDRCR (0x090)
1051 #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */
1052 #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */
1053 #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */
1054 #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */
1055 #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300)
1056 #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304)
1057 #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308)
1058 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310)
1059 #define ARM_DEBUG_OFFSET_DBGPRSR (0x314)
1060 #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00)
1061 #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0)
1062 #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4)
1063 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0)
1064 #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4)
1065 #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8)
1066 #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8)
1067 #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC)
1068 #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0)
1069 #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4)
1070 #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8)
1071 #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA)
1072 #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC)
1073 #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0)
1074 #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4)
1075 #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8)
1076 #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA)
1077 #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC)
1078
1079 /*
1080 * Media and VFP Feature Register 1 (MVFR1)
1081 */
1082 #define MVFR_ASIMD_HPFP 0x00100000UL
1083
1084 #endif /* _ARM_PROC_REG_H_ */
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