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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_FREE_COPYRIGHT@
24 */
25 /*
26 * @APPLE_FREE_COPYRIGHT@
27 */
28
29 /*
30 Firmware.s
31
32 Handle things that should be treated as an extension of the hardware
33
34 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials.
35 No animal products are used other than rendered otter bile and deep fried pork lard.
36
37 */
38
39 #include <cpus.h>
40 #include <ppc/asm.h>
41 #include <ppc/proc_reg.h>
42 #include <ppc/POWERMAC/mp/MPPlugIn.h>
43 #include <ppc/exception.h>
44 #include <mach/machine/vm_param.h>
45 #include <assym.s>
46
47
48 /*
49 * Here we generate the table of supported firmware calls
50 */
51
52
53
54 .data
55 .align 5 /* Line up on cache line */
56
57 .globl EXT(FWtable)
58
59 EXT(FWtable):
60
61 .globl CutTrace /* Let everyone know 'bout it */
62 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */
63 .long callUnimp /* This was already handled in lowmem_vectors */
64
65 #include <ppc/FirmwareCalls.h>
66
67 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */
68
69 .text
70
71 #define SIMPLESCC 1
72 #define NOTQUITEASSIMPLE 1
73 /*
74 * This routine handles the firmware call routine. It must be entered with IR and DR off,
75 * interruptions disabled, and in supervisor state.
76 *
77 * When we enter, we expect R0 to have call number, and LR
78 * to point to the return. Also, all registers saved in savearea in R13.
79 * R3 is as passed in by the user. All others must be gotten from the save area
80 */
81
82 ENTRY(FirmwareCall, TAG_NO_FRAME_USED)
83
84 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
85 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */
86 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */
87 mflr r11 /* Save the return */
88 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */
89 ble+ goodCall /* Yeah, it is... */
90
91 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
92 blr /* Return for errors... */
93
94 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */
95 lwzx r1,r1,r12 /* Pick up the address of the routine */
96 lwz r4,saver4(r13) /* Pass in caller's R4 */
97 lwz r5,saver5(r13) /* Pass in caller's R5 */
98 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */
99 stw r11,PP_TEMPWORK1(r10) /* Save our return point */
100
101 mtlr r1 /* Put it in the LR */
102 beq- callUnimp /* This one was unimplimented... */
103
104 blrl /* Call the routine... */
105
106 mfsprg r10,0 /* Make sure about the per_proc again */
107 stw r3,saver3(r13) /* Pass back the return code to caller */
108 lwz r11,PP_TEMPWORK1(r10) /* Get our return point */
109 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
110 mtlr r11 /* Set the return */
111 blr /* Bye, dudes... */
112
113 callUnimp: lwz r11,PP_TEMPWORK1(r10) /* Restore the return address */
114 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
115 mtlr r11 /* Restore the LR */
116 blr /* Return for errors... */
117
118 /*
119 * This routine is used to store using a real address. It stores parmeter1 at parameter2.
120 */
121
122 ENTRY(StoreReal, TAG_NO_FRAME_USED)
123
124 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */
125 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */
126 sc /* Do it to it */
127 blr /* Bye bye, Birdie... */
128
129 ENTRY(StoreRealLL, TAG_NO_FRAME_USED)
130
131 stw r3,0(r4) /* Store the word */
132 blr /* Leave... */
133
134 /*
135 * This routine is used to clear a range of physical pages.
136 */
137
138 ENTRY(ClearReal, TAG_NO_FRAME_USED)
139
140 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */
141 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */
142 sc /* Do it to it */
143 blr /* Bye bye, Birdie... */
144
145 ENTRY(ClearRealLL, TAG_NO_FRAME_USED)
146
147 /*
148 * We take the first parameter as a physical address. The second is the length in bytes.
149 * Being crazy, I'll round the address down, and the length up. We could end up clearing
150 * an extra page at the start and one at the end, but we don't really care. If someone
151 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough
152 * to take them at their word and to hell with them.
153 */
154
155 neg r5,r3 /* Negate the address */
156 addi r4,r4,4095 /* Round length up */
157 rlwinm r5,r5,0,20,31 /* Save extra length */
158 rlwinm r3,r3,0,0,19 /* Round the page on down */
159 add r4,r4,r5 /* Add up all extra lengths */
160 li r6,32 /* Get a displacement */
161 rlwinm r4,r4,0,0,19 /* Round the length back down */
162
163 clrloop: subi r4,r4,32 /* Back off a cache line */
164 dcbz 0,r3 /* Do the even line */
165 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */
166 dcbz r6,r3 /* Clear the even line */
167 addi r3,r3,64 /* Move up to every other line */
168 bgt+ clrloop /* Go until we've done it all... */
169
170 blr /* Leave... */
171 /*
172 * This routine will read in 32 byte of real storage.
173 */
174
175 ENTRY(ReadReal, TAG_NO_FRAME_USED)
176
177 mfmsr r0 /* Get the MSR */
178 rlwinm r5,r0,0,28,26 /* Clear DR bit */
179 rlwinm r5,r5,0,17,15 /* Clear EE bit */
180 mtmsr r5 /* Disable EE and DR */
181 isync /* Just make sure about it */
182
183 lwz r5,0(r3) /* Get word 0 */
184 lwz r6,4(r3) /* Get word 1 */
185 lwz r7,8(r3) /* Get word 2 */
186 lwz r8,12(r3) /* Get word 3 */
187 lwz r9,16(r3) /* Get word 4 */
188 lwz r10,20(r3) /* Get word 5 */
189 lwz r11,24(r3) /* Get word 6 */
190 lwz r12,28(r3) /* Get word 7 */
191
192 mtmsr r0 /* Restore original machine state */
193 isync /* Insure goodness */
194
195 stw r5,0(r4) /* Set word 0 */
196 stw r6,4(r4) /* Set word 1 */
197 stw r7,8(r4) /* Set word 2 */
198 stw r8,12(r4) /* Set word 3 */
199 stw r9,16(r4) /* Set word 4 */
200 stw r10,20(r4) /* Set word 5 */
201 stw r11,24(r4) /* Set word 6 */
202 stw r12,28(r4) /* Set word 7 */
203
204 blr
205
206
207 /*
208 * This routine is used to load all 4 DBATs.
209 */
210
211 ENTRY(LoadDBATs, TAG_NO_FRAME_USED)
212
213 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */
214 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */
215 sc /* Do it to it */
216
217 blr /* Bye bye, Birdie... */
218
219 ENTRY(xLoadDBATsLL, TAG_NO_FRAME_USED)
220
221 lwz r4,0(r3) /* Get DBAT 0 high */
222 lwz r5,4(r3) /* Get DBAT 0 low */
223 lwz r6,8(r3) /* Get DBAT 1 high */
224 lwz r7,12(r3) /* Get DBAT 1 low */
225 lwz r8,16(r3) /* Get DBAT 2 high */
226 lwz r9,20(r3) /* Get DBAT 2 low */
227 lwz r10,24(r3) /* Get DBAT 3 high */
228 lwz r11,28(r3) /* Get DBAT 3 low */
229
230 sync /* Common decency and the state law require you to wash your hands */
231 mtdbatu 0,r4 /* Load DBAT 0 high */
232 mtdbatl 0,r5 /* Load DBAT 0 low */
233 mtdbatu 1,r6 /* Load DBAT 1 high */
234 mtdbatl 1,r7 /* Load DBAT 1 low */
235 mtdbatu 2,r8 /* Load DBAT 2 high */
236 mtdbatl 2,r9 /* Load DBAT 2 low */
237 mtdbatu 3,r10 /* Load DBAT 3 high */
238 mtdbatl 3,r11 /* Load DBAT 3 low */
239 sync /* Make sure it's done */
240 isync /* Toss out anything new */
241
242 blr /* Leave... */
243
244 /*
245 * This routine is used to load all 4 IBATs.
246 */
247
248 ENTRY(LoadIBATs, TAG_NO_FRAME_USED)
249
250 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of CreateFakeIO firmware call number */
251 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
252 sc /* Do it to it */
253 blr /* Bye bye, Birdie... */
254
255 ENTRY(xLoadIBATsLL, TAG_NO_FRAME_USED)
256
257 lwz r4,0(r3) /* Get IBAT 0 high */
258 lwz r5,4(r3) /* Get IBAT 0 low */
259 lwz r6,8(r3) /* Get IBAT 1 high */
260 lwz r7,12(r3) /* Get IBAT 1 low */
261 lwz r8,16(r3) /* Get IBAT 2 high */
262 lwz r9,20(r3) /* Get IBAT 2 low */
263 lwz r10,24(r3) /* Get IBAT 3 high */
264 lwz r11,28(r3) /* Get IBAT 3 low */
265
266 sync /* Common decency and the state law require you to wash your hands */
267 mtibatu 0,r4 /* Load IBAT 0 high */
268 mtibatl 0,r5 /* Load IBAT 0 low */
269 mtibatu 1,r6 /* Load IBAT 1 high */
270 mtibatl 1,r7 /* Load IBAT 1 low */
271 mtibatu 2,r8 /* Load IBAT 2 high */
272 mtibatl 2,r9 /* Load IBAT 2 low */
273 mtibatu 3,r10 /* Load IBAT 3 high */
274 mtibatl 3,r11 /* Load IBAT 3 low */
275 sync /* Make sure it's done */
276 isync /* Toss out anything new */
277
278 blr /* Leave... */
279
280
281 /*
282 * This is the glue to call the CutTrace firmware call
283 */
284
285 ENTRY(dbgTrace, TAG_NO_FRAME_USED)
286
287 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */
288 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */
289 sc /* Do it to it */
290 blr /* Bye bye, Birdie... */
291
292 /*
293 * This is the glue to create a fake I/O interruption
294 */
295
296 ENTRY(CreateFakeIO, TAG_NO_FRAME_USED)
297
298 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */
299 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */
300 sc /* Do it to it */
301 blr /* Bye bye, Birdie... */
302
303 /*
304 * This is the glue to create a fake Dec interruption
305 */
306
307 ENTRY(CreateFakeDEC, TAG_NO_FRAME_USED)
308
309 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
310 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
311 sc /* Do it to it */
312 blr /* Bye bye, Birdie... */
313
314
315 /*
316 * This is the glue to create a shutdown context
317 */
318
319 ENTRY(CreateShutdownCTX, TAG_NO_FRAME_USED)
320
321 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */
322 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */
323 sc /* Do it to it */
324 blr /* Bye bye, Birdie... */
325
326 /*
327 * Used to initialize the SCC for debugging output
328 */
329
330
331 ENTRY(fwSCCinit, TAG_NO_FRAME_USED)
332
333 mfmsr r8 /* Save the MSR */
334 mr. r3,r3 /* See if printer or modem */
335 rlwinm r12,r8,0,28,25 /* Turn off translation */
336 lis r10,0xF301 /* Set the top part */
337 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
338 #if 0
339 mtmsr r12 /* Smash the MSR */
340 isync /* Make it clean */
341 #endif
342
343 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
344 beq+ fwSCCprnt /* It sure are... */
345 ori r10,r10,0x0002 /* Move it over to the modem port */
346
347 fwSCCprnt: dcbf 0,r10 /* Insure it is out */
348 sync
349 eieio
350 dcbi 0,r10 /* Toss it */
351 sync
352
353
354 li r7,0x09 /* Set the register */
355 stb r7,0(r10) /* Set the register */
356 dcbf 0,r10 /* Force it out */
357 sync /* Make sure it's out there */
358 dcbi 0,r10
359 eieio
360
361 li r7,0x80 /* Reset channel A */
362 stb r7,0(r10) /* Set the register */
363 dcbf 0,r10 /* Force it out */
364 sync /* Make sure it's out there */
365 dcbi 0,r10
366 eieio
367
368 li r7,0x04 /* Set the register */
369 stb r7,0(r10) /* Set the register */
370 dcbf 0,r10 /* Force it out */
371 sync /* Make sure it's out there */
372 dcbi 0,r10
373 eieio
374
375 li r7,0x44 /* x16 clock, 1 stop bit */
376 stb r7,0(r10) /* Set the register */
377 dcbf 0,r10 /* Force it out */
378 sync /* Make sure it's out there */
379 dcbi 0,r10
380 eieio
381
382 li r7,0x03 /* Set the register */
383 stb r7,0(r10) /* Set the register */
384 dcbf 0,r10 /* Force it out */
385 sync /* Make sure it's out there */
386 dcbi 0,r10
387 eieio
388
389 li r7,0xC0 /* 8 bits per char */
390 stb r7,0(r10) /* Set the register */
391 dcbf 0,r10 /* Force it out */
392 sync /* Make sure it's out there */
393 dcbi 0,r10
394 eieio
395
396 li r7,0x05 /* Set the register */
397 stb r7,0(r10) /* Set the register */
398 dcbf 0,r10 /* Force it out */
399 sync /* Make sure it's out there */
400 dcbi 0,r10
401 eieio
402
403 li r7,0xE2 /* DTR mode, 8bit/char */
404 stb r7,0(r10) /* Set the register */
405 dcbf 0,r10 /* Force it out */
406 sync /* Make sure it's out there */
407 dcbi 0,r10
408 eieio
409
410 li r7,0x02 /* Set the register */
411 stb r7,0(r10) /* Set the register */
412 dcbf 0,r10 /* Force it out */
413 sync /* Make sure it's out there */
414 dcbi 0,r10
415 eieio
416
417 li r7,0x00 /* Vector 0 */
418 stb r7,0(r10) /* Set the register */
419 dcbf 0,r10 /* Force it out */
420 sync /* Make sure it's out there */
421 dcbi 0,r10
422 eieio
423
424 li r7,0x0A /* Set the register */
425 stb r7,0(r10) /* Set the register */
426 dcbf 0,r10 /* Force it out */
427 sync /* Make sure it's out there */
428 dcbi 0,r10
429 eieio
430
431 li r7,0x00 /* Clear misc controls */
432 stb r7,0(r10) /* Set the register */
433 dcbf 0,r10 /* Force it out */
434 sync /* Make sure it's out there */
435 dcbi 0,r10
436 eieio
437
438 li r7,0x0B /* Set the register */
439 stb r7,0(r10) /* Set the register */
440 dcbf 0,r10 /* Force it out */
441 sync /* Make sure it's out there */
442 dcbi 0,r10
443 eieio
444
445 li r7,0x50 /* B/R gen T/R */
446 stb r7,0(r10) /* Set the register */
447 dcbf 0,r10 /* Force it out */
448 sync /* Make sure it's out there */
449 dcbi 0,r10
450 eieio
451
452 li r7,0x0C /* Set the register */
453 stb r7,0(r10) /* Set the register */
454 dcbf 0,r10 /* Force it out */
455 sync /* Make sure it's out there */
456 dcbi 0,r10
457 eieio
458
459 li r7,0x0A /* 9600 baud low */
460 stb r7,0(r10) /* Set the register */
461 dcbf 0,r10 /* Force it out */
462 sync /* Make sure it's out there */
463 dcbi 0,r10
464 eieio
465
466 li r7,0x0D /* Set the register */
467 stb r7,0(r10) /* Set the register */
468 dcbf 0,r10 /* Force it out */
469 sync /* Make sure it's out there */
470 dcbi 0,r10
471 eieio
472
473 li r7,0x00 /* 9600 baud high */
474 stb r7,0(r10) /* Set the register */
475 dcbf 0,r10 /* Force it out */
476 sync /* Make sure it's out there */
477 dcbi 0,r10
478 eieio
479
480 li r7,0x03 /* Set the register */
481 stb r7,0(r10) /* Set the register */
482 dcbf 0,r10 /* Force it out */
483 sync /* Make sure it's out there */
484 dcbi 0,r10
485 eieio
486
487 li r7,0xC1 /* 8 bits/char, Rx enable */
488 stb r7,0(r10) /* Set the register */
489 dcbf 0,r10 /* Force it out */
490 sync /* Make sure it's out there */
491 dcbi 0,r10
492 eieio
493
494 li r7,0x05 /* Set the register */
495 stb r7,0(r10) /* Set the register */
496 dcbf 0,r10 /* Force it out */
497 sync /* Make sure it's out there */
498 dcbi 0,r10
499 eieio
500
501 li r7,0xEA /* 8 bits/char, Tx enable */
502 stb r7,0(r10) /* Set the register */
503 dcbf 0,r10 /* Force it out */
504 sync /* Make sure it's out there */
505 dcbi 0,r10
506 eieio
507
508 li r7,0x0E /* Set the register */
509 stb r7,0(r10) /* Set the register */
510 dcbf 0,r10 /* Force it out */
511 sync /* Make sure it's out there */
512 dcbi 0,r10
513 eieio
514
515 li r7,0x01 /* BR rate gen enable */
516 stb r7,0(r10) /* Set the register */
517 dcbf 0,r10 /* Force it out */
518 sync /* Make sure it's out there */
519 dcbi 0,r10
520 eieio
521
522 li r7,0x0F /* Set the register */
523 stb r7,0(r10) /* Set the register */
524 dcbf 0,r10 /* Force it out */
525 sync /* Make sure it's out there */
526 dcbi 0,r10
527 eieio
528
529 li r7,0x00 /* ints off */
530 stb r7,0(r10) /* Set the register */
531 dcbf 0,r10 /* Force it out */
532 sync /* Make sure it's out there */
533 dcbi 0,r10
534 eieio
535
536 li r7,0x10 /* Reset ext/stat ints */
537 stb r7,0(r10) /* Set the register */
538 dcbf 0,r10 /* Force it out */
539 sync /* Make sure it's out there */
540 dcbi 0,r10
541 eieio
542
543 li r7,0x10 /* Reset ext/stat ints */
544 stb r7,0(r10) /* Set the register */
545 dcbf 0,r10 /* Force it out */
546 sync /* Make sure it's out there */
547 dcbi 0,r10
548 eieio
549
550 li r7,0x01 /* Set the register */
551 stb r7,0(r10) /* Set the register */
552 dcbf 0,r10 /* Force it out */
553 sync /* Make sure it's out there */
554 dcbi 0,r10
555 eieio
556
557 li r7,0x10 /* int on Rx, no Tx int enable */
558 stb r7,0(r10) /* Set the register */
559 dcbf 0,r10 /* Force it out */
560 sync /* Make sure it's out there */
561 dcbi 0,r10
562 eieio
563
564 li r7,0x09 /* Set the register */
565 stb r7,0(r10) /* Set the register */
566 dcbf 0,r10 /* Force it out */
567 sync /* Make sure it's out there */
568 dcbi 0,r10
569 eieio
570
571 li r7,0x0A /* int on Rx, Tx int enable */
572 stb r7,0(r10) /* Set the register */
573 dcbf 0,r10 /* Force it out */
574 sync /* Master enable, no vector */
575 dcbi 0,r10
576 eieio
577
578 li r7,0x09 /* Set the register */
579 stb r7,0(r10) /* Set the register */
580 dcbf 0,r10 /* Force it out */
581 sync /* Make sure it's out there */
582 dcbi 0,r10
583 eieio
584
585 li r7,0x02 /* No vector */
586 stb r7,0(r10) /* Set the register */
587 dcbf 0,r10 /* Force it out */
588 sync /* Master enable, no vector */
589 dcbi 0,r10
590 eieio
591
592 lbz r7,0(r10) /* Clear interrupts */
593 sync /* Master enable, no vector */
594 dcbi 0,r10
595 eieio
596
597 wSCCrdy: eieio /* Barricade it */
598 lbz r7,0(r10) /* Get current status */
599 dcbi 0,r10
600 sync
601 andi. r7,r7,0x04 /* Is transmitter empty? */
602 beq wSCCrdy /* Nope... */
603
604 eieio
605
606 #if 0
607 mtmsr r8 /* Restore 'rupts and TR */
608 isync
609 #endif
610 blr /* Leave... */
611
612 /*
613 * This routine is used to write debug output to either the modem or printer port.
614 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex
615 */
616
617 ENTRY(dbgDisp, TAG_NO_FRAME_USED)
618
619 mr r12,r0 /* Keep R0 pristene */
620 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */
621 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */
622
623 sc /* Go display the stuff */
624
625 mr r0,r12 /* Restore R0 */
626 blr /* Return... */
627
628 /* Here's the low-level part of dbgDisp */
629
630 ENTRY(dbgDispLL, TAG_NO_FRAME_USED)
631
632 dbgDispInt: mfmsr r8 /* Save the MSR */
633
634 #if 0
635 lis r10,0xF301 /* (TEST/DEBUG) */
636 ori r10,r10,0x2002 /* (TEST/DEBUG) */
637 dcbf 0,r10 /* (TEST/DEBUG) */
638 sync /* (TEST/DEBUG) */
639 dcbi 0,r10 /* (TEST/DEBUG) */
640 eieio /* (TEST/DEBUG) */
641 li r7,0x35 /* (TEST/DEBUG) */
642 stb r7,4(r10) /* (TEST/DEBUG) */
643
644 lis r7,10 /* (TEST/DEBUG) */
645 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
646 mr. r7,r7 /* (TEST/DEBUG) */
647 bne- spw6 /* (TEST/DEBUG) */
648 dcbf 0,r10 /* (TEST/DEBUG) */
649 sync /* (TEST/DEBUG) */
650 dcbi 0,r10 /* (TEST/DEBUG) */
651 eieio /* (TEST/DEBUG) */
652 #endif
653
654 rlwinm r12,r8,0,28,25 /* Turn off translation */
655 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
656
657 mflr r11 /* Save the link register */
658
659 #if 0
660 mr r7,r12 /* (TEST/DEBUG) */
661 bl dumpr7 /* (TEST/DEBUG) */
662 #endif
663
664 mr. r3,r3 /* See if printer or modem */
665 lis r10,0xF301 /* Set the top part */
666 mr r3,r4 /* Copy the ID parameter */
667
668 #if 0
669 mr r9,r12 /* (TEST/DEBUG) */
670
671 mtmsr r12 /* (TEST/DEBUG) */
672 isync /* (TEST/DEBUG) */
673
674 #if 0
675 mtmsr r8 /* (TEST/DEBUG) */
676 isync /* (TEST/DEBUG) */
677 #endif
678
679 lis r12,0xF301 /* (TEST/DEBUG) */
680 ori r12,r12,0x2002 /* (TEST/DEBUG) */
681 #if 1
682 dcbf 0,r12 /* (TEST/DEBUG) */
683 sync /* (TEST/DEBUG) */
684 dcbi 0,r12 /* (TEST/DEBUG) */
685 #endif
686
687 xqrw1: eieio /* (TEST/DEBUG) */
688 lbz r7,0(r12) /* (TEST/DEBUG) */
689 dcbi 0,r12 /* (TEST/DEBUG) */
690 sync /* (TEST/DEBUG) */
691 andi. r7,r7,0x04 /* (TEST/DEBUG) */
692 beq xqrw1 /* (TEST/DEBUG) */
693
694 eieio /* (TEST/DEBUG) */
695 li r7,0x36 /* (TEST/DEBUG) */
696 stb r7,4(r12) /* (TEST/DEBUG) */
697 eieio
698 dcbf 0,r12 /* (TEST/DEBUG) */
699 sync /* (TEST/DEBUG) */
700 dcbi 0,r12 /* (TEST/DEBUG) */
701 eieio /* (TEST/DEBUG) */
702
703
704 lis r7,10 /* (TEST/DEBUG) */
705 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
706 mr. r7,r7 /* (TEST/DEBUG) */
707 bne- spw7 /* (TEST/DEBUG) */
708 dcbf 0,r12 /* (TEST/DEBUG) */
709 sync /* (TEST/DEBUG) */
710 dcbi 0,r12 /* (TEST/DEBUG) */
711 eieio /* (TEST/DEBUG) */
712 mr r12,r9 /* (TEST/DEBUG) */
713 #endif
714
715 mtmsr r12 /* Smash the MSR */
716 isync /* Make it clean */
717
718
719 #if SIMPLESCC && !NOTQUITEASSIMPLE
720 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */
721 #else
722 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
723 #endif
724 beq+ dbgDprintr /* It sure are... */
725 #if SIMPLESCC && !NOTQUITEASSIMPLE
726 ori r10,r10,0x0020 /* Move it over to the modem port */
727 #else
728 ori r10,r10,0x0002 /* Move it over to the modem port */
729
730 #if !NOTQUITEASSIMPLE
731 lis r7,0xF300 /* Address of SCC rounded to 128k */
732 ori r7,r7,0x0032 /* Make it cache inhibited */
733 mtdbatl 3,r7 /* Load DBAT 3 low */
734 lis r7,0xF300 /* Address of SCC rounded to 128k */
735 ori r7,r7,0x0002 /* Make it supervisor only */
736 mtdbatu 3,r7 /* Load DBAT 3 high */
737 ori r12,r12,0x0010 /* Turn on DR */
738 mtmsr r12 /* Smash the MSR */
739 isync /* Make it clean */
740
741 #endif
742 #endif
743
744 dbgDprintr: sync
745 #if 0
746 mr r7,r10 /* (TEST/DEBUG) */
747 bl dumpr7 /* (TEST/DEBUG) */
748 #endif
749
750 dcbi 0,r10 /* Toss it */
751 eieio
752
753 #if 0
754 lis r12,0xF301 /* (TEST/DEBUG) */
755 ori r12,r12,0x2002 /* (TEST/DEBUG) */
756 dcbf 0,r12 /* (TEST/DEBUG) */
757 sync /* (TEST/DEBUG) */
758 dcbi 0,r12 /* (TEST/DEBUG) */
759 eieio /* (TEST/DEBUG) */
760 li r7,0x37 /* (TEST/DEBUG) */
761 stb r7,4(r12) /* (TEST/DEBUG) */
762
763 lis r7,12 /* (TEST/DEBUG) */
764 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
765 mr. r7,r7 /* (TEST/DEBUG) */
766 bne- spw8 /* (TEST/DEBUG) */
767 dcbf 0,r12 /* (TEST/DEBUG) */
768 sync /* (TEST/DEBUG) */
769 dcbi 0,r12 /* (TEST/DEBUG) */
770 eieio /* (TEST/DEBUG) */
771 #endif
772
773
774 /* Print the ID parameter */
775
776 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
777 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
778
779 lwarx r7,0,r12 ; ?
780
781 ddwait0: lwarx r7,0,r12 /* Get the lock */
782 mr. r7,r7 /* Is it locked? */
783 bne- ddwait0 /* Yup... */
784 stwcx. r12,0,r12 /* Try to get it */
785 bne- ddwait0 /* Nope, start all over... */
786
787 #if 0
788 dcbf 0,r10 /* (TEST/DEBUG) */
789 sync /* (TEST/DEBUG) */
790 dcbi 0,r10 /* (TEST/DEBUG) */
791 eieio /* (TEST/DEBUG) */
792 li r7,0x38 /* (TEST/DEBUG) */
793 stb r7,6(r10) /* (TEST/DEBUG) */
794
795 lis r7,10 /* (TEST/DEBUG) */
796 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
797 mr. r7,r7 /* (TEST/DEBUG) */
798 bne- spwa /* (TEST/DEBUG) */
799 dcbf 0,r10 /* (TEST/DEBUG) */
800 sync /* (TEST/DEBUG) */
801 dcbi 0,r10 /* (TEST/DEBUG) */
802 eieio /* (TEST/DEBUG) */
803 #endif
804
805 rlwinm r3,r3,8,0,31 /* Get the first character */
806 bl dbgDchar /* Print it */
807 rlwinm r3,r3,8,0,31 /* Get the second character */
808 bl dbgDchar /* Print it */
809 rlwinm r3,r3,8,0,31 /* Get the third character */
810 bl dbgDchar /* Print it */
811 rlwinm r3,r3,8,0,31 /* Get the fourth character */
812 bl dbgDchar /* Print it */
813
814 li r3,0x20 /* Get a space for a separator */
815 bl dbgDchar /* Print it */
816 bl dbg4byte /* Print register 5 in hex */
817
818 li r3,0x0A /* Linefeed */
819 bl dbgDchar /* Send it */
820 li r3,0x0D /* Carriage return */
821 bl dbgDchar /* Send it */
822
823 mtlr r11 /* Get back the return */
824 #if !SIMPLESCC && !NOTQUITEASSIMPLE
825 li r7,0 /* Get a zero */
826 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
827 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
828 #endif
829 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
830 li r7,0 /* Get a zero */
831 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
832 dcbi 0,r10 /* ? */
833 stw r7,0(r12) /* Release the display lock */
834 mtmsr r8 /* Restore the MSR */
835 isync /* Wait for it */
836 blr /* Leave... */
837
838
839 dbg4byte: mflr r12 /* Save the return */
840
841 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */
842 li r6,8 /* Set number of hex digits to dump */
843 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */
844
845 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */
846 subi r6,r6,1 /* Back down the count */
847 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */
848 lbzx r3,r4,r3 /* Convert to ascii */
849 bl dbgDchar /* Print it */
850 mr. r6,r6 /* Any more? */
851 bne+ dbgDnext /* Convert 'em all... */
852
853 li r3,0x20 /* Space */
854 bl dbgDchar /* Send it */
855 mtlr r12 /* Restore LR */
856 blr /* Return... */
857
858 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */
859
860 dbgDchar:
861 #if SIMPLESCC && !NOTQUITEASSIMPLE
862 stb r3,0(r10) /* ? */
863 dcbf 0,r10 /* Force it out */
864 sync /* Make sure it's out there */
865
866 lis r7,3 /* Get enough for about 1ms */
867
868 dbgDchar0: addi r7,r7,-1 /* Count down */
869 mr. r7,r7 /* Waited long enough? */
870 bgt+ dbgDchar0 /* Nope... */
871 #endif
872 #if NOTQUITEASSIMPLE
873 #if 0
874 li r7,0x01 /* ? */
875 stb r7,0(r10) /* ? */
876 dcbf 0,r10 /* Force it out */
877 sync /* Make sure it's out there */
878 dcbi 0,r10
879 eieio
880
881 lbz r7,0(r10) /* ? */
882 dcbi 0,r10 /* Force it out */
883 sync /* kill it off */
884 eieio
885
886 li r7,0x00 /* ? */
887 stb r7,0(r10) /* ? */
888 dcbf 0,r10 /* Force it out */
889 sync /* Make sure it's out there */
890 dcbi 0,r10
891 eieio
892
893 lbz r7,0(r10) /* ? */
894 dcbi 0,r10 /* Force it out */
895 sync /* kill it off */
896 eieio
897 #endif
898
899 qrw1: eieio /* Barricade it */
900 lbz r7,0(r10) /* ? */
901 dcbi 0,r10
902 sync
903 andi. r7,r7,0x04 /* ? */
904 beq qrw1 /* Nope... */
905
906 eieio
907
908 stb r3,4(r10) /* ? */
909 dcbf 0,r10 /* Force it out */
910 sync /* Make sure it's out there */
911 dcbi 0,r10
912 eieio
913
914 qrw2: eieio /* Barricade it */
915 lbz r7,0(r10) /* ? */
916 dcbi 0,r10
917 sync
918 andi. r7,r7,0x04 /* ? */
919 beq qrw2 /* Nope... */
920
921 #if 0
922 eieio
923 li r7,0x10 /* ? */
924 stb r7,0(r10) /* ? */
925 dcbf 0,r10 /* Force it out */
926 sync /* Make sure it's out there */
927 dcbi 0,r10
928 eieio
929
930 lbz r7,0(r10) /* ? */
931 dcbi 0,r10 /* Force it out */
932 sync /* kill it off */
933 eieio
934 #endif
935
936 lis r7,0x0080 /* ? */
937 lis r9,0xF300 /* ? */
938 ori r7,r7,0x010F /* ? */
939 stw r7,0x28(r9) /* ? */
940 dcbf 0,r10 /* Force it out */
941 sync /* Make sure it's out there */
942 dcbi 0,r10
943 eieio
944
945 #endif
946 #if !SIMPLESCC && !NOTQUITEASSIMPLE
947 rlwinm r9,r10,0,0,29 /* Get channel a */
948 eieio /* Barricade it */
949
950 li r7,0x03 /* ? */
951 stb r7,0(r9) /* ? */
952 eieio /* Barricade it */
953
954 lbz r7,0(r9) /* ? */
955
956 eieio /* Barricade it */
957 lbz r7,0(r9) /* ? */
958
959 dchrw1: eieio /* Barricade it */
960 lbz r7,0(r10) /* ? */
961 andi. r7,r7,0x04 /* ? */
962 beq dchrw1 /* Nope... */
963
964 stb r3,4(r10) /* ? */
965 sync /* Make sure it's there */
966 eieio /* Don't get confused */
967
968 dchrw2: eieio /* Barricade it */
969 lbz r7,0(r10) /* ? */
970 andi. r7,r7,0x04 /* ? */
971 beq dchrw2 /* Nope... */
972
973 eieio /* Avoid confusion */
974 lbz r7,0(r10) /* ? */
975 andi. r7,r7,0x40 /* ? */
976 beq+ nounder /* Nope... */
977
978 eieio /* Avoid confusion */
979 li r7,0xC0 /* ? */
980 stb r7,0(r10) /* ? */
981
982 nounder: eieio /* Avoid confusion */
983 li r7,0x10 /* ? */
984 stb r7,0(r10) /* ? */
985
986 eieio /* Avoid confusion */
987 li r7,0x38 /* ? */
988 stb r7,0(r9) /* ? */
989
990 eieio /* Avoid confusion */
991 li r7,0x30 /* ? */
992 stb r7,0(r10) /* ? */
993
994 eieio /* Avoid confusion */
995 li r7,0x20 /* ? */
996 stb r7,0(r10) /* ? */
997 eieio /* Avoid confusion */
998 sync
999
1000 #endif
1001 blr /* Return */
1002
1003 .globl hexTab
1004
1005 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */
1006
1007
1008 /*
1009 * Dumps all the registers in the savearea in R13
1010 */
1011
1012
1013 ENTRY(dbgRegsLL, TAG_NO_FRAME_USED)
1014
1015 li r3,0 /* ? */
1016 bl dbgRegsCm /* Join on up... */
1017
1018 /*
1019 * Note that we bypass the normal return 'cause we don't wanna mess up R3
1020 */
1021 mfsprg r11,0 /* Get the per_proc */
1022 lwz r11,PP_TEMPWORK1(r11) /* Get our return point */
1023 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
1024 mtlr r11 /* Set the return */
1025 blr /* Bye, dudes... */
1026
1027 ENTRY(dbgRegs, TAG_NO_FRAME_USED)
1028
1029 dbgRegsCm: mfmsr r8 /* Save the MSR */
1030 mr. r3,r3 /* ? */
1031 rlwinm r12,r8,0,28,25 /* Turn off translation */
1032 lis r10,0xF301 /* Set the top part */
1033 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
1034 mtmsr r12 /* Smash the MSR */
1035 isync /* Make it clean */
1036 #if SIMPLESCC && !NOTQUITEASSIMPLE
1037 ori r10,r10,0x3010 /* ? */
1038 #else
1039 ori r10,r10,0x2000 /* ? */
1040 #endif
1041 mflr r11 /* Save the link register */
1042 beq+ dbgDprints /* It sure are... */
1043 #if SIMPLESCC && !NOTQUITEASSIMPLE
1044 ori r10,r10,0x0020 /* ? */
1045 #else
1046 ori r10,r10,0x0002 /* ? */
1047
1048 dcbf 0,r10 /* Insure it is out */
1049 sync
1050 dcbi 0,r10 /* Toss it */
1051 #if !NOTQUITEASSIMPLE
1052 lis r7,0xF300 /* ? */
1053 ori r7,r7,0x0032 /* ? */
1054 mtdbatl 3,r7 /* ? */
1055 lis r7,0xF300 /* ? */
1056 ori r7,r7,0x0002 /* ? */
1057 mtdbatu 3,r7 /* ? */
1058 ori r12,r12,0x0010 /* ? */
1059 mtmsr r12 /* ? */
1060 isync /* ? */
1061 #endif
1062 #endif
1063
1064 dbgDprints:
1065 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1066 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1067
1068 lwarx r5,0,r3 ; ?
1069 ddwait1: lwarx r5,0,r3 /* Get the lock */
1070 mr. r5,r5 /* Is it locked? */
1071 bne- ddwait1 /* Yup... */
1072 stwcx. r3,0,r3 /* Try to get it */
1073 bne- ddwait1 /* Nope, start all over... */
1074
1075 li r3,0x52 /* Print eyecatcher */
1076 bl dbgDchar /* Send it */
1077 li r3,0x65 /* Print eyecatcher */
1078 bl dbgDchar /* Send it */
1079 li r3,0x67 /* Print eyecatcher */
1080 bl dbgDchar /* Send it */
1081 li r3,0x73 /* Print eyecatcher */
1082 bl dbgDchar /* Send it */
1083 li r3,0x20 /* Print eyecatcher */
1084 bl dbgDchar /* Send it */
1085
1086 lwz r5,saver0(r13) /* Do register */
1087 bl dbg4byte /* Print */
1088 lwz r5,saver1(r13) /* Do register */
1089 bl dbg4byte /* Print */
1090 lwz r5,saver2(r13) /* Do register */
1091 bl dbg4byte /* Print */
1092 lwz r5,saver3(r13) /* Do register */
1093 bl dbg4byte /* Print */
1094 li r3,0x0A /* Linefeed */
1095 bl dbgDchar /* Send it */
1096 li r3,0x0D /* Carriage return */
1097 bl dbgDchar /* Send it */
1098
1099 li r3,0x20 /* Print eyecatcher */
1100 bl dbgDchar /* Send it */
1101 li r3,0x20 /* Print eyecatcher */
1102 bl dbgDchar /* Send it */
1103 li r3,0x20 /* Print eyecatcher */
1104 bl dbgDchar /* Send it */
1105 li r3,0x20 /* Print eyecatcher */
1106 bl dbgDchar /* Send it */
1107 li r3,0x20 /* Print eyecatcher */
1108 bl dbgDchar /* Send it */
1109 lwz r5,saver4(r13) /* Do register */
1110 bl dbg4byte /* Print */
1111 lwz r5,saver5(r13) /* Do register */
1112 bl dbg4byte /* Print */
1113 lwz r5,saver6(r13) /* Do register */
1114 bl dbg4byte /* Print */
1115 lwz r5,saver7(r13) /* Do register */
1116 bl dbg4byte /* Print */
1117 li r3,0x0A /* Linefeed */
1118 bl dbgDchar /* Send it */
1119 li r3,0x0D /* Carriage return */
1120 bl dbgDchar /* Send it */
1121
1122 li r3,0x20 /* Print eyecatcher */
1123 bl dbgDchar /* Send it */
1124 li r3,0x20 /* Print eyecatcher */
1125 bl dbgDchar /* Send it */
1126 li r3,0x20 /* Print eyecatcher */
1127 bl dbgDchar /* Send it */
1128 li r3,0x20 /* Print eyecatcher */
1129 bl dbgDchar /* Send it */
1130 li r3,0x20 /* Print eyecatcher */
1131 bl dbgDchar /* Send it */
1132 lwz r5,saver8(r13) /* Do register */
1133 bl dbg4byte /* Print */
1134 lwz r5,saver9(r13) /* Do register */
1135 bl dbg4byte /* Print */
1136 lwz r5,saver10(r13) /* Do register */
1137 bl dbg4byte /* Print */
1138 lwz r5,saver11(r13) /* Do register */
1139 bl dbg4byte /* Print */
1140 li r3,0x0A /* Linefeed */
1141 bl dbgDchar /* Send it */
1142 li r3,0x0D /* Carriage return */
1143 bl dbgDchar /* Send it */
1144
1145 li r3,0x20 /* Print eyecatcher */
1146 bl dbgDchar /* Send it */
1147 li r3,0x20 /* Print eyecatcher */
1148 bl dbgDchar /* Send it */
1149 li r3,0x20 /* Print eyecatcher */
1150 bl dbgDchar /* Send it */
1151 li r3,0x20 /* Print eyecatcher */
1152 bl dbgDchar /* Send it */
1153 li r3,0x20 /* Print eyecatcher */
1154 bl dbgDchar /* Send it */
1155 lwz r5,saver12(r13) /* Do register */
1156 bl dbg4byte /* Print */
1157 lwz r5,saver13(r13) /* Do register */
1158 bl dbg4byte /* Print */
1159 lwz r5,saver14(r13) /* Do register */
1160 bl dbg4byte /* Print */
1161 lwz r5,saver15(r13) /* Do register */
1162 bl dbg4byte /* Print */
1163 li r3,0x0A /* Linefeed */
1164 bl dbgDchar /* Send it */
1165 li r3,0x0D /* Carriage return */
1166 bl dbgDchar /* Send it */
1167
1168 li r3,0x20 /* Print eyecatcher */
1169 bl dbgDchar /* Send it */
1170 li r3,0x20 /* Print eyecatcher */
1171 bl dbgDchar /* Send it */
1172 li r3,0x20 /* Print eyecatcher */
1173 bl dbgDchar /* Send it */
1174 li r3,0x20 /* Print eyecatcher */
1175 bl dbgDchar /* Send it */
1176 li r3,0x20 /* Print eyecatcher */
1177 bl dbgDchar /* Send it */
1178 lwz r5,saver16(r13) /* Do register */
1179 bl dbg4byte /* Print */
1180 lwz r5,saver17(r13) /* Do register */
1181 bl dbg4byte /* Print */
1182 lwz r5,saver18(r13) /* Do register */
1183 bl dbg4byte /* Print */
1184 lwz r5,saver19(r13) /* Do register */
1185 bl dbg4byte /* Print */
1186 li r3,0x0A /* Linefeed */
1187 bl dbgDchar /* Send it */
1188 li r3,0x0D /* Carriage return */
1189 bl dbgDchar /* Send it */
1190
1191 li r3,0x20 /* Print eyecatcher */
1192 bl dbgDchar /* Send it */
1193 li r3,0x20 /* Print eyecatcher */
1194 bl dbgDchar /* Send it */
1195 li r3,0x20 /* Print eyecatcher */
1196 bl dbgDchar /* Send it */
1197 li r3,0x20 /* Print eyecatcher */
1198 bl dbgDchar /* Send it */
1199 li r3,0x20 /* Print eyecatcher */
1200 bl dbgDchar /* Send it */
1201 lwz r5,saver20(r13) /* Do register */
1202 bl dbg4byte /* Print */
1203 lwz r5,saver21(r13) /* Do register */
1204 bl dbg4byte /* Print */
1205 lwz r5,saver22(r13) /* Do register */
1206 bl dbg4byte /* Print */
1207 lwz r5,saver23(r13) /* Do register */
1208 bl dbg4byte /* Print */
1209 li r3,0x0A /* Linefeed */
1210 bl dbgDchar /* Send it */
1211 li r3,0x0D /* Carriage return */
1212 bl dbgDchar /* Send it */
1213
1214 li r3,0x20 /* Print eyecatcher */
1215 bl dbgDchar /* Send it */
1216 li r3,0x20 /* Print eyecatcher */
1217 bl dbgDchar /* Send it */
1218 li r3,0x20 /* Print eyecatcher */
1219 bl dbgDchar /* Send it */
1220 li r3,0x20 /* Print eyecatcher */
1221 bl dbgDchar /* Send it */
1222 li r3,0x20 /* Print eyecatcher */
1223 bl dbgDchar /* Send it */
1224 lwz r5,saver24(r13) /* Do register */
1225 bl dbg4byte /* Print */
1226 lwz r5,saver25(r13) /* Do register */
1227 bl dbg4byte /* Print */
1228 lwz r5,saver26(r13) /* Do register */
1229 bl dbg4byte /* Print */
1230 lwz r5,saver27(r13) /* Do register */
1231 bl dbg4byte /* Print */
1232 li r3,0x0A /* Linefeed */
1233 bl dbgDchar /* Send it */
1234 li r3,0x0D /* Carriage return */
1235 bl dbgDchar /* Send it */
1236
1237 li r3,0x20 /* Print eyecatcher */
1238 bl dbgDchar /* Send it */
1239 li r3,0x20 /* Print eyecatcher */
1240 bl dbgDchar /* Send it */
1241 li r3,0x20 /* Print eyecatcher */
1242 bl dbgDchar /* Send it */
1243 li r3,0x20 /* Print eyecatcher */
1244 bl dbgDchar /* Send it */
1245 li r3,0x20 /* Print eyecatcher */
1246 bl dbgDchar /* Send it */
1247 lwz r5,saver28(r13) /* Do register */
1248 bl dbg4byte /* Print */
1249 lwz r5,saver29(r13) /* Do register */
1250 bl dbg4byte /* Print */
1251 lwz r5,saver30(r13) /* Do register */
1252 bl dbg4byte /* Print */
1253 lwz r5,saver31(r13) /* Do register */
1254 bl dbg4byte /* Print */
1255 li r3,0x0A /* Linefeed */
1256 bl dbgDchar /* Send it */
1257 li r3,0x0D /* Carriage return */
1258 bl dbgDchar /* Send it */
1259
1260 /* Segment registers */
1261
1262 li r3,0x53 /* Print eyecatcher */
1263 bl dbgDchar /* Send it */
1264 li r3,0x65 /* Print eyecatcher */
1265 bl dbgDchar /* Send it */
1266 li r3,0x67 /* Print eyecatcher */
1267 bl dbgDchar /* Send it */
1268 li r3,0x73 /* Print eyecatcher */
1269 bl dbgDchar /* Send it */
1270 li r3,0x20 /* Print eyecatcher */
1271 bl dbgDchar /* Send it */
1272
1273 lwz r5,savesr0(r13) /* Do register */
1274 bl dbg4byte /* Print */
1275 lwz r5,savesr1(r13) /* Do register */
1276 bl dbg4byte /* Print */
1277 lwz r5,savesr2(r13) /* Do register */
1278 bl dbg4byte /* Print */
1279 lwz r5,savesr3(r13) /* Do register */
1280 bl dbg4byte /* Print */
1281 li r3,0x0A /* Linefeed */
1282 bl dbgDchar /* Send it */
1283 li r3,0x0D /* Carriage return */
1284 bl dbgDchar /* Send it */
1285
1286 li r3,0x20 /* Print eyecatcher */
1287 bl dbgDchar /* Send it */
1288 li r3,0x20 /* Print eyecatcher */
1289 bl dbgDchar /* Send it */
1290 li r3,0x20 /* Print eyecatcher */
1291 bl dbgDchar /* Send it */
1292 li r3,0x20 /* Print eyecatcher */
1293 bl dbgDchar /* Send it */
1294 li r3,0x20 /* Print eyecatcher */
1295 bl dbgDchar /* Send it */
1296 lwz r5,savesr4(r13) /* Do register */
1297 bl dbg4byte /* Print */
1298 lwz r5,savesr5(r13) /* Do register */
1299 bl dbg4byte /* Print */
1300 lwz r5,savesr6(r13) /* Do register */
1301 bl dbg4byte /* Print */
1302 lwz r5,savesr7(r13) /* Do register */
1303 bl dbg4byte /* Print */
1304 li r3,0x0A /* Linefeed */
1305 bl dbgDchar /* Send it */
1306 li r3,0x0D /* Carriage return */
1307 bl dbgDchar /* Send it */
1308
1309 li r3,0x20 /* Print eyecatcher */
1310 bl dbgDchar /* Send it */
1311 li r3,0x20 /* Print eyecatcher */
1312 bl dbgDchar /* Send it */
1313 li r3,0x20 /* Print eyecatcher */
1314 bl dbgDchar /* Send it */
1315 li r3,0x20 /* Print eyecatcher */
1316 bl dbgDchar /* Send it */
1317 li r3,0x20 /* Print eyecatcher */
1318 bl dbgDchar /* Send it */
1319 lwz r5,savesr8(r13) /* Do register */
1320 bl dbg4byte /* Print */
1321 lwz r5,savesr9(r13) /* Do register */
1322 bl dbg4byte /* Print */
1323 lwz r5,savesr10(r13) /* Do register */
1324 bl dbg4byte /* Print */
1325 lwz r5,savesr11(r13) /* Do register */
1326 bl dbg4byte /* Print */
1327 li r3,0x0A /* Linefeed */
1328 bl dbgDchar /* Send it */
1329 li r3,0x0D /* Carriage return */
1330 bl dbgDchar /* Send it */
1331
1332 li r3,0x20 /* Print eyecatcher */
1333 bl dbgDchar /* Send it */
1334 li r3,0x20 /* Print eyecatcher */
1335 bl dbgDchar /* Send it */
1336 li r3,0x20 /* Print eyecatcher */
1337 bl dbgDchar /* Send it */
1338 li r3,0x20 /* Print eyecatcher */
1339 bl dbgDchar /* Send it */
1340 li r3,0x20 /* Print eyecatcher */
1341 bl dbgDchar /* Send it */
1342 lwz r5,savesr12(r13) /* Do register */
1343 bl dbg4byte /* Print */
1344 lwz r5,savesr13(r13) /* Do register */
1345 bl dbg4byte /* Print */
1346 lwz r5,savesr14(r13) /* Do register */
1347 bl dbg4byte /* Print */
1348 lwz r5,savesr15(r13) /* Do register */
1349 bl dbg4byte /* Print */
1350 li r3,0x0A /* Linefeed */
1351 bl dbgDchar /* Send it */
1352 li r3,0x0D /* Carriage return */
1353 bl dbgDchar /* Send it */
1354
1355 li r3,0x30 /* Print eyecatcher */
1356 bl dbgDchar /* Send it */
1357 li r3,0x31 /* Print eyecatcher */
1358 bl dbgDchar /* Send it */
1359 li r3,0x64 /* Print eyecatcher */
1360 bl dbgDchar /* Send it */
1361 li r3,0x64 /* Print eyecatcher */
1362 bl dbgDchar /* Send it */
1363 li r3,0x20 /* Print eyecatcher */
1364 bl dbgDchar /* Send it */
1365 lwz r5,savesrr0(r13) /* Do register */
1366 bl dbg4byte /* Print */
1367 lwz r5,savesrr1(r13) /* Do register */
1368 bl dbg4byte /* Print */
1369 lwz r5,savedar(r13) /* Do register */
1370 bl dbg4byte /* Print */
1371 lwz r5,savedsisr(r13) /* Do register */
1372 bl dbg4byte /* Print */
1373 li r3,0x0A /* Linefeed */
1374 bl dbgDchar /* Send it */
1375 li r3,0x0D /* Carriage return */
1376 bl dbgDchar /* Send it */
1377
1378 li r3,0x20 /* Print eyecatcher */
1379 bl dbgDchar /* Send it */
1380 li r3,0x6C /* Print eyecatcher */
1381 bl dbgDchar /* Send it */
1382 li r3,0x63 /* Print eyecatcher */
1383 bl dbgDchar /* Send it */
1384 li r3,0x63 /* Print eyecatcher */
1385 bl dbgDchar /* Send it */
1386 li r3,0x20 /* Print eyecatcher */
1387 bl dbgDchar /* Send it */
1388 lwz r5,savelr(r13) /* Do register */
1389 bl dbg4byte /* Print */
1390 lwz r5,savecr(r13) /* Do register */
1391 bl dbg4byte /* Print */
1392 lwz r5,savectr(r13) /* Do register */
1393 bl dbg4byte /* Print */
1394 li r3,0x0A /* Linefeed */
1395 bl dbgDchar /* Send it */
1396 li r3,0x0D /* Carriage return */
1397 bl dbgDchar /* Send it */
1398 mtlr r11 /* Get back the return */
1399 dcbi 0,r10 /* ? */
1400 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1401 li r7,0 /* Get a zero */
1402 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1403 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1404 #endif
1405 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1406 li r7,0 /* Get a zero */
1407 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1408 stw r7,0(r3) /* Clear display lock */
1409 mtmsr r8 /* Restore the MSR */
1410 isync /* Wait for it */
1411 blr /* Leave... */
1412
1413
1414 /*
1415 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes).
1416 * Mapping is V=R. Stores and loads are real.
1417 */
1418
1419 ENTRY(dbgCkpt, TAG_NO_FRAME_USED)
1420
1421 mr r12,r0 /* Keep R0 pristene */
1422 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */
1423 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */
1424
1425 sc /* Go stash the stuff */
1426
1427 mr r0,r12 /* Restore R0 */
1428 blr /* Return... */
1429
1430 /* Here's the low-level part of dbgCkpt */
1431
1432 ENTRY(dbgCkptLL, TAG_NO_FRAME_USED)
1433
1434 li r12,0x380 /* Point to output area */
1435 li r1,32 /* Get line size */
1436 dcbz 0,r12 /* Make sure we don't fetch a cache line */
1437
1438 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1439
1440 dcbt r1,r3 /* Start in the next line */
1441
1442 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1443 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1444 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1445 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1446 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1447 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1448 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1449
1450 add r3,r3,r1 /* Bump input */
1451
1452 stw r4,0x00(r12) /* Store it */
1453 stw r5,0x04(r12) /* Store it */
1454 stw r6,0x08(r12) /* Store it */
1455 stw r7,0x0C(r12) /* Store it */
1456 stw r8,0x10(r12) /* Store it */
1457 stw r9,0x14(r12) /* Store it */
1458 stw r10,0x18(r12) /* Store it */
1459 stw r11,0x1C(r12) /* Store it */
1460
1461 dcbz r1,r12 /* Clear the next line */
1462 add r12,r12,r1 /* Point to next output line */
1463
1464 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1465 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1466 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1467 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1468 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1469 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1470 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1471 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1472
1473 dcbt r1,r3 /* Touch the next line */
1474 add r3,r3,r1 /* Point to next input line */
1475
1476 stw r4,0x00(r12) /* Store it */
1477 stw r5,0x04(r12) /* Store it */
1478 stw r6,0x08(r12) /* Store it */
1479 stw r7,0x0C(r12) /* Store it */
1480 stw r8,0x10(r12) /* Store it */
1481 stw r9,0x14(r12) /* Store it */
1482 stw r10,0x18(r12) /* Store it */
1483 stw r11,0x1C(r12) /* Store it */
1484
1485 dcbz r1,r12 /* Clear the next line */
1486 add r12,r12,r1 /* Point to next output line */
1487
1488 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1489 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1490 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1491 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1492 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1493 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1494 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1495 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1496
1497 dcbt r1,r3 /* Touch the next line */
1498 add r3,r3,r1 /* Point to next input line */
1499
1500 stw r4,0x00(r12) /* Store it */
1501 stw r5,0x04(r12) /* Store it */
1502 stw r6,0x08(r12) /* Store it */
1503 stw r7,0x0C(r12) /* Store it */
1504 stw r8,0x10(r12) /* Store it */
1505 stw r9,0x14(r12) /* Store it */
1506 stw r10,0x18(r12) /* Store it */
1507 stw r11,0x1C(r12) /* Store it */
1508
1509 dcbz r1,r12 /* Clear the next line */
1510 add r12,r12,r1 /* Point to next output line */
1511
1512 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1513 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1514 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1515 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1516 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1517 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1518 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1519 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1520
1521 stw r4,0x00(r12) /* Store it */
1522 stw r5,0x04(r12) /* Store it */
1523 stw r6,0x08(r12) /* Store it */
1524 stw r7,0x0C(r12) /* Store it */
1525 stw r8,0x10(r12) /* Store it */
1526 stw r9,0x14(r12) /* Store it */
1527 stw r10,0x18(r12) /* Store it */
1528 stw r11,0x1C(r12) /* Store it */
1529
1530 blr
1531
1532
1533 /*
1534 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur.
1535 */
1536
1537 ENTRY(DoPreemptLL, TAG_NO_FRAME_USED)
1538
1539 mfsprg r11,0 /* Get the per_proc address */
1540 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1541 li r3,T_PREEMPT /* Set preemption interrupt value */
1542 mtlr r11 /* Restore the LR */
1543 stw r3,saveexception(r13) /* Modify the exception type to preemption */
1544 blr /* Return to interrupt handler */
1545
1546
1547 /*
1548 * Force 'rupt handler to dispatch with new context
1549 * R3 at the call contains the new savearea.
1550 * R4 at the call contains a return code to pass back in R3.
1551 * Forces a T_CSWITCH
1552 */
1553
1554 ENTRY(SwitchContextLL, TAG_NO_FRAME_USED)
1555
1556 mfsprg r11,0 /* Get the per_proc address */
1557 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1558 li r3,T_CSWITCH /* Set context switch value */
1559 mtlr r11 /* Restore the LR */
1560 stw r3,saveexception(r13) /* Modify the exception type to switch context */
1561 blr /* Return to interrupt handler */
1562
1563
1564 /*
1565 * Create a fake I/O 'rupt.
1566 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred.
1567 */
1568
1569 ENTRY(CreateFakeIOLL, TAG_NO_FRAME_USED)
1570
1571 mfsprg r11,0 /* Get the per_proc address */
1572 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1573 li r3,T_INTERRUPT /* Set external interrupt value */
1574 mtlr r11 /* Restore the LR */
1575 stw r3,saveexception(r13) /* Modify the exception type to external */
1576 blr /* Return to interrupt handler */
1577
1578 /*
1579 * Create a shutdown context
1580 * Forces a T_SHUTDOWN trap.
1581 */
1582
1583 ENTRY(CreateShutdownCTXLL, TAG_NO_FRAME_USED)
1584
1585 mfsprg r11,0 /* Get the per_proc address */
1586 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1587 li r3,T_SHUTDOWN /* Set external interrupt value */
1588 mtlr r11 /* Restore the LR */
1589 stw r3,saveexception(r13) /* Modify the exception type to external */
1590 blr /* Return to interrupt handler */
1591
1592 /*
1593 * Create a fake decrementer 'rupt.
1594 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred.
1595 */
1596
1597 ENTRY(CreateFakeDECLL, TAG_NO_FRAME_USED)
1598
1599 mfsprg r11,0 /* Get the per_proc address */
1600 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1601 li r3,T_DECREMENTER /* Set decrementer interrupt value */
1602 mtlr r11 /* Restore the LR */
1603 stw r3,saveexception(r13) /* Modify the exception type to external */
1604 blr /* Return to interrupt handler */
1605
1606 /*
1607 * Choke the system. This is just a dummy for now,
1608 * but we'll eventually do something.
1609 */
1610
1611 ENTRY(DoChokeLL, TAG_NO_FRAME_USED)
1612
1613 BREAKPOINT_TRAP /* Dummy for now */
1614
1615 /*
1616 * Set the low level trace flags
1617 */
1618
1619 ENTRY(LLTraceSet, TAG_NO_FRAME_USED)
1620
1621 mfsprg r6,2 ; Get feature flags
1622 mfmsr r12 /* Get the MSR */
1623 mr r4,r3 /* Save the new value */
1624 andi. r3,r12,0x01C0 /* Clear interrupts and translation */
1625 mtcrf 0x04,r6 ; Set the features
1626 bt pfNoMSRirb,ltsNoMSR ; Use MSR...
1627
1628 mtmsr r3 ; Translation and all off
1629 isync ; Toss prefetch
1630 b ltsNoMSRx
1631
1632 ltsNoMSR: li r0,loadMSR ; Get the MSR setter SC
1633 sc ; Set it
1634
1635 ltsNoMSRx:
1636
1637 lis r5,hi16(EXT(trcWork)) ; Get trace area
1638 ori r5,r5,lo16(EXT(trcWork)) ; again
1639
1640 lwz r3,traceMask(r5) /* Get the old trace flags to pass back */
1641 stw r4,traceMask(r5) /* Replace with the new ones */
1642
1643 mtmsr r12 /* Restore the MSR */
1644 isync
1645
1646 blr /* Leave... */
1647
1648 #if 1
1649
1650 /*
1651 ; ***************************************************************************
1652 ;
1653 ; ----------------- Grateful Deb ----------------
1654 ;
1655 ; Debugging: direct draw into main screen menu bar
1656 ;
1657 ; Takes R4 value, converts it to hex characters and displays it.
1658 ;
1659 ; Gotta make sure the DCBST is done to force the pixels from the cache.
1660 ;
1661 ; Position is taken as column, row (0 based) from R3.
1662 ; Characters are from hexfont, and are 16x16 pixels.
1663 ;
1664 ; Only works with two processors so far
1665 ;
1666 ;
1667 ; ***************************************************************************
1668 */
1669
1670 #define GDfromright 20
1671 #define GDfontsize 16
1672
1673 ENTRY(GratefulDeb,TAG_NO_FRAME_USED)
1674 mfspr r6,pir /* Get the PIR */
1675 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */
1676 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */
1677 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */
1678 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */
1679 add r6,r6,r5 /* Point at our CPU's work area */
1680 mfmsr r5 /* Get that MSR */
1681 stmw r0,GDsave(r6) /* Save all registers */
1682 lwz r10,GDready(r6) /* See if we're all ready to go */
1683 ori r0,r5,0x2000 /* Turn on the floating point */
1684 mr r31,r6 /* Get a more sane base register */
1685 mr. r10,r10 /* Are we all set? */
1686 mtmsr r0 /* Enable floating point */
1687 isync
1688
1689 stfd f0,GDfp0(r31) /* Save FP */
1690 stfd f1,GDfp1(r31) /* Save FP */
1691 stfd f2,GDfp2(r31) /* Save FP */
1692 stfd f3,GDfp3(r31) /* Save FP */
1693
1694 beq- GDbailout /* Go and bail... */
1695
1696 rlwinm r25,r3,0,16,31 /* Isolate just the row number */
1697 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */
1698 rlwinm r3,r3,16,16,31 /* Isolate the column number */
1699 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */
1700 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */
1701 lwz r26,GDdepth(r31) /* Get the bit depth */
1702 mullw r25,r25,r9 /* get offset to the row to write in bytes */
1703 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */
1704 add r25,r28,r25 /* Physical address of row */
1705 mullw r3,r3,r24 /* Get byte offset to first output column */
1706
1707 li r9,32 /* Get the initial shift calc */
1708
1709 lis r20,HIGH_ADDR(hexfont) /* Point to the font */
1710
1711 li r18,GDfontsize /* Get the number of rows in the font */
1712 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */
1713 add r21,r25,r3 /* Physical address of top left output pixel */
1714 sub r9,r9,r26 /* Get right shift justifier for pixel size */
1715 li r7,32 /* Number of bits per word */
1716
1717 startNybble:
1718 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1719 li r19,8 /* Get the number of characters in a row */
1720
1721 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */
1722 rlwinm r4,r4,4,0,31 /* Rotate a nybble */
1723 add r10,r20,r10 /* Point to the character in the font */
1724
1725 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */
1726 lhz r15,0(r10) /* Get the next row of the font */
1727
1728 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */
1729 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */
1730 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */
1731
1732 slw r14,r14,r26 /* Make room for our pixel in a register */
1733 srw r17,r17,r9 /* Isolate one pixels worth of black or white */
1734 sub. r7,r7,r26 /* See how may bits are left */
1735 sub r16,r16,r26 /* Count how many bits are left to store for this row */
1736 or r14,r14,r17 /* Put in the pixel */
1737 bne+ notfull /* Finish rendering this word */
1738
1739 not r14,r14 /* Invert to black on white */
1740 stw r14,0(r6) /* Write out the word */
1741 li r7,32 /* Bit per word count */
1742 addi r6,r6,4 /* Point to the next word */
1743
1744 notfull: mr. r16,r16 /* Have we finished the whole character row? */
1745 bne+ rendrow /* Finish rendering the row */
1746
1747 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */
1748 bne+ getNybble /* Not yet... */
1749
1750 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1751 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */
1752 mr r14,r21 /* Get the frame buffer address */
1753
1754 // BREAKPOINT_TRAP
1755
1756 blitrow: lfd f0,0(r6) /* Load a line */
1757 lfd f1,8(r6)
1758 lfd f2,16(r6)
1759 lfd f3,24(r6)
1760
1761 stfd f0,0(r14) /* Blit a line */
1762 stfd f1,8(r14)
1763 stfd f2,16(r14)
1764 stfd f3,24(r14)
1765
1766 addi r6,r6,32 /* Next buffered line */
1767
1768 dcbst 0,r14 /* Force the line to the screen */
1769 sync /* Make sure the line is on it's way */
1770 eieio /* Make sure we beat the invalidate */
1771 dcbi 0,r14 /* Make sure we leave no paradox */
1772
1773 addic. r19,r19,-1 /* Done all lines yet? */
1774 addi r14,r14,32 /* Point to the next output */
1775 bne+ blitrow /* Nope, do it some more... */
1776
1777 addic. r18,r18,-1 /* Have we done all the rows in character yet? */
1778 addi r20,r20,2 /* Offset the font to the next row */
1779 add r21,r21,r27 /* Point to start of next row */
1780 bne+ startNybble /* Nope, go through the word one more time... */
1781
1782 GDbailout: mr r1,r31 /* Move the workarea base */
1783
1784 lfd f0,GDfp0(r31) /* Restore FP */
1785 lfd f1,GDfp1(r31) /* Restore FP */
1786 lfd f2,GDfp2(r31) /* Restore FP */
1787 lfd f3,GDfp3(r31) /* Restore FP */
1788
1789 mtmsr r5 /* Disable floating point */
1790 isync
1791
1792 lmw r3,GDsave+12(r1) /* Restore most registers */
1793 lwz r0,GDsave(r1) /* Restore R0 */
1794 lwz r1,GDsave+4(r1) /* Finally, R1 */
1795 blr /* Leave... */
1796
1797
1798 /*
1799 * void GratefulDebDisp(unsigned int coord, unsigned int data);
1800 */
1801
1802
1803 ENTRY(GratefulDebDisp,TAG_NO_FRAME_USED)
1804
1805 mfmsr r9 /* Save the current MSR */
1806 mflr r7 /* Save the return */
1807 andi. r8,r9,0x7FCF /* Clear interrupt and translation */
1808 mtmsr r8 /* Turn 'em really off */
1809 isync /* Make sure about the translation part */
1810 bl EXT(GratefulDeb) /* Display it */
1811 mtmsr r9 /* Restore interrupt and translation */
1812 mtlr r7 /* Restore return */
1813 isync /* Make sure */
1814 blr
1815
1816
1817 #endif
1818
1819 /*
1820 * void checkNMI(void);
1821 */
1822
1823
1824 ENTRY(checkNMI,TAG_NO_FRAME_USED)
1825
1826 mfmsr r9 /* Save it */
1827 andi. r8,r9,0x7FCF /* Clear it */
1828 mtmsr r8 /* Disable it */
1829 isync /* Fence it */
1830 lis r7,0xF300 /* Find it */
1831 ori r7,r7,0x0020 /* Find it */
1832 dcbi 0,r7 /* Toss it */
1833 sync /* Sync it */
1834 eieio /* Get it */
1835 lwz r6,0x000C(r7) /* Check it */
1836 eieio /* Fence it */
1837 dcbi 0,r7 /* Toss it */
1838 rlwinm. r4,r6,0,19,19 /* Check it */
1839 rlwinm r6,r6,0,20,18 /* Clear it */
1840 sync /* Sync it */
1841 eieio /* Fence it */
1842 beq+ xnonmi /* Branch on it */
1843
1844 stw r6,0x0008(r7) /* Reset it */
1845 sync /* Sync it */
1846 dcbi 0,r6 /* Toss it */
1847 eieio /* Fence it */
1848
1849 mtmsr r9 /* Restore it */
1850 isync /* Hold it */
1851
1852 BREAKPOINT_TRAP /* Kill it */
1853 blr /* Return from it */
1854
1855 xnonmi: /* Label it */
1856 mtmsr r9 /* Restore it */
1857 isync /* Hold it */
1858 blr /* Return from it */
1859
1860
1861 /*
1862 * Early debug code
1863 */
1864
1865 dumpr7: lis r9,HIGH_ADDR(hexTab) /* (TEST/DEBUG) */
1866 li r5,8 /* (TEST/DEBUG) */
1867 ori r9,r9,LOW_ADDR(hexTab) /* (TEST/DEBUG) */
1868
1869 dumpr7n: rlwinm r7,r7,4,0,31 /* (TEST/DEBUG) */
1870 mr r6,r7 /* (TEST/DEBUG) */
1871 andi. r6,r6,15 /* (TEST/DEBUG) */
1872 lbzx r6,r9,r6 /* (TEST/DEBUG) */
1873 lis r10,0xF301 /* (TEST/DEBUG) */
1874 ori r10,r10,0x2000 /* (TEST/DEBUG) */
1875
1876 #if 0
1877 xqrw2: eieio /* (TEST/DEBUG) */
1878 lbz r7,0(r10) /* (TEST/DEBUG) */
1879 dcbi 0,r10 /* (TEST/DEBUG) */
1880 sync /* (TEST/DEBUG) */
1881 andi. r7,r7,0x04 /* (TEST/DEBUG) */
1882 beq xqrw2 /* (TEST/DEBUG) */
1883 #endif
1884
1885 dcbf 0,r10 /* (TEST/DEBUG) */
1886 sync /* (TEST/DEBUG) */
1887 dcbi 0,r10 /* (TEST/DEBUG) */
1888 eieio /* (TEST/DEBUG) */
1889 stb r6,4(r10) /* (TEST/DEBUG) */
1890
1891 lis r6,10 /* (TEST/DEBUG) */
1892 dumpr7d: addi r6,r6,-1 /* (TEST/DEBUG) */
1893 mr. r6,r6 /* (TEST/DEBUG) */
1894 bne- dumpr7d /* (TEST/DEBUG) */
1895 dcbf 0,r10 /* (TEST/DEBUG) */
1896 sync /* (TEST/DEBUG) */
1897 dcbi 0,r10 /* (TEST/DEBUG) */
1898 eieio /* (TEST/DEBUG) */
1899
1900 addic. r5,r5,-1 /* (TEST/DEBUG) */
1901 bne+ dumpr7n /* (TEST/DEBUG) */
1902
1903 blr /* (TEST/DEBUG) */
1904
1905 ;
1906 ; Log a special entry in physical memory.
1907 ; This assumes that memory size has been significantly lowered using
1908 ; the maxmem boot option. The buffer starts just after the end of mem_size.
1909 ;
1910 ; This is absolutely for special tracing cases. Do not ever leave in...
1911 ;
1912
1913 ENTRY(dbgLog,TAG_NO_FRAME_USED)
1914
1915 li r11,0 ; Clear callers callers callers return
1916 li r10,0 ; Clear callers callers callers callers return
1917 li r9,0 ; Clear callers callers callers callers callers return
1918 lwz r2,0(r1) ; Get callers callers stack frame
1919 lis r0,0x4000 ; First invalid address
1920 lwz r12,8(r2) ; Get our callers return
1921 lwz r2,0(r2) ; Back chain
1922
1923 mr. r2,r2 ; End of chain?
1924 cmplw cr1,r2,r0 ; Valid kernel address?
1925 beq- nosavehere ; Yes, end of chain...
1926 bge- cr1,nosavehere ; No...
1927 lwz r11,8(r2) ; Get our callers return
1928 lwz r2,0(r2) ; Back chain
1929
1930 mr. r2,r2 ; End of chain?
1931 cmplw cr1,r2,r0 ; Valid kernel address?
1932 beq- nosavehere ; Yes, end of chain...
1933 bge- cr1,nosavehere ; No...
1934 lwz r10,8(r2) ; Get our callers return
1935 lwz r2,0(r2) ; Back chain
1936
1937 mr. r2,r2 ; End of chain?
1938 cmplw cr1,r2,r0 ; Valid kernel address?
1939 beq- nosavehere ; Yes, end of chain...
1940 bge- cr1,nosavehere ; No...
1941 lwz r9,8(r2) ; Get our callers return
1942
1943 nosavehere: mfmsr r8 ; Get the MSR
1944 lis r2,hi16(EXT(DebugWork)) ; High part of area
1945 lis r7,hi16(EXT(mem_actual)) ; High part of actual
1946 andi. r0,r8,0x7FCF ; Interrupts and translation off
1947 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
1948 mtmsr r0 ; Turn stuff off
1949 ori r7,r7,lo16(EXT(mem_actual)) ; Get the actual
1950 isync
1951
1952 lwz r0,4(r2) ; Get the flag
1953 mr. r0,r0 ; Should we log?
1954 lwz r0,0(r7) ; Get the end of memory
1955 lwz r7,0(r2) ; Get the position
1956 bne- waytoofar ; No logging...
1957 mr. r7,r7 ; Is this the first?
1958 bne+ gotspot ; Nope...
1959
1960 lis r7,hi16(EXT(mem_size)) ; High part of defined memory
1961 ori r7,r7,lo16(EXT(mem_size)) ; Low part of defined memory
1962 lwz r7,0(r7) ; Make it end of defined
1963
1964 gotspot: cmplw r7,r0 ; Do we fit in memory
1965 addi r0,r7,0x0020 ; Next slot
1966 bge- waytoofar ; No fit...
1967
1968 stw r0,0(r2) ; Set next time slot
1969 dcbz 0,r7 ; Zap it
1970
1971 stw r3,0(r7) ; First data
1972 li r3,32 ; Disp to next line
1973 stw r4,4(r7) ; Second data
1974 dcbz r3,r7 ; Zap it
1975 stw r5,8(r7) ; Third data
1976 stw r6,12(r7) ; Fourth data
1977
1978 stw r12,16(r7) ; Callers callers
1979 stw r11,20(r7) ; Callers callers caller
1980 stw r10,24(r7) ; Callers callers callers caller
1981 stw r9,28(r7) ; Callers callers callers callers caller
1982
1983 waytoofar: mtmsr r8 ; Back to normal
1984 isync
1985 blr
1986
1987 ;
1988 ; Same as the other, but no traceback and 16 byte entry
1989 ; Trashes R0, R2, R10, R12
1990 ;
1991
1992 .align 5
1993 .globl EXT(dbgLog2)
1994
1995 LEXT(dbgLog2)
1996
1997
1998 mfmsr r10 ; Get the MSR
1999 lis r2,hi16(EXT(DebugWork)) ; High part of area
2000 lis r12,hi16(EXT(mem_actual)) ; High part of actual
2001 andi. r0,r10,0x7FCF ; Interrupts and translation off
2002 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
2003 mtmsr r0 ; Turn stuff off
2004 ori r12,r12,lo16(EXT(mem_actual)) ; Get the actual
2005 isync
2006
2007 lwz r0,4(r2) ; Get the flag
2008 mr. r0,r0 ; Should we log?
2009 lwz r0,0(r12) ; Get the end of memory
2010 lwz r12,0(r2) ; Get the position
2011 bne- waytoofar2 ; No logging...
2012 mr. r12,r12 ; Is this the first?
2013 bne+ gotspot2 ; Nope...
2014
2015 lis r12,hi16(EXT(mem_size)) ; High part of defined memory
2016 ori r12,r12,lo16(EXT(mem_size)) ; Low part of defined memory
2017 lwz r12,0(r12) ; Make it end of defined
2018
2019 gotspot2: cmplw cr1,r12,r0 ; Do we fit in memory
2020 rlwinm. r0,r12,0,27,27 ; Are we on a new line?
2021 bge- cr1,waytoofar2 ; No fit...
2022 addi r0,r12,0x0010 ; Next slot
2023
2024 bne+ nonewline ; Not on a new line...
2025 dcbz br0,r12 ; Clear it so we do not fetch it
2026
2027 nonewline: cmplwi r3,68 ; Special place for time stamp?
2028
2029 stw r0,0(r2) ; Set next time slot
2030 bne+ nospcts ; Nope...
2031
2032 lwz r0,0x17C(br0) ; Get special saved time stamp
2033 b nospctt ; Skip...
2034
2035 nospcts: mftb r0 ; Get the current time
2036
2037 nospctt: stw r3,4(r12) ; First data
2038 stw r4,8(r12) ; Second data
2039 stw r5,12(r12) ; Third data
2040 stw r0,0(r12) ; Time stamp
2041
2042 waytoofar2: mtmsr r10 ; Back to normal
2043 isync
2044 blr
2045
2046
2047 ;
2048 ; Saves floating point registers
2049 ;
2050
2051 .align 5
2052 .globl EXT(stFloat)
2053
2054 LEXT(stFloat)
2055
2056 mfmsr r0 ; Save the MSR
2057 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2058 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
2059 mtmsr r4
2060 isync
2061
2062 stfd f0,0x00(r3)
2063 stfd f1,0x08(r3)
2064 stfd f2,0x10(r3)
2065 stfd f3,0x18(r3)
2066 stfd f4,0x20(r3)
2067 stfd f5,0x28(r3)
2068 stfd f6,0x30(r3)
2069 stfd f7,0x38(r3)
2070 stfd f8,0x40(r3)
2071 stfd f9,0x48(r3)
2072 stfd f10,0x50(r3)
2073 stfd f11,0x58(r3)
2074 stfd f12,0x60(r3)
2075 stfd f13,0x68(r3)
2076 stfd f14,0x70(r3)
2077 stfd f15,0x78(r3)
2078 stfd f16,0x80(r3)
2079 stfd f17,0x88(r3)
2080 stfd f18,0x90(r3)
2081 stfd f19,0x98(r3)
2082 stfd f20,0xA0(r3)
2083 stfd f21,0xA8(r3)
2084 stfd f22,0xB0(r3)
2085 stfd f23,0xB8(r3)
2086 stfd f24,0xC0(r3)
2087 stfd f25,0xC8(r3)
2088 stfd f26,0xD0(r3)
2089 stfd f27,0xD8(r3)
2090 stfd f28,0xE0(r3)
2091 stfd f29,0xE8(r3)
2092 stfd f30,0xF0(r3)
2093 stfd f31,0xF8(r3)
2094 mffs f0
2095 stfd f0,0x100(r3)
2096 lfd f0,0x00(r3)
2097 mtmsr r0
2098 isync
2099 blr
2100
2101
2102 ;
2103 ; Saves vector registers. Returns 0 if non-Altivec machine.
2104 ;
2105
2106 .align 5
2107 .globl EXT(stVectors)
2108
2109 LEXT(stVectors)
2110
2111 mfpvr r6 ; Get machine type
2112 mr r5,r3 ; Save area address
2113 rlwinm r6,r6,16,17,31 ; Rotate on it
2114 li r3,0 ; Assume failure
2115 cmplwi r6,PROCESSOR_VERSION_7400 ; Do we have Altivec?
2116 bltlr+ ; No...
2117
2118 mfmsr r0 ; Save the MSR
2119 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2120 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
2121 mtmsr r4
2122 isync
2123
2124 stvxl v0,0,r5
2125 addi r5,r5,16
2126 stvxl v1,0,r5
2127 addi r5,r5,16
2128 stvxl v2,0,r5
2129 addi r5,r5,16
2130 stvxl v3,0,r5
2131 addi r5,r5,16
2132 stvxl v4,0,r5
2133 addi r5,r5,16
2134 stvxl v5,0,r5
2135 addi r5,r5,16
2136 stvxl v6,0,r5
2137 addi r5,r5,16
2138 stvxl v7,0,r5
2139 addi r5,r5,16
2140 stvxl v8,0,r5
2141 addi r5,r5,16
2142 stvxl v9,0,r5
2143 addi r5,r5,16
2144 stvxl v10,0,r5
2145 addi r5,r5,16
2146 stvxl v11,0,r5
2147 addi r5,r5,16
2148 stvxl v12,0,r5
2149 addi r5,r5,16
2150 stvxl v13,0,r5
2151 addi r5,r5,16
2152 stvxl v14,0,r5
2153 addi r5,r5,16
2154 stvxl v15,0,r5
2155 addi r5,r5,16
2156 stvxl v16,0,r5
2157 addi r5,r5,16
2158 stvxl v17,0,r5
2159 addi r5,r5,16
2160 stvxl v18,0,r5
2161 addi r5,r5,16
2162 stvxl v19,0,r5
2163 addi r5,r5,16
2164 stvxl v20,0,r5
2165 addi r5,r5,16
2166 stvxl v21,0,r5
2167 addi r5,r5,16
2168 stvxl v22,0,r5
2169 addi r5,r5,16
2170 stvxl v23,0,r5
2171 addi r5,r5,16
2172 stvxl v24,0,r5
2173 addi r5,r5,16
2174 stvxl v25,0,r5
2175 addi r5,r5,16
2176 stvxl v26,0,r5
2177 addi r5,r5,16
2178 stvxl v27,0,r5
2179 addi r5,r5,16
2180 stvxl v28,0,r5
2181 addi r5,r5,16
2182 stvxl v29,0,r5
2183 addi r5,r5,16
2184 stvxl v30,0,r5
2185 addi r5,r5,16
2186 stvxl v31,0,r5
2187 mfvscr v31
2188 addi r6,r5,16
2189 stvxl v31,0,r6
2190 li r3,1
2191 lvxl v31,0,r5
2192 mtmsr r0
2193 isync
2194 blr
2195
2196
2197 ;
2198 ; Saves yet more registers
2199 ;
2200
2201 .align 5
2202 .globl EXT(stSpecrs)
2203
2204 LEXT(stSpecrs)
2205
2206 mfmsr r0 ; Save the MSR
2207 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2208 mtmsr r4
2209 isync
2210
2211 mfpvr r12
2212 stw r12,4(r3)
2213 rlwinm r12,r12,16,16,31
2214
2215 mfdbatu r4,0
2216 mfdbatl r5,0
2217 mfdbatu r6,1
2218 mfdbatl r7,1
2219 mfdbatu r8,2
2220 mfdbatl r9,2
2221 mfdbatu r10,3
2222 mfdbatl r11,3
2223 stw r4,8(r3)
2224 stw r5,12(r3)
2225 stw r6,16(r3)
2226 stw r7,20(r3)
2227 stw r8,24(r3)
2228 stw r9,28(r3)
2229 stw r10,32(r3)
2230 stw r11,36(r3)
2231
2232 mfibatu r4,0
2233 mfibatl r5,0
2234 mfibatu r6,1
2235 mfibatl r7,1
2236 mfibatu r8,2
2237 mfibatl r9,2
2238 mfibatu r10,3
2239 mfibatl r11,3
2240 stw r4,40(r3)
2241 stw r5,44(r3)
2242 stw r6,48(r3)
2243 stw r7,52(r3)
2244 stw r8,56(r3)
2245 stw r9,60(r3)
2246 stw r10,64(r3)
2247 stw r11,68(r3)
2248
2249 mfsprg r4,0
2250 mfsprg r5,1
2251 mfsprg r6,2
2252 mfsprg r7,3
2253 stw r4,72(r3)
2254 stw r5,76(r3)
2255 stw r6,80(r3)
2256 stw r7,84(r3)
2257
2258 mfsdr1 r4
2259 stw r4,88(r3)
2260
2261 la r4,92(r3)
2262 li r5,0
2263
2264 stSnsr: mfsrin r6,r5
2265 addis r5,r5,0x1000
2266 stw r6,0(r4)
2267 mr. r5,r5
2268 addi r4,r4,4
2269 bne+ stSnsr
2270
2271 cmplwi cr1,r12,PROCESSOR_VERSION_604e
2272 cmplwi cr5,r12,PROCESSOR_VERSION_604ev
2273 cror cr1_eq,cr1_eq,cr5_eq ; Set if 604 type
2274 cmplwi r12,PROCESSOR_VERSION_750
2275 mfspr r4,hid0
2276 stw r4,(39*4)(r3)
2277
2278 li r4,0
2279 li r5,0
2280 li r6,0
2281 li r7,0
2282 beq- cr1,before750
2283 blt- before750
2284
2285 mfspr r4,hid1
2286 mfspr r5,l2cr
2287 mfspr r6,msscr0
2288 mfspr r7,msscr1
2289
2290 before750: stw r4,(40*4)(r3)
2291 stw r6,(42*4)(r3)
2292 stw r5,(41*4)(r3)
2293 stw r7,(43*4)(r3)
2294
2295 li r4,0
2296 beq isis750
2297
2298 mfspr r4,pir
2299 isis750: stw r4,0(r3)
2300
2301 li r4,0
2302 li r5,0
2303 li r6,0
2304 li r7,0
2305 beq- cr1,b4750
2306 blt- b4750
2307
2308 mfspr r4,thrm1
2309 mfspr r5,thrm2
2310 mfspr r6,thrm3
2311 mfspr r7,ictc
2312
2313 b4750: stw r4,(44*4)(r3)
2314 stw r5,(45*4)(r3)
2315 stw r6,(46*4)(r3)
2316 stw r7,(47*4)(r3)
2317
2318 li r4,0
2319 cmplwi r12,PROCESSOR_VERSION_7400
2320 bne nnmax
2321
2322 mfpvr r5
2323 rlwinm r5,r5,0,16,31
2324 cmplwi r5,0x1101
2325 beq gnmax
2326 cmplwi r5,0x1102
2327 bne nnmax
2328
2329 gnmax: mfspr r4,1016
2330
2331 nnmax: stw r4,(48*4)(r3)
2332
2333 mtmsr r0
2334 isync
2335 blr
mirror of XNU