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1 /*
2 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23 /*
24 * @OSF_COPYRIGHT@
25 */
26
27 /* Miscellaneous constants and structures used by the exception
28 * handlers
29 */
30
31 #ifndef _PPC_EXCEPTION_H_
32 #define _PPC_EXCEPTION_H_
33
34 #include <ppc/savearea.h>
35
36 #ifndef ASSEMBLER
37
38 #include <mach_kdb.h>
39 #include <mach_kdp.h>
40
41 #include <mach/machine/vm_types.h>
42 #include <mach/boolean.h>
43 #include <kern/ast.h>
44 #include <kern/cpu_data.h>
45 #include <pexpert/pexpert.h>
46 #include <IOKit/IOInterrupts.h>
47 #include <ppc/machine_routines.h>
48 #include <ppc/pms.h>
49 #include <ppc/rtclock.h>
50
51 /* Per processor CPU features */
52 #pragma pack(4) /* Make sure the structure stays as we defined it */
53 struct procFeatures {
54 unsigned int Available; /* 0x000 */
55 #define pfFloat 0x80000000
56 #define pfFloatb 0
57 #define pfAltivec 0x40000000
58 #define pfAltivecb 1
59 #define pfAvJava 0x20000000
60 #define pfAvJavab 2
61 #define pfSMPcap 0x10000000
62 #define pfSMPcapb 3
63 #define pfCanSleep 0x08000000
64 #define pfCanSleepb 4
65 #define pfCanNap 0x04000000
66 #define pfCanNapb 5
67 #define pfCanDoze 0x02000000
68 #define pfCanDozeb 6
69 #define pfSlowNap 0x00400000
70 #define pfSlowNapb 9
71 #define pfNoMuMMCK 0x00200000
72 #define pfNoMuMMCKb 10
73 #define pfNoL2PFNap 0x00100000
74 #define pfNoL2PFNapb 11
75 #define pfSCOMFixUp 0x00080000
76 #define pfSCOMFixUpb 12
77 #define pfHasDcba 0x00040000
78 #define pfHasDcbab 13
79 #define pfL1fa 0x00010000
80 #define pfL1fab 15
81 #define pfL2 0x00008000
82 #define pfL2b 16
83 #define pfL2fa 0x00004000
84 #define pfL2fab 17
85 #define pfL2i 0x00002000
86 #define pfL2ib 18
87 #define pfLClck 0x00001000
88 #define pfLClckb 19
89 #define pfWillNap 0x00000800
90 #define pfWillNapb 20
91 #define pfNoMSRir 0x00000400
92 #define pfNoMSRirb 21
93 #define pfL3pdet 0x00000200
94 #define pfL3pdetb 22
95 #define pf128Byte 0x00000080
96 #define pf128Byteb 24
97 #define pf32Byte 0x00000020
98 #define pf32Byteb 26
99 #define pf64Bit 0x00000010
100 #define pf64Bitb 27
101 #define pfL3 0x00000004
102 #define pfL3b 29
103 #define pfL3fa 0x00000002
104 #define pfL3fab 30
105 #define pfValid 0x00000001
106 #define pfValidb 31
107 unsigned short rptdProc; /* 0x004 */
108 unsigned short lineSize; /* 0x006 */
109 unsigned int l1iSize; /* 0x008 */
110 unsigned int l1dSize; /* 0x00C */
111 unsigned int l2cr; /* 0x010 */
112 unsigned int l2Size; /* 0x014 */
113 unsigned int l3cr; /* 0x018 */
114 unsigned int l3Size; /* 0x01C */
115 unsigned int pfMSSCR0; /* 0x020 */
116 unsigned int pfMSSCR1; /* 0x024 */
117 unsigned int pfICTRL; /* 0x028 */
118 unsigned int pfLDSTCR; /* 0x02C */
119 unsigned int pfLDSTDB; /* 0x030 */
120 unsigned int pfMaxVAddr; /* 0x034 */
121 unsigned int pfMaxPAddr; /* 0x038 */
122 unsigned int pfPTEG; /* 0x03C */
123 uint64_t pfHID0; /* 0x040 */
124 uint64_t pfHID1; /* 0x048 */
125 uint64_t pfHID2; /* 0x050 */
126 uint64_t pfHID3; /* 0x058 */
127 uint64_t pfHID4; /* 0x060 */
128 uint64_t pfHID5; /* 0x068 */
129 unsigned int l2crOriginal; /* 0x070 */
130 unsigned int l3crOriginal; /* 0x074 */
131 unsigned int pfBootConfig; /* 0x078 */
132 unsigned int pfPowerModes; /* 0x07C */
133 #define pmDPLLVmin 0x00010000
134 #define pmDPLLVminb 15
135 #define pmType 0x000000FF
136 #define pmPowerTune 0x00000003
137 #define pmDFS 0x00000002
138 #define pmDualPLL 0x00000001
139 unsigned int pfPowerTune0; /* 0x080 */
140 unsigned int pfPowerTune1; /* 0x084 */
141 unsigned int rsrvd88[6]; /* 0x088 */
142 };
143 #pragma pack()
144
145 typedef struct procFeatures procFeatures;
146
147
148 /*
149 *
150 * Various performance counters
151 */
152 #pragma pack(4) /* Make sure the structure stays as we defined it */
153 struct hwCtrs {
154
155 unsigned int hwInVains; /* In vain */
156 unsigned int hwResets; /* Reset */
157 unsigned int hwMachineChecks; /* Machine check */
158 unsigned int hwDSIs; /* DSIs */
159 unsigned int hwISIs; /* ISIs */
160 unsigned int hwExternals; /* Externals */
161 unsigned int hwAlignments; /* Alignment */
162 unsigned int hwPrograms; /* Program */
163 unsigned int hwFloatPointUnavailable; /* Floating point */
164 unsigned int hwDecrementers; /* Decrementer */
165 unsigned int hwIOErrors; /* I/O error */
166 unsigned int hwrsvd0; /* Reserved */
167 unsigned int hwSystemCalls; /* System call */
168 unsigned int hwTraces; /* Trace */
169 unsigned int hwFloatingPointAssists; /* Floating point assist */
170 unsigned int hwPerformanceMonitors; /* Performance monitor */
171 unsigned int hwAltivecs; /* VMX */
172 unsigned int hwrsvd1; /* Reserved */
173 unsigned int hwrsvd2; /* Reserved */
174 unsigned int hwrsvd3; /* Reserved */
175 unsigned int hwInstBreakpoints; /* Instruction breakpoint */
176 unsigned int hwSystemManagements; /* System management */
177 unsigned int hwAltivecAssists; /* Altivec Assist */
178 unsigned int hwThermal; /* Thermals */
179 unsigned int hwrsvd5; /* Reserved */
180 unsigned int hwrsvd6; /* Reserved */
181 unsigned int hwrsvd7; /* Reserved */
182 unsigned int hwrsvd8; /* Reserved */
183 unsigned int hwrsvd9; /* Reserved */
184 unsigned int hwrsvd10; /* Reserved */
185 unsigned int hwrsvd11; /* Reserved */
186 unsigned int hwrsvd12; /* Reserved */
187 unsigned int hwrsvd13; /* Reserved */
188 unsigned int hwTrace601; /* Trace */
189 unsigned int hwSIGPs; /* SIGP */
190 unsigned int hwPreemptions; /* Preemption */
191 unsigned int hwContextSwitchs; /* Context switch */
192 unsigned int hwShutdowns; /* Shutdowns */
193 unsigned int hwChokes; /* System ABENDs */
194 unsigned int hwDataSegments; /* Data Segment Interruptions */
195 unsigned int hwInstructionSegments; /* Instruction Segment Interruptions */
196 unsigned int hwSoftPatches; /* Soft Patch interruptions */
197 unsigned int hwMaintenances; /* Maintenance interruptions */
198 unsigned int hwInstrumentations; /* Instrumentation interruptions */
199 unsigned int hwrsvd14; /* Reserved */
200 unsigned int hwhdec; /* 0B4 Hypervisor decrementer */
201
202 unsigned int hwspare0[11]; /* 0B8 Reserved */
203 unsigned int hwspare0a; /* 0E4 Reserved */
204 unsigned int hwspare0b; /* 0E8 Reserved */
205 unsigned int hwspare0c; /* 0EC Reserved */
206 unsigned int hwspare0d; /* 0F0 Reserved */
207 unsigned int hwIgnored; /* 0F4 Interruptions ignored */
208 unsigned int hwRedrives; /* 0F8 Number of redriven interrupts */
209 unsigned int hwSteals; /* 0FC Steals */
210 /* 100 */
211
212 unsigned int hwMckHang; /* ? */
213 unsigned int hwMckSLBPE; /* ? */
214 unsigned int hwMckTLBPE; /* ? */
215 unsigned int hwMckERCPE; /* ? */
216 unsigned int hwMckL1DPE; /* ? */
217 unsigned int hwMckL1TPE; /* ? */
218 unsigned int hwMckUE; /* ? */
219 unsigned int hwMckIUE; /* ? */
220 unsigned int hwMckIUEr; /* ? */
221 unsigned int hwMckDUE; /* ? */
222 unsigned int hwMckDTW; /* ? */
223 unsigned int hwMckUnk; /* ? */
224 unsigned int hwMckExt; /* ? */
225 unsigned int hwMckICachePE; /* ? */
226 unsigned int hwMckITagPE; /* ? */
227 unsigned int hwMckIEratPE; /* ? */
228 unsigned int hwMckDEratPE; /* ? */
229 unsigned int hwspare2[15]; /* Pad to next 128 bndry */
230 /* 0x180 */
231
232 unsigned int napStamp[2]; /* Time base when we napped */
233 unsigned int napTotal[2]; /* Total nap time in ticks */
234 unsigned int numSIGPast; /* Number of SIGP asts recieved */
235 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
236 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
237 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
238 unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
239 unsigned int numSIGPmast; /* Number of SIGPast messages merged */
240 unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
241
242 unsigned int hwWalkPhys; /* Number of entries to hw_walk_phys */
243 unsigned int hwWalkFull; /* Full purge of connected PTE's */
244 unsigned int hwWalkMerge; /* RC merge of connected PTE's */
245 unsigned int hwWalkQuick; /* Quick scan of connected PTE's */
246 unsigned int numSIGPcall; /* Number of SIGPcall messages received */
247
248 unsigned int hwspare3[16]; /* Pad to 512 */
249
250 };
251 #pragma pack()
252
253 typedef struct hwCtrs hwCtrs;
254
255 struct patch_entry {
256 unsigned int *addr;
257 unsigned int data;
258 unsigned int type;
259 unsigned int value;
260 };
261
262 typedef struct patch_entry patch_entry_t;
263
264 #define PATCH_INVALID 0
265 #define PATCH_PROCESSOR 1
266 #define PATCH_FEATURE 2
267 #define PATCH_END_OF_TABLE 3
268
269 #define PatchExt32 0x80000000
270 #define PatchExt32b 0
271 #define PatchLwsync 0x40000000
272 #define PatchLwsyncb 1
273
274 /* When an exception is taken, this info is accessed via sprg0 */
275 /* We should always have this one on a cache line boundary */
276
277 #pragma pack(4) /* Make sure the structure stays as we defined it */
278 struct per_proc_info {
279 unsigned short cpu_number;
280 unsigned short cpu_flags; /* Various low-level flags */
281 vm_offset_t istackptr;
282 vm_offset_t intstack_top_ss;
283
284 vm_offset_t debstackptr;
285 vm_offset_t debstack_top_ss;
286
287 unsigned int spcFlags; /* Special thread flags */
288 unsigned int old_thread;
289 ast_t pending_ast; /* mask of pending ast(s) */
290
291 /* PPC cache line boundary here - 020 */
292
293 int cpu_type;
294 int cpu_subtype;
295 int cpu_threadtype;
296 /*
297 * Note: the following two pairs of words need to stay in order and each pair must
298 * be in the same reservation (line) granule
299 */
300 struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
301 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
302 struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
303 unsigned int spcTRc; /* Special trace count */
304 unsigned int spcTRp; /* Special trace buffer pointer */
305
306 /* PPC cache line boundary here - 040 */
307 addr64_t quickfret; /* List of saveareas to release */
308 addr64_t lclfree; /* Pointer to local savearea list */
309 unsigned int lclfreecnt; /* Entries in local savearea list */
310 unsigned int holdQFret; /* Hold off releasing quickfret list */
311 uint64_t rtcPop; /* Real Time Clock pop */
312
313 /* PPC cache line boundary here - 060 */
314 boolean_t interrupts_enabled;
315 IOInterruptHandler interrupt_handler;
316 void * interrupt_nub;
317 unsigned int interrupt_source;
318 void * interrupt_target;
319 void * interrupt_refCon;
320 uint64_t next_savearea; /* pointer to the next savearea */
321
322 /* PPC cache line boundary here - 080 */
323 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
324 #define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass ) */
325 #define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
326 #define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
327 #define MPsigpAck 0x20000000 /* Ack Busy lock passed to receiving processor */
328 #define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
329 /* whomever set busy. When a busy is passed, */
330 /* this is the requestor of the function. */
331 #define MPsigpFunc 0x0000FF00 /* Current function */
332 #define MPsigpIdle 0x00 /* No function pending */
333 #define MPsigpSigp 0x04 /* Signal a processor */
334 unsigned int MPsigpParm0; /* SIGP parm 0 */
335 unsigned int MPsigpParm1; /* SIGP parm 1 */
336 unsigned int MPsigpParm2; /* SIGP parm 2 */
337 cpu_id_t cpu_id;
338 vm_offset_t start_paddr;
339 unsigned int ruptStamp[2]; /* Timebase at last interruption */
340
341 /* PPC cache line boundary here - 0A0 */
342 procFeatures pf; /* Processor features */
343
344 /* PPC cache line boundary here - 140 */
345 void * pp_cbfr;
346 void * pp_chud;
347 uint64_t rtclock_tick_deadline;
348 rtclock_timer_t rtclock_timer;
349 unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
350
351 /* PPC cache line boundary here - 160 */
352 struct savearea * db_saved_state;
353 time_base_enable_t time_base_enable;
354 int ppXFlags;
355 int running;
356 int debugger_is_slave;
357 int debugger_active;
358 int debugger_pending;
359 int debugger_holdoff;
360
361 /* PPC cache line boundary here - 180 */
362 uint64_t Uassist; /* User Assist DoubleWord */
363 uint64_t validSegs; /* Valid SR/STB slots */
364 addr64_t ppUserPmap; /* Current user state pmap (physical address) */
365 unsigned int ppUserPmapVirt; /* Current user state pmap (virtual address) */
366 unsigned int ppMapFlags; /* Mapping flags */
367
368 /* PPC cache line boundary here - 1A0 */
369 unsigned short ppInvSeg; /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
370 unsigned short ppCurSeg; /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
371 unsigned int ppSegSteal; /* Count of segment slot steals */
372 ppnum_t VMMareaPhys; /* vmm state page physical addr */
373 unsigned int VMMXAFlgs; /* vmm extended flags */
374 unsigned int FAMintercept; /* vmm FAM Exceptions to intercept */
375 unsigned int hibernate; /* wake from hibernate */
376 uint32_t save_tbl;
377 uint32_t save_tbu;
378
379 /* PPC cache line boundary here - 1C0 */
380 unsigned int ppUMWmp[16]; /* Linkage mapping for user memory window - 64 bytes */
381
382 /* PPC cache line boundary here - 200 */
383 uint64_t tempr0; /* temporary savearea */
384 uint64_t tempr1;
385 uint64_t tempr2;
386 uint64_t tempr3;
387
388 uint64_t tempr4;
389 uint64_t tempr5;
390 uint64_t tempr6;
391 uint64_t tempr7;
392
393 uint64_t tempr8;
394 uint64_t tempr9;
395 uint64_t tempr10;
396 uint64_t tempr11;
397
398 uint64_t tempr12;
399 uint64_t tempr13;
400 uint64_t tempr14;
401 uint64_t tempr15;
402
403 uint64_t tempr16;
404 uint64_t tempr17;
405 uint64_t tempr18;
406 uint64_t tempr19;
407
408 uint64_t tempr20;
409 uint64_t tempr21;
410 uint64_t tempr22;
411 uint64_t tempr23;
412
413 uint64_t tempr24;
414 uint64_t tempr25;
415 uint64_t tempr26;
416 uint64_t tempr27;
417
418 uint64_t tempr28;
419 uint64_t tempr29;
420 uint64_t tempr30;
421 uint64_t tempr31;
422
423
424 /* PPC cache line boundary here - 300 */
425 double emfp0; /* Copies of floating point registers */
426 double emfp1; /* Used for emulation purposes */
427 double emfp2;
428 double emfp3;
429
430 double emfp4;
431 double emfp5;
432 double emfp6;
433 double emfp7;
434
435 double emfp8;
436 double emfp9;
437 double emfp10;
438 double emfp11;
439
440 double emfp12;
441 double emfp13;
442 double emfp14;
443 double emfp15;
444
445 double emfp16;
446 double emfp17;
447 double emfp18;
448 double emfp19;
449
450 double emfp20;
451 double emfp21;
452 double emfp22;
453 double emfp23;
454
455 double emfp24;
456 double emfp25;
457 double emfp26;
458 double emfp27;
459
460 double emfp28;
461 double emfp29;
462 double emfp30;
463 double emfp31;
464
465 /* - 400 */
466 unsigned int emfpscr_pad;
467 unsigned int emfpscr;
468 unsigned int empadfp[6];
469
470 /* - 420 */
471 unsigned int emvr0[4]; /* Copies of vector registers used both */
472 unsigned int emvr1[4]; /* for full vector emulation or */
473 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
474 unsigned int emvr3[4];
475 unsigned int emvr4[4];
476 unsigned int emvr5[4];
477 unsigned int emvr6[4];
478 unsigned int emvr7[4];
479 unsigned int emvr8[4];
480 unsigned int emvr9[4];
481 unsigned int emvr10[4];
482 unsigned int emvr11[4];
483 unsigned int emvr12[4];
484 unsigned int emvr13[4];
485 unsigned int emvr14[4];
486 unsigned int emvr15[4];
487 unsigned int emvr16[4];
488 unsigned int emvr17[4];
489 unsigned int emvr18[4];
490 unsigned int emvr19[4];
491 unsigned int emvr20[4];
492 unsigned int emvr21[4];
493 unsigned int emvr22[4];
494 unsigned int emvr23[4];
495 unsigned int emvr24[4];
496 unsigned int emvr25[4];
497 unsigned int emvr26[4];
498 unsigned int emvr27[4];
499 unsigned int emvr28[4];
500 unsigned int emvr29[4];
501 unsigned int emvr30[4];
502 unsigned int emvr31[4];
503 unsigned int emvscr[4];
504 unsigned int empadvr[4];
505 /* - 640 */
506 /* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
507 addr64_t skipListPrev[28]; /* prev ptrs saved as side effect of calling mapSearchFull() */
508
509 /* - 720 */
510
511 unsigned int patcharea[56];
512 /* - 800 */
513
514 hwCtrs hwCtr; /* Hardware exception counters */
515 /* - A00 */
516 addr64_t pp2ndPage; /* Physical address of the second page of the per_proc */
517 uint32_t pprsvd0A08[6];
518 /* - A20 */
519 pmsd pms; /* Power Management Stepper control */
520 unsigned int pprsvd0A40[368]; /* Reserved out to next page boundary */
521 /* - 1000 */
522
523 /*
524 * This is the start of the second page of the per_proc block. Because we do not
525 * allocate physically contiguous memory, it may be physically discontiguous from the
526 * first page. Currently there isn't anything here that is accessed translation off,
527 * but if we need it, pp2ndPage contains the physical address.
528 *
529 * Note that the boot processor's per_proc is statically allocated, so it will be a
530 * V=R contiguous area. That allows access during early boot before we turn translation on
531 * for the first time.
532 */
533
534 unsigned int processor[384]; /* processor structure */
535
536 unsigned int pprsvd1[640]; /* Reserved out to next page boundary */
537 /* - 2000 */
538
539 };
540
541 #pragma pack()
542
543
544 /*
545 * Macro to convert a processor_t processor to its attached per_proc_info_t per_proc
546 */
547 #define PROCESSOR_TO_PER_PROC(x) \
548 ((struct per_proc_info*)((unsigned int)(x) \
549 - (unsigned int)(((struct per_proc_info *)0)->processor)))
550
551 extern struct per_proc_info BootProcInfo;
552
553 #define MAX_CPUS 256
554
555 struct per_proc_entry {
556 addr64_t ppe_paddr; /* Physical address of the first page of per_proc, 2nd is in pp2ndPage. */
557 unsigned int ppe_pad4[1];
558 struct per_proc_info *ppe_vaddr; /* Virtual address of the per_proc */
559 };
560
561 extern struct per_proc_entry PerProcTable[MAX_CPUS-1];
562
563
564 extern char *trap_type[];
565
566 #endif /* ndef ASSEMBLER */ /* with this savearea should be redriven */
567
568 /* cpu_flags defs */
569 #define SIGPactive 0x8000
570 #define needSRload 0x4000
571 #define turnEEon 0x2000
572 #define traceBE 0x1000 /* user mode BE tracing in enabled */
573 #define traceBEb 3 /* bit number for traceBE */
574 #define SleepState 0x0800
575 #define SleepStateb 4
576 #define mcountOff 0x0400
577 #define SignalReady 0x0200
578 #define BootDone 0x0100
579 #define loadMSR 0x7FF4
580
581 /* ppXFlags defs */
582 #define SignalReadyWait 0x00000001
583
584 #define T_VECTOR_SIZE 4 /* function pointer size */
585
586 /* Hardware exceptions */
587
588 #define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
589 #define T_RESET (0x01 * T_VECTOR_SIZE)
590 #define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
591 #define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
592 #define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
593 #define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
594 #define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
595 #define T_PROGRAM (0x07 * T_VECTOR_SIZE)
596 #define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
597 #define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
598 #define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
599 #define T_RESERVED (0x0b * T_VECTOR_SIZE)
600 #define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
601 #define T_TRACE (0x0d * T_VECTOR_SIZE)
602 #define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
603 #define T_PERF_MON (0x0f * T_VECTOR_SIZE)
604 #define T_VMX (0x10 * T_VECTOR_SIZE)
605 #define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
606 #define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
607 #define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
608 #define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
609 #define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
610 #define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
611 #define T_THERMAL (0x17 * T_VECTOR_SIZE)
612 #define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
613 #define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
614 #define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
615 #define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
616 #define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
617 #define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
618 #define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
619 #define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
620 #define T_EMULATE (0x20 * T_VECTOR_SIZE)
621
622 #define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
623
624 #define T_SIGP (0x22 * T_VECTOR_SIZE)
625 #define T_PREEMPT (0x23 * T_VECTOR_SIZE)
626 #define T_CSWITCH (0x24 * T_VECTOR_SIZE)
627 #define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
628 #define T_CHOKE (0x26 * T_VECTOR_SIZE)
629
630 #define T_DATA_SEGMENT (0x27 * T_VECTOR_SIZE)
631 #define T_INSTRUCTION_SEGMENT (0x28 * T_VECTOR_SIZE)
632
633 #define T_SOFT_PATCH (0x29 * T_VECTOR_SIZE)
634 #define T_MAINTENANCE (0x2A * T_VECTOR_SIZE)
635 #define T_INSTRUMENTATION (0x2B * T_VECTOR_SIZE)
636 #define T_ARCHDEP0 (0x2C * T_VECTOR_SIZE)
637 #define T_HDEC (0x2D * T_VECTOR_SIZE)
638
639 #define T_AST (0x100 * T_VECTOR_SIZE)
640 #define T_MAX T_CHOKE /* Maximum exception no */
641
642 #define T_FAM 0x00004000
643
644 #define EXCEPTION_VECTOR(exception) (exception * 0x100 / T_VECTOR_SIZE )
645
646 /*
647 * System choke (failure) codes
648 */
649
650 #define failDebug 0
651 #define failStack 1
652 #define failMapping 2
653 #define failContext 3
654 #define failNoSavearea 4
655 #define failSaveareaCorr 5
656 #define failBadLiveContext 6
657 #define failSkipLists 7
658 #define failUnalignedStk 8
659 #define failPmap 9
660 #define failTimeout 10
661
662 /* Always must be last - update failNames table in model_dep.c as well */
663 #define failUnknown 11
664
665 #ifndef ASSEMBLER
666
667 #pragma pack(4) /* Make sure the structure stays as we defined it */
668 typedef struct resethandler {
669 unsigned int type;
670 vm_offset_t call_paddr;
671 vm_offset_t arg__paddr;
672 } resethandler_t;
673 #pragma pack()
674
675 extern resethandler_t ResetHandler;
676
677 #endif
678
679 #define RESET_HANDLER_NULL 0x0
680 #define RESET_HANDLER_START 0x1
681 #define RESET_HANDLER_BUPOR 0x2
682 #define RESET_HANDLER_IGNORE 0x3
683
684 #endif /* _PPC_EXCEPTION_H_ */
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