osfmk/mach/i386/fp_reg.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. Please obtain a copy of the License at
  10  * http://www.opensource.apple.com/apsl/ and read it before using this
  11  * file.
  12  *
  13  * The Original Code and all software distributed under the License are
  14  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  16  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  18  * Please see the License for the specific language governing rights and
  19  * limitations under the License.
  20  *
  21  * @APPLE_LICENSE_HEADER_END@
  22  */
  23 /*
  24  * @OSF_COPYRIGHT@
  25  */
  26 /*
  27  * Mach Operating System
  28  * Copyright (c) 1992-1989 Carnegie Mellon University
  29  * All Rights Reserved.
  30  *
  31  * Permission to use, copy, modify and distribute this software and its
  32  * documentation is hereby granted, provided that both the copyright
  33  * notice and this permission notice appear in all copies of the
  34  * software, derivative works or modified versions, and any portions
  35  * thereof, and that both notices appear in supporting documentation.
  36  *
  37  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  38  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  39  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  40  *
  41  * Carnegie Mellon requests users of this software to return to
  42  *
  43  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  44  *  School of Computer Science
  45  *  Carnegie Mellon University
  46  *  Pittsburgh PA 15213-3890
  47  *
  48  * any improvements or extensions that they make and grant Carnegie Mellon
  49  * the rights to redistribute these changes.
  50  */
  51 /*
  52  */
  53
  54 #ifndef _I386_FP_SAVE_H_
  55 #define _I386_FP_SAVE_H_
  56
  57 /*
  58  *      Floating point registers and status, as saved
  59  *      and restored by FP save/restore instructions.
  60  */
  61 struct i386_fp_save     {
  62         unsigned short  fp_control;     /* control */
  63         unsigned short  fp_unused_1;
  64         unsigned short  fp_status;      /* status */
  65         unsigned short  fp_unused_2;
  66         unsigned short  fp_tag;         /* register tags */
  67         unsigned short  fp_unused_3;
  68         unsigned int    fp_eip;         /* eip at failed instruction */
  69         unsigned short  fp_cs;          /* cs at failed instruction */
  70         unsigned short  fp_opcode;      /* opcode of failed instruction */
  71         unsigned int    fp_dp;          /* data address */
  72         unsigned short  fp_ds;          /* data segment */
  73         unsigned short  fp_unused_4;
  74 };
  75
  76 struct i386_fp_regs {
  77         unsigned short  fp_reg_word[5][8];
  78                                         /* space for 8 80-bit FP registers */
  79 };
  80
  81 /* note when allocating this data structure, it must be 16 byte aligned. */
  82 struct i386_fx_save {
  83         unsigned short  fx_control;     /* control */
  84         unsigned short  fx_status;      /* status */
  85         unsigned char   fx_tag;         /* register tags */
  86         unsigned char   fx_bbz1;        /* better be zero when calling fxrtstor */
  87         unsigned short  fx_opcode;
  88         unsigned int    fx_eip;         /* eip  instruction */
  89         unsigned short  fx_cs;          /* cs instruction */
  90         unsigned short  fx_bbz2;        /* better be zero when calling fxrtstor */
  91         unsigned int    fx_dp;          /* data address */
  92         unsigned short  fx_ds;          /* data segment */
  93         unsigned short  fx_bbz3;        /* better be zero when calling fxrtstor */
  94         unsigned int    fx_MXCSR;
  95         unsigned int    fx_MXCSR_MASK;
  96         unsigned short  fx_reg_word[8][8];      /* STx/MMx registers */
  97         unsigned short  fx_XMM_reg[8][8];       /* XMM0-XMM7 */
  98         unsigned char   fx_reserved[16*14];     /* reserved by intel for future expansion */
  99 };
 100
 101
 102 /*
 103  * Control register
 104  */
 105 #define FPC_IE          0x0001          /* enable invalid operation
 106                                            exception */
 107 #define FPC_IM          FPC_IE
 108 #define FPC_DE          0x0002          /* enable denormalized operation
 109                                            exception */
 110 #define FPC_DM          FPC_DE
 111 #define FPC_ZE          0x0004          /* enable zero-divide exception */
 112 #define FPC_ZM          FPC_ZE
 113 #define FPC_OE          0x0008          /* enable overflow exception */
 114 #define FPC_OM          FPC_OE
 115 #define FPC_UE          0x0010          /* enable underflow exception */
 116 #define FPC_PE          0x0020          /* enable precision exception */
 117 #define FPC_PC          0x0300          /* precision control: */
 118 #define FPC_PC_24       0x0000                  /* 24 bits */
 119 #define FPC_PC_53       0x0200                  /* 53 bits */
 120 #define FPC_PC_64       0x0300                  /* 64 bits */
 121 #define FPC_RC          0x0c00          /* rounding control: */
 122 #define FPC_RC_RN       0x0000                  /* round to nearest or even */
 123 #define FPC_RC_RD       0x0400                  /* round down */
 124 #define FPC_RC_RU       0x0800                  /* round up */
 125 #define FPC_RC_CHOP     0x0c00                  /* chop */
 126 #define FPC_IC          0x1000          /* infinity control (obsolete) */
 127 #define FPC_IC_PROJ     0x0000                  /* projective infinity */
 128 #define FPC_IC_AFF      0x1000                  /* affine infinity (std) */
 129
 130 /*
 131  * Status register
 132  */
 133 #define FPS_IE          0x0001          /* invalid operation */
 134 #define FPS_DE          0x0002          /* denormalized operand */
 135 #define FPS_ZE          0x0004          /* divide by zero */
 136 #define FPS_OE          0x0008          /* overflow */
 137 #define FPS_UE          0x0010          /* underflow */
 138 #define FPS_PE          0x0020          /* precision */
 139 #define FPS_SF          0x0040          /* stack flag */
 140 #define FPS_ES          0x0080          /* error summary */
 141 #define FPS_C0          0x0100          /* condition code bit 0 */
 142 #define FPS_C1          0x0200          /* condition code bit 1 */
 143 #define FPS_C2          0x0400          /* condition code bit 2 */
 144 #define FPS_TOS         0x3800          /* top-of-stack pointer */
 145 #define FPS_TOS_SHIFT   11
 146 #define FPS_C3          0x4000          /* condition code bit 3 */
 147 #define FPS_BUSY        0x8000          /* FPU busy */
 148
 149 /*
 150  * Kind of floating-point support provided by kernel.
 151  */
 152 #define FP_NO           0               /* no floating point */
 153 #define FP_SOFT         1               /* software FP emulator */
 154 #define FP_287          2               /* 80287 */
 155 #define FP_387          3               /* 80387 or 80486 */
 156 #define FP_FXSR         4               /* Fast save/restore SIMD Extension */
 157
 158 #endif  /* _I386_FP_SAVE_H_ */