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1 /*
2 * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
14 * agreement.
15 *
16 * Please obtain a copy of the License at
17 * http://www.opensource.apple.com/apsl/ and read it before using this
18 * file.
19 *
20 * The Original Code and all software distributed under the License are
21 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
23 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
25 * Please see the License for the specific language governing rights and
26 * limitations under the License.
27 *
28 * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
29 */
30 /*
31 * @OSF_COPYRIGHT@
32 */
33
34 /* Miscellaneous constants and structures used by the exception
35 * handlers
36 */
37
38 #ifndef _PPC_EXCEPTION_H_
39 #define _PPC_EXCEPTION_H_
40
41 #include <ppc/savearea.h>
42
43 #ifndef ASSEMBLER
44
45 #include <mach_kdb.h>
46 #include <mach_kdp.h>
47
48 #include <mach/machine/vm_types.h>
49 #include <mach/boolean.h>
50 #include <kern/ast.h>
51 #include <kern/cpu_data.h>
52 #include <pexpert/pexpert.h>
53 #include <IOKit/IOInterrupts.h>
54 #include <ppc/machine_routines.h>
55 #include <ppc/pms.h>
56 #include <ppc/rtclock.h>
57
58 /* Per processor CPU features */
59 #pragma pack(4) /* Make sure the structure stays as we defined it */
60 struct procFeatures {
61 unsigned int Available; /* 0x000 */
62 #define pfFloat 0x80000000
63 #define pfFloatb 0
64 #define pfAltivec 0x40000000
65 #define pfAltivecb 1
66 #define pfAvJava 0x20000000
67 #define pfAvJavab 2
68 #define pfSMPcap 0x10000000
69 #define pfSMPcapb 3
70 #define pfCanSleep 0x08000000
71 #define pfCanSleepb 4
72 #define pfCanNap 0x04000000
73 #define pfCanNapb 5
74 #define pfCanDoze 0x02000000
75 #define pfCanDozeb 6
76 #define pfSlowNap 0x00400000
77 #define pfSlowNapb 9
78 #define pfNoMuMMCK 0x00200000
79 #define pfNoMuMMCKb 10
80 #define pfNoL2PFNap 0x00100000
81 #define pfNoL2PFNapb 11
82 #define pfSCOMFixUp 0x00080000
83 #define pfSCOMFixUpb 12
84 #define pfHasDcba 0x00040000
85 #define pfHasDcbab 13
86 #define pfL1fa 0x00010000
87 #define pfL1fab 15
88 #define pfL2 0x00008000
89 #define pfL2b 16
90 #define pfL2fa 0x00004000
91 #define pfL2fab 17
92 #define pfL2i 0x00002000
93 #define pfL2ib 18
94 #define pfLClck 0x00001000
95 #define pfLClckb 19
96 #define pfWillNap 0x00000800
97 #define pfWillNapb 20
98 #define pfNoMSRir 0x00000400
99 #define pfNoMSRirb 21
100 #define pfL3pdet 0x00000200
101 #define pfL3pdetb 22
102 #define pf128Byte 0x00000080
103 #define pf128Byteb 24
104 #define pf32Byte 0x00000020
105 #define pf32Byteb 26
106 #define pf64Bit 0x00000010
107 #define pf64Bitb 27
108 #define pfL3 0x00000004
109 #define pfL3b 29
110 #define pfL3fa 0x00000002
111 #define pfL3fab 30
112 #define pfValid 0x00000001
113 #define pfValidb 31
114 unsigned short rptdProc; /* 0x004 */
115 unsigned short lineSize; /* 0x006 */
116 unsigned int l1iSize; /* 0x008 */
117 unsigned int l1dSize; /* 0x00C */
118 unsigned int l2cr; /* 0x010 */
119 unsigned int l2Size; /* 0x014 */
120 unsigned int l3cr; /* 0x018 */
121 unsigned int l3Size; /* 0x01C */
122 unsigned int pfMSSCR0; /* 0x020 */
123 unsigned int pfMSSCR1; /* 0x024 */
124 unsigned int pfICTRL; /* 0x028 */
125 unsigned int pfLDSTCR; /* 0x02C */
126 unsigned int pfLDSTDB; /* 0x030 */
127 unsigned int pfMaxVAddr; /* 0x034 */
128 unsigned int pfMaxPAddr; /* 0x038 */
129 unsigned int pfPTEG; /* 0x03C */
130 uint64_t pfHID0; /* 0x040 */
131 uint64_t pfHID1; /* 0x048 */
132 uint64_t pfHID2; /* 0x050 */
133 uint64_t pfHID3; /* 0x058 */
134 uint64_t pfHID4; /* 0x060 */
135 uint64_t pfHID5; /* 0x068 */
136 unsigned int l2crOriginal; /* 0x070 */
137 unsigned int l3crOriginal; /* 0x074 */
138 unsigned int pfBootConfig; /* 0x078 */
139 unsigned int pfPowerModes; /* 0x07C */
140 #define pmDPLLVmin 0x00010000
141 #define pmDPLLVminb 15
142 #define pmType 0x000000FF
143 #define pmPowerTune 0x00000003
144 #define pmDFS 0x00000002
145 #define pmDualPLL 0x00000001
146 unsigned int pfPowerTune0; /* 0x080 */
147 unsigned int pfPowerTune1; /* 0x084 */
148 unsigned int rsrvd88[6]; /* 0x088 */
149 };
150 #pragma pack()
151
152 typedef struct procFeatures procFeatures;
153
154
155 /*
156 *
157 * Various performance counters
158 */
159 #pragma pack(4) /* Make sure the structure stays as we defined it */
160 struct hwCtrs {
161
162 unsigned int hwInVains; /* In vain */
163 unsigned int hwResets; /* Reset */
164 unsigned int hwMachineChecks; /* Machine check */
165 unsigned int hwDSIs; /* DSIs */
166 unsigned int hwISIs; /* ISIs */
167 unsigned int hwExternals; /* Externals */
168 unsigned int hwAlignments; /* Alignment */
169 unsigned int hwPrograms; /* Program */
170 unsigned int hwFloatPointUnavailable; /* Floating point */
171 unsigned int hwDecrementers; /* Decrementer */
172 unsigned int hwIOErrors; /* I/O error */
173 unsigned int hwrsvd0; /* Reserved */
174 unsigned int hwSystemCalls; /* System call */
175 unsigned int hwTraces; /* Trace */
176 unsigned int hwFloatingPointAssists; /* Floating point assist */
177 unsigned int hwPerformanceMonitors; /* Performance monitor */
178 unsigned int hwAltivecs; /* VMX */
179 unsigned int hwrsvd1; /* Reserved */
180 unsigned int hwrsvd2; /* Reserved */
181 unsigned int hwrsvd3; /* Reserved */
182 unsigned int hwInstBreakpoints; /* Instruction breakpoint */
183 unsigned int hwSystemManagements; /* System management */
184 unsigned int hwAltivecAssists; /* Altivec Assist */
185 unsigned int hwThermal; /* Thermals */
186 unsigned int hwrsvd5; /* Reserved */
187 unsigned int hwrsvd6; /* Reserved */
188 unsigned int hwrsvd7; /* Reserved */
189 unsigned int hwrsvd8; /* Reserved */
190 unsigned int hwrsvd9; /* Reserved */
191 unsigned int hwrsvd10; /* Reserved */
192 unsigned int hwrsvd11; /* Reserved */
193 unsigned int hwrsvd12; /* Reserved */
194 unsigned int hwrsvd13; /* Reserved */
195 unsigned int hwTrace601; /* Trace */
196 unsigned int hwSIGPs; /* SIGP */
197 unsigned int hwPreemptions; /* Preemption */
198 unsigned int hwContextSwitchs; /* Context switch */
199 unsigned int hwShutdowns; /* Shutdowns */
200 unsigned int hwChokes; /* System ABENDs */
201 unsigned int hwDataSegments; /* Data Segment Interruptions */
202 unsigned int hwInstructionSegments; /* Instruction Segment Interruptions */
203 unsigned int hwSoftPatches; /* Soft Patch interruptions */
204 unsigned int hwMaintenances; /* Maintenance interruptions */
205 unsigned int hwInstrumentations; /* Instrumentation interruptions */
206 unsigned int hwrsvd14; /* Reserved */
207 unsigned int hwhdec; /* 0B4 Hypervisor decrementer */
208
209 unsigned int hwspare0[11]; /* 0B8 Reserved */
210 unsigned int hwspare0a; /* 0E4 Reserved */
211 unsigned int hwspare0b; /* 0E8 Reserved */
212 unsigned int hwspare0c; /* 0EC Reserved */
213 unsigned int hwspare0d; /* 0F0 Reserved */
214 unsigned int hwIgnored; /* 0F4 Interruptions ignored */
215 unsigned int hwRedrives; /* 0F8 Number of redriven interrupts */
216 unsigned int hwSteals; /* 0FC Steals */
217 /* 100 */
218
219 unsigned int hwMckHang; /* ? */
220 unsigned int hwMckSLBPE; /* ? */
221 unsigned int hwMckTLBPE; /* ? */
222 unsigned int hwMckERCPE; /* ? */
223 unsigned int hwMckL1DPE; /* ? */
224 unsigned int hwMckL1TPE; /* ? */
225 unsigned int hwMckUE; /* ? */
226 unsigned int hwMckIUE; /* ? */
227 unsigned int hwMckIUEr; /* ? */
228 unsigned int hwMckDUE; /* ? */
229 unsigned int hwMckDTW; /* ? */
230 unsigned int hwMckUnk; /* ? */
231 unsigned int hwMckExt; /* ? */
232 unsigned int hwMckICachePE; /* ? */
233 unsigned int hwMckITagPE; /* ? */
234 unsigned int hwMckIEratPE; /* ? */
235 unsigned int hwMckDEratPE; /* ? */
236 unsigned int hwspare2[15]; /* Pad to next 128 bndry */
237 /* 0x180 */
238
239 unsigned int napStamp[2]; /* Time base when we napped */
240 unsigned int napTotal[2]; /* Total nap time in ticks */
241 unsigned int numSIGPast; /* Number of SIGP asts recieved */
242 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
243 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
244 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
245 unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
246 unsigned int numSIGPmast; /* Number of SIGPast messages merged */
247 unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
248
249 unsigned int hwWalkPhys; /* Number of entries to hw_walk_phys */
250 unsigned int hwWalkFull; /* Full purge of connected PTE's */
251 unsigned int hwWalkMerge; /* RC merge of connected PTE's */
252 unsigned int hwWalkQuick; /* Quick scan of connected PTE's */
253 unsigned int numSIGPcall; /* Number of SIGPcall messages received */
254
255 unsigned int hwspare3[16]; /* Pad to 512 */
256
257 };
258 #pragma pack()
259
260 typedef struct hwCtrs hwCtrs;
261
262 struct patch_entry {
263 unsigned int *addr;
264 unsigned int data;
265 unsigned int type;
266 unsigned int value;
267 };
268
269 typedef struct patch_entry patch_entry_t;
270
271 #define PATCH_INVALID 0
272 #define PATCH_PROCESSOR 1
273 #define PATCH_FEATURE 2
274 #define PATCH_END_OF_TABLE 3
275
276 #define PatchExt32 0x80000000
277 #define PatchExt32b 0
278 #define PatchLwsync 0x40000000
279 #define PatchLwsyncb 1
280
281 /* When an exception is taken, this info is accessed via sprg0 */
282 /* We should always have this one on a cache line boundary */
283
284 #pragma pack(4) /* Make sure the structure stays as we defined it */
285 struct per_proc_info {
286 unsigned short cpu_number;
287 unsigned short cpu_flags; /* Various low-level flags */
288 vm_offset_t istackptr;
289 vm_offset_t intstack_top_ss;
290
291 vm_offset_t debstackptr;
292 vm_offset_t debstack_top_ss;
293
294 unsigned int spcFlags; /* Special thread flags */
295 unsigned int old_thread;
296 ast_t pending_ast; /* mask of pending ast(s) */
297
298 /* PPC cache line boundary here - 020 */
299
300 int cpu_type;
301 int cpu_subtype;
302 int cpu_threadtype;
303 /*
304 * Note: the following two pairs of words need to stay in order and each pair must
305 * be in the same reservation (line) granule
306 */
307 struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
308 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
309 struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
310 unsigned int spcTRc; /* Special trace count */
311 unsigned int spcTRp; /* Special trace buffer pointer */
312
313 /* PPC cache line boundary here - 040 */
314 addr64_t quickfret; /* List of saveareas to release */
315 addr64_t lclfree; /* Pointer to local savearea list */
316 unsigned int lclfreecnt; /* Entries in local savearea list */
317 unsigned int holdQFret; /* Hold off releasing quickfret list */
318 uint64_t rtcPop; /* Real Time Clock pop */
319
320 /* PPC cache line boundary here - 060 */
321 boolean_t interrupts_enabled;
322 IOInterruptHandler interrupt_handler;
323 void * interrupt_nub;
324 unsigned int interrupt_source;
325 void * interrupt_target;
326 void * interrupt_refCon;
327 uint64_t next_savearea; /* pointer to the next savearea */
328
329 /* PPC cache line boundary here - 080 */
330 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
331 #define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass ) */
332 #define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
333 #define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
334 #define MPsigpAck 0x20000000 /* Ack Busy lock passed to receiving processor */
335 #define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
336 /* whomever set busy. When a busy is passed, */
337 /* this is the requestor of the function. */
338 #define MPsigpFunc 0x0000FF00 /* Current function */
339 #define MPsigpIdle 0x00 /* No function pending */
340 #define MPsigpSigp 0x04 /* Signal a processor */
341 unsigned int MPsigpParm0; /* SIGP parm 0 */
342 unsigned int MPsigpParm1; /* SIGP parm 1 */
343 unsigned int MPsigpParm2; /* SIGP parm 2 */
344 cpu_id_t cpu_id;
345 vm_offset_t start_paddr;
346 unsigned int ruptStamp[2]; /* Timebase at last interruption */
347
348 /* PPC cache line boundary here - 0A0 */
349 procFeatures pf; /* Processor features */
350
351 /* PPC cache line boundary here - 140 */
352 void * pp_cbfr;
353 void * pp_chud;
354 uint64_t rtclock_tick_deadline;
355 rtclock_timer_t rtclock_timer;
356 unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
357
358 /* PPC cache line boundary here - 160 */
359 struct savearea * db_saved_state;
360 time_base_enable_t time_base_enable;
361 int ppXFlags;
362 int running;
363 int debugger_is_slave;
364 int debugger_active;
365 int debugger_pending;
366 int debugger_holdoff;
367
368 /* PPC cache line boundary here - 180 */
369 uint64_t Uassist; /* User Assist DoubleWord */
370 uint64_t validSegs; /* Valid SR/STB slots */
371 addr64_t ppUserPmap; /* Current user state pmap (physical address) */
372 unsigned int ppUserPmapVirt; /* Current user state pmap (virtual address) */
373 unsigned int ppMapFlags; /* Mapping flags */
374
375 /* PPC cache line boundary here - 1A0 */
376 unsigned short ppInvSeg; /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
377 unsigned short ppCurSeg; /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
378 unsigned int ppSegSteal; /* Count of segment slot steals */
379 ppnum_t VMMareaPhys; /* vmm state page physical addr */
380 unsigned int VMMXAFlgs; /* vmm extended flags */
381 unsigned int FAMintercept; /* vmm FAM Exceptions to intercept */
382 unsigned int hibernate; /* wake from hibernate */
383 uint32_t save_tbl;
384 uint32_t save_tbu;
385
386 /* PPC cache line boundary here - 1C0 */
387 unsigned int ppUMWmp[16]; /* Linkage mapping for user memory window - 64 bytes */
388
389 /* PPC cache line boundary here - 200 */
390 uint64_t tempr0; /* temporary savearea */
391 uint64_t tempr1;
392 uint64_t tempr2;
393 uint64_t tempr3;
394
395 uint64_t tempr4;
396 uint64_t tempr5;
397 uint64_t tempr6;
398 uint64_t tempr7;
399
400 uint64_t tempr8;
401 uint64_t tempr9;
402 uint64_t tempr10;
403 uint64_t tempr11;
404
405 uint64_t tempr12;
406 uint64_t tempr13;
407 uint64_t tempr14;
408 uint64_t tempr15;
409
410 uint64_t tempr16;
411 uint64_t tempr17;
412 uint64_t tempr18;
413 uint64_t tempr19;
414
415 uint64_t tempr20;
416 uint64_t tempr21;
417 uint64_t tempr22;
418 uint64_t tempr23;
419
420 uint64_t tempr24;
421 uint64_t tempr25;
422 uint64_t tempr26;
423 uint64_t tempr27;
424
425 uint64_t tempr28;
426 uint64_t tempr29;
427 uint64_t tempr30;
428 uint64_t tempr31;
429
430
431 /* PPC cache line boundary here - 300 */
432 double emfp0; /* Copies of floating point registers */
433 double emfp1; /* Used for emulation purposes */
434 double emfp2;
435 double emfp3;
436
437 double emfp4;
438 double emfp5;
439 double emfp6;
440 double emfp7;
441
442 double emfp8;
443 double emfp9;
444 double emfp10;
445 double emfp11;
446
447 double emfp12;
448 double emfp13;
449 double emfp14;
450 double emfp15;
451
452 double emfp16;
453 double emfp17;
454 double emfp18;
455 double emfp19;
456
457 double emfp20;
458 double emfp21;
459 double emfp22;
460 double emfp23;
461
462 double emfp24;
463 double emfp25;
464 double emfp26;
465 double emfp27;
466
467 double emfp28;
468 double emfp29;
469 double emfp30;
470 double emfp31;
471
472 /* - 400 */
473 unsigned int emfpscr_pad;
474 unsigned int emfpscr;
475 unsigned int empadfp[6];
476
477 /* - 420 */
478 unsigned int emvr0[4]; /* Copies of vector registers used both */
479 unsigned int emvr1[4]; /* for full vector emulation or */
480 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
481 unsigned int emvr3[4];
482 unsigned int emvr4[4];
483 unsigned int emvr5[4];
484 unsigned int emvr6[4];
485 unsigned int emvr7[4];
486 unsigned int emvr8[4];
487 unsigned int emvr9[4];
488 unsigned int emvr10[4];
489 unsigned int emvr11[4];
490 unsigned int emvr12[4];
491 unsigned int emvr13[4];
492 unsigned int emvr14[4];
493 unsigned int emvr15[4];
494 unsigned int emvr16[4];
495 unsigned int emvr17[4];
496 unsigned int emvr18[4];
497 unsigned int emvr19[4];
498 unsigned int emvr20[4];
499 unsigned int emvr21[4];
500 unsigned int emvr22[4];
501 unsigned int emvr23[4];
502 unsigned int emvr24[4];
503 unsigned int emvr25[4];
504 unsigned int emvr26[4];
505 unsigned int emvr27[4];
506 unsigned int emvr28[4];
507 unsigned int emvr29[4];
508 unsigned int emvr30[4];
509 unsigned int emvr31[4];
510 unsigned int emvscr[4];
511 unsigned int empadvr[4];
512 /* - 640 */
513 /* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
514 addr64_t skipListPrev[28]; /* prev ptrs saved as side effect of calling mapSearchFull() */
515
516 /* - 720 */
517
518 unsigned int patcharea[56];
519 /* - 800 */
520
521 hwCtrs hwCtr; /* Hardware exception counters */
522 /* - A00 */
523 addr64_t pp2ndPage; /* Physical address of the second page of the per_proc */
524 uint32_t pprsvd0A08[6];
525 /* - A20 */
526 pmsd pms; /* Power Management Stepper control */
527 unsigned int pprsvd0A40[368]; /* Reserved out to next page boundary */
528 /* - 1000 */
529
530 /*
531 * This is the start of the second page of the per_proc block. Because we do not
532 * allocate physically contiguous memory, it may be physically discontiguous from the
533 * first page. Currently there isn't anything here that is accessed translation off,
534 * but if we need it, pp2ndPage contains the physical address.
535 *
536 * Note that the boot processor's per_proc is statically allocated, so it will be a
537 * V=R contiguous area. That allows access during early boot before we turn translation on
538 * for the first time.
539 */
540
541 unsigned int processor[384]; /* processor structure */
542
543 unsigned int pprsvd1[640]; /* Reserved out to next page boundary */
544 /* - 2000 */
545
546 };
547
548 #pragma pack()
549
550
551 /*
552 * Macro to convert a processor_t processor to its attached per_proc_info_t per_proc
553 */
554 #define PROCESSOR_TO_PER_PROC(x) \
555 ((struct per_proc_info*)((unsigned int)(x) \
556 - (unsigned int)(((struct per_proc_info *)0)->processor)))
557
558 extern struct per_proc_info BootProcInfo;
559
560 #define MAX_CPUS 256
561
562 struct per_proc_entry {
563 addr64_t ppe_paddr; /* Physical address of the first page of per_proc, 2nd is in pp2ndPage. */
564 unsigned int ppe_pad4[1];
565 struct per_proc_info *ppe_vaddr; /* Virtual address of the per_proc */
566 };
567
568 extern struct per_proc_entry PerProcTable[MAX_CPUS-1];
569
570
571 extern char *trap_type[];
572
573 #endif /* ndef ASSEMBLER */ /* with this savearea should be redriven */
574
575 /* cpu_flags defs */
576 #define SIGPactive 0x8000
577 #define needSRload 0x4000
578 #define turnEEon 0x2000
579 #define traceBE 0x1000 /* user mode BE tracing in enabled */
580 #define traceBEb 3 /* bit number for traceBE */
581 #define SleepState 0x0800
582 #define SleepStateb 4
583 #define mcountOff 0x0400
584 #define SignalReady 0x0200
585 #define BootDone 0x0100
586 #define loadMSR 0x7FF4
587
588 /* ppXFlags defs */
589 #define SignalReadyWait 0x00000001
590
591 #define T_VECTOR_SIZE 4 /* function pointer size */
592
593 /* Hardware exceptions */
594
595 #define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
596 #define T_RESET (0x01 * T_VECTOR_SIZE)
597 #define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
598 #define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
599 #define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
600 #define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
601 #define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
602 #define T_PROGRAM (0x07 * T_VECTOR_SIZE)
603 #define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
604 #define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
605 #define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
606 #define T_RESERVED (0x0b * T_VECTOR_SIZE)
607 #define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
608 #define T_TRACE (0x0d * T_VECTOR_SIZE)
609 #define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
610 #define T_PERF_MON (0x0f * T_VECTOR_SIZE)
611 #define T_VMX (0x10 * T_VECTOR_SIZE)
612 #define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
613 #define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
614 #define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
615 #define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
616 #define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
617 #define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
618 #define T_THERMAL (0x17 * T_VECTOR_SIZE)
619 #define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
620 #define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
621 #define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
622 #define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
623 #define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
624 #define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
625 #define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
626 #define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
627 #define T_EMULATE (0x20 * T_VECTOR_SIZE)
628
629 #define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
630
631 #define T_SIGP (0x22 * T_VECTOR_SIZE)
632 #define T_PREEMPT (0x23 * T_VECTOR_SIZE)
633 #define T_CSWITCH (0x24 * T_VECTOR_SIZE)
634 #define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
635 #define T_CHOKE (0x26 * T_VECTOR_SIZE)
636
637 #define T_DATA_SEGMENT (0x27 * T_VECTOR_SIZE)
638 #define T_INSTRUCTION_SEGMENT (0x28 * T_VECTOR_SIZE)
639
640 #define T_SOFT_PATCH (0x29 * T_VECTOR_SIZE)
641 #define T_MAINTENANCE (0x2A * T_VECTOR_SIZE)
642 #define T_INSTRUMENTATION (0x2B * T_VECTOR_SIZE)
643 #define T_ARCHDEP0 (0x2C * T_VECTOR_SIZE)
644 #define T_HDEC (0x2D * T_VECTOR_SIZE)
645
646 #define T_AST (0x100 * T_VECTOR_SIZE)
647 #define T_MAX T_CHOKE /* Maximum exception no */
648
649 #define T_FAM 0x00004000
650
651 #define EXCEPTION_VECTOR(exception) (exception * 0x100 / T_VECTOR_SIZE )
652
653 /*
654 * System choke (failure) codes
655 */
656
657 #define failDebug 0
658 #define failStack 1
659 #define failMapping 2
660 #define failContext 3
661 #define failNoSavearea 4
662 #define failSaveareaCorr 5
663 #define failBadLiveContext 6
664 #define failSkipLists 7
665 #define failUnalignedStk 8
666 #define failPmap 9
667 #define failTimeout 10
668
669 /* Always must be last - update failNames table in model_dep.c as well */
670 #define failUnknown 11
671
672 #ifndef ASSEMBLER
673
674 #pragma pack(4) /* Make sure the structure stays as we defined it */
675 typedef struct resethandler {
676 unsigned int type;
677 vm_offset_t call_paddr;
678 vm_offset_t arg__paddr;
679 } resethandler_t;
680 #pragma pack()
681
682 extern resethandler_t ResetHandler;
683
684 #endif
685
686 #define RESET_HANDLER_NULL 0x0
687 #define RESET_HANDLER_START 0x1
688 #define RESET_HANDLER_BUPOR 0x2
689 #define RESET_HANDLER_IGNORE 0x3
690
691 #endif /* _PPC_EXCEPTION_H_ */
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